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minor update

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This commit is contained in:
Blaise Tine 2024-08-18 02:13:43 -07:00
parent a2b24b4ed0
commit 3612ceda80
3 changed files with 20 additions and 23 deletions
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15
hw/rtl/libs/VX_cyclic_arbiter.sv
View file

@ -40,17 +40,17 @@ module VX_cyclic_arbiter #(
localparam IS_POW2 = (1 << LOG_NUM_REQS) == NUM_REQS;
wire [LOG_NUM_REQS-1:0] grant_index_um, grant_index_ql;
wire [LOG_NUM_REQS-1:0] grant_index_um;
reg [LOG_NUM_REQS-1:0] grant_index_r;
always @(posedge clk) begin
if (reset) begin
grant_index_r <= '0;
end else if (grant_valid && grant_ready) begin
if (!IS_POW2 && grant_index_ql == LOG_NUM_REQS'(NUM_REQS-1)) begin
if (!IS_POW2 && grant_index == LOG_NUM_REQS'(NUM_REQS-1)) begin
grant_index_r <= '0;
end else begin
grant_index_r <= grant_index_ql + LOG_NUM_REQS'(1);
grant_index_r <= grant_index + LOG_NUM_REQS'(1);
end
end
end
@ -61,14 +61,11 @@ module VX_cyclic_arbiter #(
.data_in (requests),
`UNUSED_PIN (onehot_out),
.index_out (grant_index_um),
`UNUSED_PIN (valid_out)
.valid_out (grant_valid)
);
assign grant_index_ql = requests[grant_index_r] ? grant_index_r : grant_index_um;
assign grant_index = grant_index_ql;
assign grant_onehot = NUM_REQS'(1) << grant_index_ql;
assign grant_valid = (| requests);
assign grant_index = requests[grant_index_r] ? grant_index_r : grant_index_um;
assign grant_onehot = NUM_REQS'(1) << grant_index;
end

2
hw/rtl/libs/VX_priority_encoder.sv
View file

@ -53,7 +53,7 @@ module VX_priority_encoder #(
VX_scan #(
.N (N),
.OP (2)
.OP ("|")
) scan (
.data_in (reversed),
.data_out (scan_lo)

26
hw/rtl/libs/VX_scan.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -19,8 +19,8 @@
`TRACING_OFF
module VX_scan #(
parameter N = 1,
parameter OP = 0, // 0: XOR, 1: AND, 2: OR
parameter REVERSE = 0 // 0: LO->HI, 1: HI->LO
parameter `STRING OP = "^", // ^: XOR, &: AND, |: OR
parameter REVERSE = 0 // 0: LO->HI, 1: HI->LO
) (
input wire [N-1:0] data_in,
output wire [N-1:0] data_out
@ -28,7 +28,7 @@ module VX_scan #(
localparam LOGN = `CLOG2(N);
`IGNORE_UNOPTFLAT_BEGIN
wire [LOGN:0][N-1:0] t;
wire [LOGN:0][N-1:0] t;
`IGNORE_UNOPTFLAT_END
// reverses bits
@ -39,29 +39,29 @@ module VX_scan #(
end
// optimize for the common case of small and-scans
if ((N == 2) && (OP == 1)) begin
if ((N == 2) && (OP == "&")) begin
assign t[LOGN] = {t[0][1], &t[0][1:0]};
end else if ((N == 3) && (OP == 1)) begin
end else if ((N == 3) && (OP == "&")) begin
assign t[LOGN] = {t[0][2], &t[0][2:1], &t[0][2:0]};
end else if ((N == 4) && (OP == 1)) begin
end else if ((N == 4) && (OP == "&")) begin
assign t[LOGN] = {t[0][3], &t[0][3:2], &t[0][3:1], &t[0][3:0]};
end else begin
// general case
wire [N-1:0] fill;
for (genvar i = 0; i < LOGN; ++i) begin
wire [N-1:0] shifted = N'({fill, t[i]} >> (1<<i));
if (OP == 0) begin
if (OP == "^") begin
assign fill = {N{1'b0}};
assign t[i+1] = t[i] ^ shifted;
end else if (OP == 1) begin
end else if (OP == "&") begin
assign fill = {N{1'b1}};
assign t[i+1] = t[i] & shifted;
end else if (OP == 2) begin
end else if (OP == "|") begin
assign fill = {N{1'b0}};
assign t[i+1] = t[i] | shifted;
end
end
end
end
// reverse bits
if (REVERSE != 0) begin
@ -69,7 +69,7 @@ module VX_scan #(
end else begin
for (genvar i = 0; i < N; ++i) begin
assign data_out[i] = t[LOGN][N-1-i];
end
end
end
endmodule