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buffering core reset signal

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This commit is contained in:
Blaise Tine 2021-01-01 11:46:30 -08:00
parent 138db29310
commit 36602cfa6a
2 changed files with 37 additions and 12 deletions
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8
hw/rtl/VX_cluster.v
View file

@ -68,13 +68,19 @@ module VX_cluster #(
wire [`NUM_CORES-1:0] per_core_ebreak;
for (genvar i = 0; i < `NUM_CORES; i++) begin
reg core_reset;
always @(posedge clk) begin
core_reset <= reset;
end
VX_core #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) core (
`SCOPE_BIND_VX_cluster_core(i)
.clk (clk),
.reset (reset),
.reset (core_reset),
.dram_req_valid (per_core_dram_req_valid[i]),
.dram_req_rw (per_core_dram_req_rw [i]),

41
hw/rtl/libs/VX_pipe_register.v
View file

@ -18,24 +18,43 @@ module VX_pipe_register #(
`UNUSED_VAR (enable)
assign data_out = data_in;
end else if (DEPTH == 1) begin
reg [DATAW-1:0] value;
if (RESETW != 0) begin
always @(posedge clk) begin
if (reset) begin
value[DATAW-1:DATAW-RESETW] <= RESETW'(0);
end else if (enable) begin
value <= data_in;
end
end
end else begin
if (RESETW == 0) begin
`UNUSED_VAR (reset)
reg [DATAW-1:0] value;
always @(posedge clk) begin
if (enable) begin
value <= data_in;
end
end
assign data_out = value;
end else if (RESETW == DATAW) begin
reg [DATAW-1:0] value;
always @(posedge clk) begin
if (reset) begin
value <= RESETW'(0);
end else if (enable) begin
value <= data_in;
end
end
assign data_out = value;
end else begin
reg [DATAW-RESETW-1:0] value_d;
reg [RESETW-1:0] value_r;
always @(posedge clk) begin
if (reset) begin
value_r <= RESETW'(0);
end else if (enable) begin
value_r <= data_in[DATAW-1:DATAW-RESETW];
end
if (enable) begin
value_d <= data_in[DATAW-RESETW-1:0];
end
end
assign data_out = {value_r, value_d};
end
assign data_out = value;
end else begin
VX_shift_register #(
.DATAW (DATAW),