mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 13:57:17 -04:00
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
This commit is contained in:
Blaise Tine
commit
3837638a85
28 changed files with 2178 additions and 2143 deletions
11
.travis.yml
11
.travis.yml
|
|
@ -21,16 +21,7 @@ install:
|
|||
- make -s
|
||||
|
||||
script:
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||||
- ./ci/test_runtime.sh
|
||||
- ./ci/test_riscv_isa.sh
|
||||
- ./ci/test_opencl.sh
|
||||
- ./ci/test_driver.sh
|
||||
- ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1"
|
||||
- ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1"
|
||||
- ./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=demo --args="-n1"
|
||||
- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1"
|
||||
- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1"
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||||
- ./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=demo --args="-n1"
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||||
- ./ci/regresion.sh
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||||
|
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after_success:
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# Gather code coverage
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|
|
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|||
12
ci/regression.sh
Executable file
12
ci/regression.sh
Executable file
|
|
@ -0,0 +1,12 @@
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|||
#!/bin/bash
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./ci/test_runtime.sh
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||||
./ci/test_riscv_isa.sh
|
||||
./ci/test_opencl.sh
|
||||
./ci/test_driver.sh
|
||||
./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --perf --app=demo --args="-n1"
|
||||
./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --debug --app=demo --args="-n1"
|
||||
./ci/travis_run.py ./ci/blackbox.sh --driver=vlsim --cores=1 --scope --app=demo --args="-n1"
|
||||
./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --app=demo --args="-n1"
|
||||
./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --l2cache --app=demo --args="-n1"
|
||||
./ci/travis_run.py ./ci/blackbox.sh --driver=rtlsim --cores=2 --clusters=2 --l2cache --l3cache --app=demo --args="-n1"
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||||
|
|
@ -74,9 +74,9 @@ module VX_cluster #(
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VX_reset_relay #(
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.DEPTH (`NUM_CORES > 1)
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) reset_relay (
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.clk (clk),
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.reset (reset),
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.reset_out (core_reset)
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.clk (clk),
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.reset (reset),
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||||
.reset_o (core_reset)
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||||
);
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||||
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VX_core #(
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|
|
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|||
|
|
@ -133,9 +133,9 @@ module VX_ibuffer #(
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deq_wid_n = (!deq_fire || q_sizeMany[deq_wid]) ? deq_wid : ibuf_enq_if.wid;
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deq_instr_n = deq_fire ? (q_sizeMany[deq_wid] ? q_data_prev[deq_wid] : q_data_in) : q_data_out[deq_wid];
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end else begin
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deq_valid_n = (| schedule_table_n);
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deq_valid_n = (| schedule_table);
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for (integer i = 0; i < `NUM_WARPS; i++) begin
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if (schedule_table_n[i]) begin
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if (schedule_table[i]) begin
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deq_wid_n = `NW_BITS'(i);
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deq_instr_n = q_data_out[i];
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schedule_table_n[i] = 0;
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|
|
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|
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@ -86,9 +86,9 @@ module VX_mem_unit # (
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VX_reset_relay #(
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.NUM_NODES (2)
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) reset_relay (
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.clk (clk),
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.reset (reset),
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||||
.reset_out ({dcache_reset, icache_reset})
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||||
.clk (clk),
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||||
.reset (reset),
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.reset_o ({dcache_reset, icache_reset})
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||||
);
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VX_cache #(
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|
|
@ -214,9 +214,9 @@ module VX_mem_unit # (
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wire scache_reset;
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VX_reset_relay reset_relay (
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.clk (clk),
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.reset (reset),
|
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.reset_out (scache_reset)
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.clk (clk),
|
||||
.reset (reset),
|
||||
.reset_o (scache_reset)
|
||||
);
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|
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VX_shared_mem #(
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|
|
|
|||
|
|
@ -75,9 +75,9 @@ module Vortex (
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VX_reset_relay #(
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.DEPTH (`NUM_CLUSTERS > 1)
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) reset_relay (
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.clk (clk),
|
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.reset (reset),
|
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.reset_out (cluster_reset)
|
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.clk (clk),
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.reset (reset),
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.reset_o (cluster_reset)
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);
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VX_cluster #(
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|
|
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118
hw/rtl/cache/VX_bank.v
vendored
118
hw/rtl/cache/VX_bank.v
vendored
|
|
@ -2,18 +2,19 @@
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|||
|
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module VX_bank #(
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parameter CACHE_ID = 0,
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parameter BANK_ID = 0,
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parameter BANK_ID = 0,
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// Number of Word requests per cycle
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parameter NUM_REQS = 1,
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// Size of cache in bytes
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parameter CACHE_SIZE = 1,
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// Size of line inside a bank in bytes
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parameter CACHE_LINE_SIZE = 1,
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// Number of bankS
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parameter NUM_BANKS = 1,
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parameter NUM_BANKS = 1,
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// Size of a word in bytes
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parameter WORD_SIZE = 1,
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// Number of Word requests per cycle
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parameter NUM_REQS = 1,
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// Core Request Queue Size
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parameter CREQ_SIZE = 1,
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@ -55,8 +56,9 @@ module VX_bank #(
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input wire core_req_valid,
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input wire [`REQS_BITS-1:0] core_req_tid,
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input wire core_req_rw,
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input wire [`LINE_ADDR_WIDTH-1:0] core_req_addr,
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input wire [`WORD_SELECT_BITS-1:0] core_req_wsel,
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input wire [WORD_SIZE-1:0] core_req_byteen,
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input wire [`WORD_ADDR_WIDTH-1:0] core_req_addr,
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input wire [`WORD_WIDTH-1:0] core_req_data,
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input wire [CORE_TAG_WIDTH-1:0] core_req_tag,
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output wire core_req_ready,
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@ -94,41 +96,27 @@ module VX_bank #(
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wire creq_pop;
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wire creq_full, creq_empty;
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wire creq_rw;
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wire [`LINE_ADDR_WIDTH-1:0] creq_addr;
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wire [`WORD_SELECT_BITS-1:0] creq_wsel;
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wire [WORD_SIZE-1:0] creq_byteen;
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wire [`REQS_BITS-1:0] creq_tid;
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`IGNORE_WARNINGS_BEGIN
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wire [`WORD_ADDR_WIDTH-1:0] creq_addr;
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`IGNORE_WARNINGS_END
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wire [`LINE_ADDR_WIDTH-1:0] creq_line_addr;
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wire [`UP(`WORD_SELECT_BITS)-1:0] creq_wsel;
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wire [`WORD_WIDTH-1:0] creq_data;
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wire [CORE_TAG_WIDTH-1:0] creq_tag;
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wire [`REQS_BITS-1:0] creq_tid;
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wire creq_push = core_req_valid && core_req_ready;
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assign core_req_ready = !creq_full;
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if (BANK_ADDR_OFFSET == 0) begin
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assign creq_line_addr = `LINE_SELECT_ADDR0(creq_addr);
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end else begin
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assign creq_line_addr = `LINE_SELECT_ADDRX(creq_addr);
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end
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if (`WORD_SELECT_BITS != 0) begin
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assign creq_wsel = creq_addr[`WORD_SELECT_BITS-1:0];
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end else begin
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||||
assign creq_wsel = 0;
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end
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VX_fifo_queue #(
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.DATAW (CORE_TAG_WIDTH + `REQS_BITS + 1 + WORD_SIZE + `WORD_ADDR_WIDTH + `WORD_WIDTH),
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.SIZE (CREQ_SIZE)
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.DATAW (CORE_TAG_WIDTH + `REQS_BITS + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_BITS + WORD_SIZE + `WORD_WIDTH),
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.SIZE (CREQ_SIZE),
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.BUFFERED (1)
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) core_req_queue (
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.clk (clk),
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.reset (reset),
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.push (creq_push),
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.pop (creq_pop),
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.data_in ({core_req_tag, core_req_tid, core_req_rw, core_req_byteen, core_req_addr, core_req_data}),
|
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.data_out ({creq_tag, creq_tid, creq_rw, creq_byteen, creq_addr, creq_data}),
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.data_in ({core_req_tag, core_req_tid, core_req_rw, core_req_addr, core_req_wsel, core_req_byteen, core_req_data}),
|
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.data_out ({creq_tag, creq_tid, creq_rw, creq_addr, creq_wsel, creq_byteen, creq_data}),
|
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.empty (creq_empty),
|
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.full (creq_full),
|
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`UNUSED_PIN (alm_empty),
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|
|
@ -141,16 +129,14 @@ module VX_bank #(
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wire mshr_push;
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wire mshr_pending;
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wire mshr_valid;
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wire [`REQS_BITS-1:0] mshr_tid;
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wire [`LINE_ADDR_WIDTH-1:0] mshr_addr;
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wire [`UP(`WORD_SELECT_BITS)-1:0] mshr_wsel;
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wire [`WORD_WIDTH-1:0] mshr_data;
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wire [CORE_TAG_WIDTH-1:0] mshr_tag;
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wire mshr_rw;
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wire [`WORD_SELECT_BITS-1:0] mshr_wsel;
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wire [WORD_SIZE-1:0] mshr_byteen;
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wire [CORE_TAG_WIDTH-1:0] mshr_tag;
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wire [`REQS_BITS-1:0] mshr_tid;
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wire [`LINE_ADDR_WIDTH-1:0] addr_st0, addr_st1;
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wire [`UP(`WORD_SELECT_BITS)-1:0] wsel_st0, wsel_st1;
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wire [`WORD_SELECT_BITS-1:0] wsel_st0, wsel_st1;
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wire mem_rw_st0, mem_rw_st1;
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wire [WORD_SIZE-1:0] byteen_st0, byteen_st1;
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wire [`CACHE_LINE_WIDTH-1:0] data_st0, data_st1;
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@ -207,7 +193,7 @@ module VX_bank #(
|
|||
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||||
// we have a miss in mshr or entering it for the current address
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wire mshr_pending_sel = mshr_pending
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|| (is_miss_st1 && (creq_line_addr == addr_st1));
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|| (is_miss_st1 && (creq_addr == addr_st1));
|
||||
|
||||
`ifdef DBG_CACHE_REQ_INFO
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if (CORE_TAG_WIDTH != CORE_TAG_ID_BITS && CORE_TAG_ID_BITS != 0) begin
|
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|
|
@ -218,7 +204,7 @@ module VX_bank #(
|
|||
`endif
|
||||
|
||||
VX_pipe_register #(
|
||||
.DATAW (1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + 1 + WORD_SIZE + `CACHE_LINE_WIDTH + `REQS_BITS + CORE_TAG_WIDTH + 1 + 1),
|
||||
.DATAW (1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_BITS + 1 + WORD_SIZE + `CACHE_LINE_WIDTH + `REQS_BITS + CORE_TAG_WIDTH + 1 + 1),
|
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.RESETW (1)
|
||||
) pipe_reg0 (
|
||||
.clk (clk),
|
||||
|
|
@ -228,11 +214,11 @@ module VX_bank #(
|
|||
mshr_pop || drsq_pop || creq_pop,
|
||||
mshr_pop_unqual,
|
||||
drsq_pop_unqual,
|
||||
mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr : creq_line_addr),
|
||||
mshr_pop_unqual ? mshr_addr : (dram_rsp_valid ? dram_rsp_addr : creq_addr),
|
||||
mshr_pop_unqual ? mshr_wsel : creq_wsel,
|
||||
mshr_pop_unqual ? mshr_rw : creq_rw,
|
||||
mshr_pop_unqual ? 1'b0 : creq_rw,
|
||||
mshr_pop_unqual ? mshr_byteen : creq_byteen,
|
||||
mshr_pop_unqual ? {`WORDS_PER_LINE{mshr_data}} : (dram_rsp_valid ? dram_rsp_data : {`WORDS_PER_LINE{creq_data}}),
|
||||
dram_rsp_valid ? dram_rsp_data : {`WORDS_PER_LINE{creq_data}},
|
||||
mshr_pop_unqual ? mshr_tid : creq_tid,
|
||||
mshr_pop_unqual ? mshr_tag : creq_tag,
|
||||
mshr_pending_sel,
|
||||
|
|
@ -292,7 +278,7 @@ module VX_bank #(
|
|||
assign incoming_fill_st0 = dram_rsp_valid && (addr_st0 == dram_rsp_addr);
|
||||
|
||||
VX_pipe_register #(
|
||||
.DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `UP(`WORD_SELECT_BITS) + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + CORE_TAG_WIDTH),
|
||||
.DATAW (1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + `LINE_ADDR_WIDTH + `WORD_SELECT_BITS + `CACHE_LINE_WIDTH + 1 + WORD_SIZE + `REQS_BITS + CORE_TAG_WIDTH),
|
||||
.RESETW (1)
|
||||
) pipe_reg1 (
|
||||
.clk (clk),
|
||||
|
|
@ -367,7 +353,7 @@ module VX_bank #(
|
|||
wire mshr_init_ready_state = !miss_st1 || incoming_fill_qual_st1;
|
||||
|
||||
// use dram rsp or core req address to lookup the mshr
|
||||
wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = dram_rsp_valid ? dram_rsp_addr : creq_line_addr;
|
||||
wire [`LINE_ADDR_WIDTH-1:0] lookup_addr = dram_rsp_valid ? dram_rsp_addr : creq_addr;
|
||||
|
||||
VX_miss_resrv #(
|
||||
.BANK_ID (BANK_ID),
|
||||
|
|
@ -394,7 +380,7 @@ module VX_bank #(
|
|||
// enqueue
|
||||
.enqueue (mshr_push),
|
||||
.enqueue_addr (addr_st1),
|
||||
.enqueue_data ({data_st1[`WORD_WIDTH-1:0], req_tid_st1, tag_st1, mem_rw_st1, byteen_st1, wsel_st1}),
|
||||
.enqueue_data ({wsel_st1, byteen_st1, tag_st1, req_tid_st1}),
|
||||
.enqueue_is_mshr (is_mshr_st1),
|
||||
.enqueue_as_ready (mshr_init_ready_state),
|
||||
`UNUSED_PIN (enqueue_almfull),
|
||||
|
|
@ -409,7 +395,7 @@ module VX_bank #(
|
|||
.schedule (mshr_pop),
|
||||
.schedule_valid (mshr_valid),
|
||||
.schedule_addr (mshr_addr),
|
||||
.schedule_data ({mshr_data, mshr_tid, mshr_tag, mshr_rw, mshr_byteen, mshr_wsel}),
|
||||
.schedule_data ({mshr_wsel, mshr_byteen, mshr_tag, mshr_tid}),
|
||||
|
||||
// dequeue
|
||||
.dequeue (mshr_dequeue)
|
||||
|
|
@ -417,20 +403,22 @@ module VX_bank #(
|
|||
|
||||
// Enqueue core response
|
||||
|
||||
wire [`WORD_WIDTH-1:0] crsq_data;
|
||||
wire [CORE_TAG_WIDTH-1:0] crsq_tag;
|
||||
wire [`REQS_BITS-1:0] crsq_tid;
|
||||
wire crsq_empty;
|
||||
|
||||
assign crsq_push = valid_st1 && crsq_push_st1;
|
||||
assign crsq_pop = core_rsp_valid && core_rsp_ready;
|
||||
|
||||
wire [`REQS_BITS-1:0] crsq_tid_st1 = req_tid_st1;
|
||||
wire [CORE_TAG_WIDTH-1:0] crsq_tag_st1 = CORE_TAG_WIDTH'(tag_st1);
|
||||
wire [`WORD_WIDTH-1:0] crsq_data_st1;
|
||||
|
||||
if (`WORD_SELECT_BITS != 0) begin
|
||||
assign crsq_data_st1 = readdata_st1[wsel_st1 * `WORD_WIDTH +: `WORD_WIDTH];
|
||||
assign crsq_pop = core_rsp_valid && core_rsp_ready;
|
||||
|
||||
if (`WORD_SELECT_BITS != 0) begin
|
||||
assign crsq_data = readdata_st1[wsel_st1 * `WORD_WIDTH +: `WORD_WIDTH];
|
||||
end else begin
|
||||
assign crsq_data_st1 = readdata_st1;
|
||||
assign crsq_data = readdata_st1;
|
||||
end
|
||||
|
||||
assign crsq_tag = tag_st1;
|
||||
assign crsq_tid = req_tid_st1;
|
||||
|
||||
VX_fifo_queue #(
|
||||
.DATAW (`REQS_BITS + CORE_TAG_WIDTH + `WORD_WIDTH),
|
||||
|
|
@ -442,8 +430,8 @@ module VX_bank #(
|
|||
.reset (reset),
|
||||
.push (crsq_push),
|
||||
.pop (crsq_pop),
|
||||
.data_in ({crsq_tid_st1, crsq_tag_st1, crsq_data_st1}),
|
||||
.data_out ({core_rsp_tid, core_rsp_tag, core_rsp_data}),
|
||||
.data_in ({crsq_data, crsq_tag, crsq_tid}),
|
||||
.data_out ({core_rsp_data, core_rsp_tag, core_rsp_tid}),
|
||||
.empty (crsq_empty),
|
||||
.alm_full (crsq_alm_full),
|
||||
`UNUSED_PIN (full),
|
||||
|
|
@ -455,18 +443,16 @@ module VX_bank #(
|
|||
|
||||
// Enqueue DRAM request
|
||||
|
||||
wire dreq_empty;
|
||||
wire [CACHE_LINE_SIZE-1:0] dreq_byteen, dreq_byteen_unqual;
|
||||
wire [`LINE_ADDR_WIDTH-1:0] dreq_addr;
|
||||
wire [`CACHE_LINE_WIDTH-1:0] dreq_data;
|
||||
wire dreq_empty, writeback;
|
||||
|
||||
assign dreq_push = valid_st1 && dreq_push_st1;
|
||||
|
||||
assign dreq_pop = dram_req_valid && dram_req_ready;
|
||||
|
||||
wire writeback = WRITE_ENABLE && do_writeback_st1;
|
||||
|
||||
wire [`LINE_ADDR_WIDTH-1:0] dreq_addr = addr_st1;
|
||||
|
||||
wire [`CACHE_LINE_WIDTH-1:0] dreq_data;
|
||||
wire [CACHE_LINE_SIZE-1:0] dreq_byteen, dreq_byteen_unqual;
|
||||
assign writeback = WRITE_ENABLE && do_writeback_st1;
|
||||
|
||||
if (`WORD_SELECT_BITS != 0) begin
|
||||
for (genvar i = 0; i < `WORDS_PER_LINE; i++) begin
|
||||
|
|
@ -475,9 +461,10 @@ module VX_bank #(
|
|||
end else begin
|
||||
assign dreq_byteen_unqual = byteen_st1;
|
||||
end
|
||||
assign dreq_data = data_st1;
|
||||
|
||||
assign dreq_byteen = writeback ? dreq_byteen_unqual : {CACHE_LINE_SIZE{1'b1}};
|
||||
assign dreq_addr = addr_st1;
|
||||
assign dreq_data = data_st1;
|
||||
|
||||
VX_fifo_queue #(
|
||||
.DATAW (1 + CACHE_LINE_SIZE + `LINE_ADDR_WIDTH + `CACHE_LINE_WIDTH),
|
||||
|
|
@ -488,7 +475,7 @@ module VX_bank #(
|
|||
.reset (reset),
|
||||
.push (dreq_push),
|
||||
.pop (dreq_pop),
|
||||
.data_in ({writeback, dreq_byteen, dreq_addr, dreq_data}),
|
||||
.data_in ({writeback, dreq_byteen, dreq_addr, dreq_data}),
|
||||
.data_out ({dram_req_rw, dram_req_byteen, dram_req_addr, dram_req_data}),
|
||||
.empty (dreq_empty),
|
||||
.alm_full (dreq_alm_full),
|
||||
|
|
@ -535,10 +522,7 @@ module VX_bank #(
|
|||
$display("%t: cache%0d:%0d fill-rsp: addr=%0h, data=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(dram_rsp_addr, BANK_ID), dram_rsp_data);
|
||||
end
|
||||
if (mshr_pop) begin
|
||||
if (mshr_rw)
|
||||
$display("%t: cache%0d:%0d mshr-wr-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), mshr_tag, mshr_tid, mshr_byteen, mshr_data, debug_wid_sel, debug_pc_sel);
|
||||
else
|
||||
$display("%t: cache%0d:%0d mshr-rd-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), mshr_tag, mshr_tid, mshr_byteen, debug_wid_sel, debug_pc_sel);
|
||||
$display("%t: cache%0d:%0d mshr-rd-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), mshr_tag, mshr_tid, mshr_byteen, debug_wid_sel, debug_pc_sel);
|
||||
end
|
||||
if (creq_pop) begin
|
||||
if (creq_rw)
|
||||
|
|
@ -547,7 +531,7 @@ module VX_bank #(
|
|||
$display("%t: cache%0d:%0d core-rd-req: addr=%0h, tag=%0h, tid=%0d, byteen=%b, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st0, BANK_ID), creq_tag, creq_tid, creq_byteen, debug_wid_sel, debug_pc_sel);
|
||||
end
|
||||
if (crsq_push) begin
|
||||
$display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag_st1, crsq_tid_st1, crsq_data_st1, debug_wid_st1, debug_pc_st1);
|
||||
$display("%t: cache%0d:%0d core-rsp: addr=%0h, tag=%0h, tid=%0d, data=%0h, wid=%0d, PC=%0h", $time, CACHE_ID, BANK_ID, `LINE_TO_BYTE_ADDR(addr_st1, BANK_ID), crsq_tag, crsq_tid, crsq_data, debug_wid_st1, debug_pc_st1);
|
||||
end
|
||||
if (dreq_push) begin
|
||||
if (do_writeback_st1)
|
||||
|
|
|
|||
49
hw/rtl/cache/VX_cache.v
vendored
49
hw/rtl/cache/VX_cache.v
vendored
|
|
@ -3,16 +3,17 @@
|
|||
module VX_cache #(
|
||||
parameter CACHE_ID = 0,
|
||||
|
||||
// Number of Word requests per cycle
|
||||
parameter NUM_REQS = 4,
|
||||
|
||||
// Size of cache in bytes
|
||||
parameter CACHE_SIZE = 16384,
|
||||
// Size of line inside a bank in bytes
|
||||
parameter CACHE_LINE_SIZE = 64,
|
||||
// Number of banks
|
||||
parameter NUM_BANKS = 4,
|
||||
parameter NUM_BANKS = NUM_REQS,
|
||||
// Size of a word in bytes
|
||||
parameter WORD_SIZE = 4,
|
||||
// Number of Word requests per cycle
|
||||
parameter NUM_REQS = NUM_BANKS,
|
||||
|
||||
// Core Request Queue Size
|
||||
parameter CREQ_SIZE = 4,
|
||||
|
|
@ -51,8 +52,8 @@ module VX_cache #(
|
|||
// Core request
|
||||
input wire [NUM_REQS-1:0] core_req_valid,
|
||||
input wire [NUM_REQS-1:0] core_req_rw,
|
||||
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
|
||||
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
|
||||
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
|
||||
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
|
||||
input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
|
||||
output wire [NUM_REQS-1:0] core_req_ready,
|
||||
|
|
@ -87,18 +88,19 @@ module VX_cache #(
|
|||
`STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value"))
|
||||
|
||||
wire [NUM_BANKS-1:0] per_bank_core_req_valid;
|
||||
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid;
|
||||
wire [NUM_BANKS-1:0] per_bank_core_req_rw;
|
||||
wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr;
|
||||
wire [NUM_BANKS-1:0][`WORD_SELECT_BITS-1:0] per_bank_core_req_wsel;
|
||||
wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen;
|
||||
wire [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr;
|
||||
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag;
|
||||
wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data;
|
||||
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag;
|
||||
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid;
|
||||
wire [NUM_BANKS-1:0] per_bank_core_req_ready;
|
||||
|
||||
wire [NUM_BANKS-1:0] per_bank_core_rsp_valid;
|
||||
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid;
|
||||
wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data;
|
||||
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag;
|
||||
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid;
|
||||
wire [NUM_BANKS-1:0] per_bank_core_rsp_ready;
|
||||
|
||||
wire [NUM_BANKS-1:0] per_bank_dram_req_valid;
|
||||
|
|
@ -131,8 +133,9 @@ module VX_cache #(
|
|||
assign dram_rsp_ready = !drsq_full;
|
||||
|
||||
VX_fifo_queue #(
|
||||
.DATAW (DRAM_TAG_WIDTH + `CACHE_LINE_WIDTH),
|
||||
.SIZE (DRSQ_SIZE)
|
||||
.DATAW (DRAM_TAG_WIDTH + `CACHE_LINE_WIDTH),
|
||||
.SIZE (DRSQ_SIZE),
|
||||
.BUFFERED (1)
|
||||
) dram_rsp_queue (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
|
|
@ -184,23 +187,22 @@ module VX_cache #(
|
|||
.reset (reset),
|
||||
`ifdef PERF_ENABLE
|
||||
.bank_stalls(perf_cache_if.bank_stalls),
|
||||
`else
|
||||
`UNUSED_PIN (bank_stalls),
|
||||
`endif
|
||||
.core_req_valid (core_req_valid),
|
||||
.core_req_rw (core_req_rw),
|
||||
.core_req_byteen(core_req_byteen),
|
||||
.core_req_addr (core_req_addr),
|
||||
.core_req_byteen(core_req_byteen),
|
||||
.core_req_data (core_req_data),
|
||||
.core_req_tag (core_req_tag),
|
||||
.core_req_ready (core_req_ready),
|
||||
.per_bank_core_req_valid (per_bank_core_req_valid),
|
||||
.per_bank_core_req_tid (per_bank_core_req_tid),
|
||||
.per_bank_core_req_rw (per_bank_core_req_rw),
|
||||
.per_bank_core_req_byteen(per_bank_core_req_byteen),
|
||||
.per_bank_core_req_addr (per_bank_core_req_addr),
|
||||
.per_bank_core_req_tag (per_bank_core_req_tag),
|
||||
.per_bank_core_req_wsel (per_bank_core_req_wsel),
|
||||
.per_bank_core_req_byteen(per_bank_core_req_byteen),
|
||||
.per_bank_core_req_data (per_bank_core_req_data),
|
||||
.per_bank_core_req_tag (per_bank_core_req_tag),
|
||||
.per_bank_core_req_tid (per_bank_core_req_tid),
|
||||
.per_bank_core_req_ready (per_bank_core_req_ready)
|
||||
);
|
||||
|
||||
|
|
@ -208,12 +210,13 @@ module VX_cache #(
|
|||
|
||||
for (genvar i = 0; i < NUM_BANKS; i++) begin
|
||||
wire curr_bank_core_req_valid;
|
||||
wire [`REQS_BITS-1:0] curr_bank_core_req_tid;
|
||||
wire curr_bank_core_req_rw;
|
||||
wire [`LINE_ADDR_WIDTH-1:0] curr_bank_core_req_addr;
|
||||
wire [`WORD_SELECT_BITS-1:0] curr_bank_core_req_wsel;
|
||||
wire [WORD_SIZE-1:0] curr_bank_core_req_byteen;
|
||||
wire [`WORD_ADDR_WIDTH-1:0] curr_bank_core_req_addr;
|
||||
wire [CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
|
||||
wire [`WORD_WIDTH-1:0] curr_bank_core_req_data;
|
||||
wire [CORE_TAG_WIDTH-1:0] curr_bank_core_req_tag;
|
||||
wire [`REQS_BITS-1:0] curr_bank_core_req_tid;
|
||||
wire curr_bank_core_req_ready;
|
||||
|
||||
wire curr_bank_core_rsp_valid;
|
||||
|
|
@ -237,12 +240,13 @@ module VX_cache #(
|
|||
|
||||
// Core Req
|
||||
assign curr_bank_core_req_valid = per_bank_core_req_valid[i];
|
||||
assign curr_bank_core_req_tid = per_bank_core_req_tid[i];
|
||||
assign curr_bank_core_req_addr = per_bank_core_req_addr[i];
|
||||
assign curr_bank_core_req_rw = per_bank_core_req_rw[i];
|
||||
assign curr_bank_core_req_wsel = per_bank_core_req_wsel[i];
|
||||
assign curr_bank_core_req_byteen = per_bank_core_req_byteen[i];
|
||||
assign curr_bank_core_req_data = per_bank_core_req_data[i];
|
||||
assign curr_bank_core_req_tag = per_bank_core_req_tag[i];
|
||||
assign curr_bank_core_req_tid = per_bank_core_req_tid[i];
|
||||
assign per_bank_core_req_ready[i] = curr_bank_core_req_ready;
|
||||
|
||||
// Core WB
|
||||
|
|
@ -308,12 +312,13 @@ module VX_cache #(
|
|||
|
||||
// Core request
|
||||
.core_req_valid (curr_bank_core_req_valid),
|
||||
.core_req_tid (curr_bank_core_req_tid),
|
||||
.core_req_rw (curr_bank_core_req_rw),
|
||||
.core_req_byteen (curr_bank_core_req_byteen),
|
||||
.core_req_addr (curr_bank_core_req_addr),
|
||||
.core_req_wsel (curr_bank_core_req_wsel),
|
||||
.core_req_data (curr_bank_core_req_data),
|
||||
.core_req_tag (curr_bank_core_req_tag),
|
||||
.core_req_tid (curr_bank_core_req_tid),
|
||||
.core_req_ready (curr_bank_core_req_ready),
|
||||
|
||||
// Core response
|
||||
|
|
@ -350,9 +355,9 @@ module VX_cache #(
|
|||
.clk (clk),
|
||||
.reset (reset),
|
||||
.per_bank_core_rsp_valid (per_bank_core_rsp_valid),
|
||||
.per_bank_core_rsp_data (per_bank_core_rsp_data),
|
||||
.per_bank_core_rsp_tag (per_bank_core_rsp_tag),
|
||||
.per_bank_core_rsp_tid (per_bank_core_rsp_tid),
|
||||
.per_bank_core_rsp_data (per_bank_core_rsp_data),
|
||||
.per_bank_core_rsp_ready (per_bank_core_rsp_ready),
|
||||
.core_rsp_valid (core_rsp_valid),
|
||||
.core_rsp_tag (core_rsp_tag),
|
||||
|
|
|
|||
9
hw/rtl/cache/VX_cache_config.vh
vendored
9
hw/rtl/cache/VX_cache_config.vh
vendored
|
|
@ -9,11 +9,11 @@
|
|||
|
||||
`define REQS_BITS `LOG2UP(NUM_REQS)
|
||||
|
||||
// tag rw byteen tid
|
||||
`define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + 1 + WORD_SIZE + `REQS_BITS)
|
||||
// tag byteen tid
|
||||
`define REQ_INST_META_WIDTH (CORE_TAG_WIDTH + WORD_SIZE + `REQS_BITS)
|
||||
|
||||
// data metadata word_sel
|
||||
`define MSHR_DATA_WIDTH (`WORD_WIDTH + `REQ_INST_META_WIDTH + `UP(`WORD_SELECT_BITS))
|
||||
// metadata word_sel
|
||||
`define MSHR_DATA_WIDTH (`REQ_INST_META_WIDTH + `WORD_SELECT_BITS)
|
||||
|
||||
`define WORD_WIDTH (8 * WORD_SIZE)
|
||||
|
||||
|
|
@ -23,7 +23,6 @@
|
|||
`define LINES_PER_BANK (`BANK_SIZE / CACHE_LINE_SIZE)
|
||||
`define WORDS_PER_LINE (CACHE_LINE_SIZE / WORD_SIZE)
|
||||
|
||||
`define WORD_SELECT_BITS `CLOG2(`WORDS_PER_LINE)
|
||||
`define WORD_ADDR_WIDTH (32-`CLOG2(WORD_SIZE))
|
||||
`define DRAM_ADDR_WIDTH (32-`CLOG2(CACHE_LINE_SIZE))
|
||||
`define LINE_ADDR_WIDTH (`DRAM_ADDR_WIDTH-`BANK_SELECT_BITS)
|
||||
|
|
|
|||
173
hw/rtl/cache/VX_cache_core_req_bank_sel.v
vendored
173
hw/rtl/cache/VX_cache_core_req_bank_sel.v
vendored
|
|
@ -6,75 +6,98 @@ module VX_cache_core_req_bank_sel #(
|
|||
// Size of a word in bytes
|
||||
parameter WORD_SIZE = 4,
|
||||
// Number of banks
|
||||
parameter NUM_BANKS = 4,
|
||||
parameter NUM_BANKS = 4,
|
||||
// Number of Word requests per cycle
|
||||
parameter NUM_REQS = 4,
|
||||
// core request tag size
|
||||
parameter CORE_TAG_WIDTH = 3,
|
||||
// bank offset from beginning of index range
|
||||
parameter BANK_ADDR_OFFSET = 0,
|
||||
// buffer the output
|
||||
parameter BUFFERED = 0
|
||||
parameter BANK_ADDR_OFFSET = 0
|
||||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
|
||||
`ifdef PERF_ENABLE
|
||||
output wire [63:0] bank_stalls,
|
||||
`endif
|
||||
|
||||
input wire [NUM_REQS-1:0] core_req_valid,
|
||||
input wire [NUM_REQS-1:0] core_req_rw,
|
||||
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
|
||||
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
|
||||
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
|
||||
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
|
||||
input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
|
||||
output wire [NUM_REQS-1:0] core_req_ready,
|
||||
|
||||
output wire [NUM_BANKS-1:0] per_bank_core_req_valid,
|
||||
output wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid,
|
||||
output wire [NUM_BANKS-1:0] per_bank_core_req_rw,
|
||||
output wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr,
|
||||
output wire [NUM_BANKS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel,
|
||||
output wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen,
|
||||
output wire [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr,
|
||||
output wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag,
|
||||
output wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data,
|
||||
output wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag,
|
||||
output wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid,
|
||||
input wire [NUM_BANKS-1:0] per_bank_core_req_ready
|
||||
);
|
||||
if (NUM_BANKS > 1) begin
|
||||
`STATIC_ASSERT (NUM_REQS >= NUM_BANKS, ("invalid number of banks"));
|
||||
|
||||
`UNUSED_VAR (clk)
|
||||
`UNUSED_VAR (reset)
|
||||
|
||||
wire [NUM_REQS-1:0][`LINE_ADDR_WIDTH-1:0] core_req_line_addr;
|
||||
wire [NUM_REQS-1:0][`UP(`WORD_SELECT_BITS)-1:0] core_req_wsel;
|
||||
wire [NUM_REQS-1:0][`UP(`BANK_SELECT_BITS)-1:0] core_req_bid;
|
||||
|
||||
for (genvar i = 0; i < NUM_REQS; i++) begin
|
||||
if (BANK_ADDR_OFFSET == 0) begin
|
||||
assign core_req_line_addr[i] = `LINE_SELECT_ADDR0(core_req_addr[i]);
|
||||
end else begin
|
||||
assign core_req_line_addr[i] = `LINE_SELECT_ADDRX(core_req_addr[i]);
|
||||
end
|
||||
assign core_req_wsel[i] = core_req_addr[i][`UP(`WORD_SELECT_BITS)-1:0];
|
||||
end
|
||||
|
||||
for (genvar i = 0; i < NUM_REQS; ++i) begin
|
||||
if (NUM_BANKS > 1) begin
|
||||
assign core_req_bid[i] = `BANK_SELECT_ADDR(core_req_addr[i]);
|
||||
end else begin
|
||||
assign core_req_bid[i] = 0;
|
||||
end
|
||||
end
|
||||
|
||||
if (NUM_REQS > 1) begin
|
||||
|
||||
reg [NUM_BANKS-1:0] per_bank_core_req_valid_r;
|
||||
reg [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_r;
|
||||
reg [NUM_BANKS-1:0] per_bank_core_req_rw_r;
|
||||
reg [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr_r;
|
||||
reg [NUM_BANKS-1:0][`UP(`WORD_SELECT_BITS)-1:0] per_bank_core_req_wsel_r;
|
||||
reg [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_r;
|
||||
reg [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr_r;
|
||||
reg [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_r;
|
||||
reg [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_r;
|
||||
reg [NUM_BANKS-1:0] per_bank_core_req_stall;
|
||||
reg [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_r;
|
||||
reg [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_r;
|
||||
|
||||
reg [NUM_REQS-1:0] core_req_ready_r;
|
||||
reg [NUM_REQS-1:0] core_req_sel_r;
|
||||
wire [NUM_REQS-1:0][`BANK_SELECT_BITS-1:0] core_req_bid;
|
||||
|
||||
for (genvar i = 0; i < NUM_REQS; ++i) begin
|
||||
assign core_req_bid[i] = `BANK_SELECT_ADDR(core_req_addr[i]);
|
||||
end
|
||||
reg [NUM_REQS-1:0] core_req_ready_r;
|
||||
|
||||
always @(*) begin
|
||||
per_bank_core_req_valid_r = 0;
|
||||
per_bank_core_req_tid_r = 'x;
|
||||
per_bank_core_req_rw_r = 'x;
|
||||
per_bank_core_req_byteen_r= 'x;
|
||||
per_bank_core_req_addr_r = 'x;
|
||||
per_bank_core_req_tag_r = 'x;
|
||||
per_bank_core_req_wsel_r = 'x;
|
||||
per_bank_core_req_byteen_r= 'x;
|
||||
per_bank_core_req_data_r = 'x;
|
||||
per_bank_core_req_tag_r = 'x;
|
||||
per_bank_core_req_tid_r = 'x;
|
||||
|
||||
for (integer i = NUM_REQS-1; i >= 0; --i) begin
|
||||
for (integer i = NUM_REQS-1; i >= 0; --i) begin
|
||||
if (core_req_valid[i]) begin
|
||||
per_bank_core_req_valid_r[core_req_bid[i]] = 1;
|
||||
per_bank_core_req_tid_r[core_req_bid[i]] = `REQS_BITS'(i);
|
||||
per_bank_core_req_rw_r[core_req_bid[i]] = core_req_rw[i];
|
||||
per_bank_core_req_addr_r[core_req_bid[i]] = core_req_line_addr[i];
|
||||
per_bank_core_req_wsel_r[core_req_bid[i]] = core_req_wsel[i];
|
||||
per_bank_core_req_byteen_r[core_req_bid[i]]= core_req_byteen[i];
|
||||
per_bank_core_req_addr_r[core_req_bid[i]] = core_req_addr[i];
|
||||
per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i];
|
||||
per_bank_core_req_data_r[core_req_bid[i]] = core_req_data[i];
|
||||
per_bank_core_req_tag_r[core_req_bid[i]] = core_req_tag[i];
|
||||
per_bank_core_req_tid_r[core_req_bid[i]] = `REQS_BITS'(i);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -84,65 +107,63 @@ module VX_cache_core_req_bank_sel #(
|
|||
for (integer j = 0; j < NUM_BANKS; ++j) begin
|
||||
for (integer i = 0; i < NUM_REQS; ++i) begin
|
||||
if (core_req_valid[i] && (core_req_bid[i] == `BANK_SELECT_BITS'(j))) begin
|
||||
core_req_ready_r[i] = ~per_bank_core_req_stall[j];
|
||||
core_req_ready_r[i] = per_bank_core_req_ready[j];
|
||||
break;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
core_req_sel_r = 0;
|
||||
for (integer j = 0; j < NUM_BANKS; ++j) begin
|
||||
for (integer i = 0; i < NUM_REQS; ++i) begin
|
||||
if (core_req_valid[i] && (core_req_bid[i] == `BANK_SELECT_BITS'(j))) begin
|
||||
core_req_sel_r[i] = ~per_bank_core_req_stall[j];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [63:0] bank_stalls_r;
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
bank_stalls_r <= 0;
|
||||
end else begin
|
||||
bank_stalls_r <= bank_stalls_r + 64'($countones(core_req_sel_r & ~core_req_ready_r));
|
||||
end
|
||||
end
|
||||
|
||||
for (genvar i = 0; i < NUM_BANKS; ++i) begin
|
||||
assign per_bank_core_req_stall[i] = ~per_bank_core_req_ready[i] && (!BUFFERED || per_bank_core_req_valid[i]);
|
||||
VX_pipe_register #(
|
||||
.DATAW (1 + `REQS_BITS + 1 + WORD_SIZE + `WORD_ADDR_WIDTH + CORE_TAG_WIDTH + `WORD_WIDTH),
|
||||
.RESETW (1),
|
||||
.DEPTH (BUFFERED)
|
||||
) pipe_reg (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.enable (~per_bank_core_req_stall[i]),
|
||||
.data_in ({per_bank_core_req_valid_r[i], per_bank_core_req_tid_r[i], per_bank_core_req_rw_r[i], per_bank_core_req_byteen_r[i], per_bank_core_req_addr_r[i], per_bank_core_req_tag_r[i], per_bank_core_req_data_r[i]}),
|
||||
.data_out ({per_bank_core_req_valid[i], per_bank_core_req_tid[i], per_bank_core_req_rw[i], per_bank_core_req_byteen[i], per_bank_core_req_addr[i], per_bank_core_req_tag[i], per_bank_core_req_data[i]})
|
||||
);
|
||||
end
|
||||
|
||||
assign per_bank_core_req_valid = per_bank_core_req_valid_r;
|
||||
assign per_bank_core_req_rw = per_bank_core_req_rw_r;
|
||||
assign per_bank_core_req_addr = per_bank_core_req_addr_r;
|
||||
assign per_bank_core_req_wsel = per_bank_core_req_wsel_r;
|
||||
assign per_bank_core_req_byteen = per_bank_core_req_byteen_r;
|
||||
assign per_bank_core_req_data = per_bank_core_req_data_r;
|
||||
assign per_bank_core_req_tag = per_bank_core_req_tag_r;
|
||||
assign per_bank_core_req_tid = per_bank_core_req_tid_r;
|
||||
assign core_req_ready = core_req_ready_r;
|
||||
assign bank_stalls = bank_stalls_r;
|
||||
|
||||
end else begin
|
||||
|
||||
`UNUSED_VAR (clk)
|
||||
`UNUSED_VAR (reset)
|
||||
assign bank_stalls = 0;
|
||||
assign per_bank_core_req_valid = core_req_valid;
|
||||
assign per_bank_core_req_tid[0] = 0;
|
||||
assign per_bank_core_req_rw[0] = core_req_rw;
|
||||
assign per_bank_core_req_byteen[0] = core_req_byteen;
|
||||
assign per_bank_core_req_addr[0] = core_req_addr;
|
||||
assign per_bank_core_req_tag[0] = core_req_tag;
|
||||
assign per_bank_core_req_data[0] = core_req_data;
|
||||
assign core_req_ready[0] = per_bank_core_req_ready;
|
||||
`UNUSED_VAR (core_req_bid)
|
||||
|
||||
end
|
||||
assign per_bank_core_req_valid = core_req_valid[0];
|
||||
assign per_bank_core_req_rw[0] = core_req_rw[0];
|
||||
assign per_bank_core_req_addr[0] = core_req_line_addr[0];
|
||||
assign per_bank_core_req_wsel[0] = core_req_wsel[0];
|
||||
assign per_bank_core_req_byteen[0] = core_req_byteen[0];
|
||||
assign per_bank_core_req_data[0] = core_req_data[0];
|
||||
assign per_bank_core_req_tag[0] = core_req_tag[0];
|
||||
assign per_bank_core_req_tid[0] = 0;
|
||||
assign core_req_ready[0] = per_bank_core_req_ready;
|
||||
end
|
||||
|
||||
`ifdef PERF_ENABLE
|
||||
reg [NUM_REQS-1:0] core_req_sel_r;
|
||||
|
||||
always @(*) begin
|
||||
core_req_sel_r = 0;
|
||||
for (integer j = 0; j < NUM_BANKS; ++j) begin
|
||||
for (integer i = 0; i < NUM_REQS; ++i) begin
|
||||
if (core_req_valid[i] && (core_req_bid[i] == `UP(`BANK_SELECT_BITS)'(j))) begin
|
||||
core_req_sel_r[i] = per_bank_core_req_ready[j];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [63:0] bank_stalls_r;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
bank_stalls_r <= 0;
|
||||
end else begin
|
||||
bank_stalls_r <= bank_stalls_r + 64'($countones(core_req_sel_r & ~core_req_ready));
|
||||
end
|
||||
end
|
||||
|
||||
assign bank_stalls = bank_stalls_r;
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
4
hw/rtl/cache/VX_cache_core_rsp_merge.v
vendored
4
hw/rtl/cache/VX_cache_core_rsp_merge.v
vendored
|
|
@ -16,10 +16,10 @@ module VX_cache_core_rsp_merge #(
|
|||
input wire reset,
|
||||
|
||||
// Per Bank WB
|
||||
input wire [NUM_BANKS-1:0] per_bank_core_rsp_valid,
|
||||
input wire [NUM_BANKS-1:0] per_bank_core_rsp_valid,
|
||||
input wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data,
|
||||
input wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_rsp_tag,
|
||||
input wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_rsp_tid,
|
||||
input wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_rsp_data,
|
||||
output wire [NUM_BANKS-1:0] per_bank_core_rsp_ready,
|
||||
|
||||
// Core Response
|
||||
|
|
|
|||
2
hw/rtl/cache/VX_data_access.v
vendored
2
hw/rtl/cache/VX_data_access.v
vendored
|
|
@ -39,7 +39,7 @@ module VX_data_access #(
|
|||
// writing
|
||||
input wire writeen,
|
||||
input wire is_fill,
|
||||
input wire [`UP(`WORD_SELECT_BITS)-1:0] wsel,
|
||||
input wire [`WORD_SELECT_BITS-1:0] wsel,
|
||||
input wire [WORD_SIZE-1:0] byteen,
|
||||
input wire [`CACHE_LINE_WIDTH-1:0] wrdata
|
||||
);
|
||||
|
|
|
|||
7
hw/rtl/cache/VX_miss_resrv.v
vendored
7
hw/rtl/cache/VX_miss_resrv.v
vendored
|
|
@ -4,14 +4,15 @@ module VX_miss_resrv #(
|
|||
parameter CACHE_ID = 0,
|
||||
parameter BANK_ID = 0,
|
||||
|
||||
// Number of Word requests per cycle
|
||||
parameter NUM_REQS = 1,
|
||||
|
||||
// Size of line inside a bank in bytes
|
||||
parameter CACHE_LINE_SIZE = 1,
|
||||
// Number of banks
|
||||
parameter NUM_BANKS = 1,
|
||||
parameter NUM_BANKS = 1,
|
||||
// Size of a word in bytes
|
||||
parameter WORD_SIZE = 1,
|
||||
// Number of Word requests per cycle
|
||||
parameter NUM_REQS = 1,
|
||||
// Miss Reserv Queue Knob
|
||||
parameter MSHR_SIZE = 1,
|
||||
parameter ALM_FULL = (MSHR_SIZE-1),
|
||||
|
|
|
|||
88
hw/rtl/cache/VX_shared_mem.v
vendored
88
hw/rtl/cache/VX_shared_mem.v
vendored
|
|
@ -38,8 +38,8 @@ module VX_shared_mem #(
|
|||
// Core request
|
||||
input wire [NUM_REQS-1:0] core_req_valid,
|
||||
input wire [NUM_REQS-1:0] core_req_rw,
|
||||
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
|
||||
input wire [NUM_REQS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr,
|
||||
input wire [NUM_REQS-1:0][WORD_SIZE-1:0] core_req_byteen,
|
||||
input wire [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_req_data,
|
||||
input wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
|
||||
output wire [NUM_REQS-1:0] core_req_ready,
|
||||
|
|
@ -63,12 +63,12 @@ module VX_shared_mem #(
|
|||
`endif
|
||||
|
||||
wire [NUM_BANKS-1:0] per_bank_core_req_valid_unqual;
|
||||
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_unqual;
|
||||
wire [NUM_BANKS-1:0] per_bank_core_req_rw_unqual;
|
||||
wire [NUM_BANKS-1:0][`LINE_ADDR_WIDTH-1:0] per_bank_core_req_addr_unqual;
|
||||
wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen_unqual;
|
||||
wire [NUM_BANKS-1:0][`WORD_ADDR_WIDTH-1:0] per_bank_core_req_addr_unqual;
|
||||
wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data_unqual;
|
||||
wire [NUM_BANKS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag_unqual;
|
||||
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid_unqual;
|
||||
wire [NUM_BANKS-1:0] per_bank_core_req_ready_unqual;
|
||||
|
||||
VX_cache_core_req_bank_sel #(
|
||||
|
|
@ -77,28 +77,26 @@ module VX_shared_mem #(
|
|||
.WORD_SIZE (WORD_SIZE),
|
||||
.NUM_REQS (NUM_REQS),
|
||||
.CORE_TAG_WIDTH (CORE_TAG_WIDTH),
|
||||
.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET),
|
||||
.BUFFERED (0)
|
||||
.BANK_ADDR_OFFSET(BANK_ADDR_OFFSET)
|
||||
) core_req_bank_sel (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
`ifdef PERF_ENABLE
|
||||
.bank_stalls(perf_cache_if.bank_stalls),
|
||||
`else
|
||||
`UNUSED_PIN (bank_stalls),
|
||||
`endif
|
||||
.core_req_valid (core_req_valid),
|
||||
.core_req_rw (core_req_rw),
|
||||
.core_req_byteen(core_req_byteen),
|
||||
.core_req_rw (core_req_rw),
|
||||
.core_req_addr (core_req_addr),
|
||||
.core_req_byteen(core_req_byteen),
|
||||
.core_req_data (core_req_data),
|
||||
.core_req_tag (core_req_tag),
|
||||
.core_req_ready (core_req_ready),
|
||||
.per_bank_core_req_valid (per_bank_core_req_valid_unqual),
|
||||
.per_bank_core_req_valid (per_bank_core_req_valid_unqual),
|
||||
.per_bank_core_req_tid (per_bank_core_req_tid_unqual),
|
||||
.per_bank_core_req_rw (per_bank_core_req_rw_unqual),
|
||||
.per_bank_core_req_byteen(per_bank_core_req_byteen_unqual),
|
||||
.per_bank_core_req_addr (per_bank_core_req_addr_unqual),
|
||||
`UNUSED_PIN (per_bank_core_req_wsel),
|
||||
.per_bank_core_req_byteen(per_bank_core_req_byteen_unqual),
|
||||
.per_bank_core_req_tag (per_bank_core_req_tag_unqual),
|
||||
.per_bank_core_req_data (per_bank_core_req_data_unqual),
|
||||
.per_bank_core_req_ready (per_bank_core_req_ready_unqual)
|
||||
|
|
@ -108,12 +106,12 @@ module VX_shared_mem #(
|
|||
`UNUSED_VAR (per_bank_core_req_rw_unqual)
|
||||
|
||||
wire [NUM_BANKS-1:0] per_bank_core_req_valid;
|
||||
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid;
|
||||
wire [NUM_REQS-1:0] per_bank_core_req_rw;
|
||||
wire [NUM_BANKS-1:0] per_bank_core_req_rw;
|
||||
wire [NUM_BANKS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr;
|
||||
wire [NUM_BANKS-1:0][WORD_SIZE-1:0] per_bank_core_req_byteen;
|
||||
wire [NUM_BANKS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr;
|
||||
wire [NUM_BANKS-1:0][`WORD_WIDTH-1:0] per_bank_core_req_data;
|
||||
wire [NUM_REQS-1:0][CORE_TAG_WIDTH-1:0] per_bank_core_req_tag;
|
||||
wire [NUM_BANKS-1:0][`REQS_BITS-1:0] per_bank_core_req_tid;
|
||||
|
||||
wire creq_push, creq_pop, creq_empty, creq_full;
|
||||
wire crsq_full;
|
||||
|
|
@ -121,18 +119,16 @@ module VX_shared_mem #(
|
|||
assign creq_push = (| core_req_valid) && !creq_full;
|
||||
assign creq_pop = ~creq_empty && ~crsq_full;
|
||||
|
||||
assign per_bank_core_req_ready_unqual = {NUM_BANKS{~creq_full}};
|
||||
assign per_bank_core_req_ready_unqual = {NUM_BANKS{~creq_full}};
|
||||
|
||||
wire [NUM_REQS-1:0][`LINE_SELECT_BITS-1:0] per_bank_core_req_addr_qual;
|
||||
`UNUSED_VAR (per_bank_core_req_addr_unqual)
|
||||
for (genvar i = 0; i < NUM_REQS; i++) begin
|
||||
wire [`LINE_ADDR_WIDTH-1:0] tmp = `LINE_SELECT_ADDRX(per_bank_core_req_addr_unqual[i]);
|
||||
assign per_bank_core_req_addr_qual[i] = tmp[`LINE_SELECT_BITS-1:0];
|
||||
`UNUSED_VAR (tmp)
|
||||
for (genvar i = 0; i < NUM_REQS; i++) begin
|
||||
assign per_bank_core_req_addr_qual[i] = per_bank_core_req_addr_unqual[i][`LINE_SELECT_BITS-1:0];
|
||||
end
|
||||
|
||||
VX_fifo_queue #(
|
||||
.DATAW (NUM_BANKS * (1 + `REQS_BITS + 1 + WORD_SIZE + `LINE_SELECT_BITS + `WORD_WIDTH + CORE_TAG_WIDTH)),
|
||||
.DATAW (NUM_BANKS * (1 + 1 + `LINE_SELECT_BITS + WORD_SIZE + `WORD_WIDTH + CORE_TAG_WIDTH + `REQS_BITS)),
|
||||
.SIZE (CREQ_SIZE),
|
||||
.BUFFERED (1)
|
||||
) core_req_queue (
|
||||
|
|
@ -140,20 +136,20 @@ module VX_shared_mem #(
|
|||
.reset (reset),
|
||||
.push (creq_push),
|
||||
.pop (creq_pop),
|
||||
.data_in ({per_bank_core_req_valid_unqual,
|
||||
per_bank_core_req_tid_unqual,
|
||||
.data_in ({per_bank_core_req_valid_unqual,
|
||||
per_bank_core_req_rw_unqual,
|
||||
per_bank_core_req_byteen_unqual,
|
||||
per_bank_core_req_addr_qual,
|
||||
per_bank_core_req_byteen_unqual,
|
||||
per_bank_core_req_data_unqual,
|
||||
per_bank_core_req_tag_unqual}),
|
||||
.data_out({per_bank_core_req_valid,
|
||||
per_bank_core_req_tid,
|
||||
per_bank_core_req_tag_unqual,
|
||||
per_bank_core_req_tid_unqual}),
|
||||
.data_out({per_bank_core_req_valid,
|
||||
per_bank_core_req_rw,
|
||||
per_bank_core_req_byteen,
|
||||
per_bank_core_req_addr,
|
||||
per_bank_core_req_byteen,
|
||||
per_bank_core_req_data,
|
||||
per_bank_core_req_tag}),
|
||||
per_bank_core_req_tag,
|
||||
per_bank_core_req_tid}),
|
||||
.empty (creq_empty),
|
||||
.full (creq_full),
|
||||
`UNUSED_PIN (alm_empty),
|
||||
|
|
@ -248,13 +244,41 @@ module VX_shared_mem #(
|
|||
`endif
|
||||
|
||||
`ifdef PERF_ENABLE
|
||||
assign perf_cache_if.reads = '0;
|
||||
assign perf_cache_if.writes = '0;
|
||||
// per cycle: core_reads, core_writes
|
||||
reg [($clog2(NUM_REQS+1)-1):0] perf_core_reads_per_cycle, perf_core_writes_per_cycle;
|
||||
reg [($clog2(NUM_REQS+1)-1):0] perf_crsp_stall_per_cycle;
|
||||
|
||||
assign perf_core_reads_per_cycle = $countones(core_req_valid & core_req_ready & ~core_req_rw);
|
||||
assign perf_core_writes_per_cycle = $countones(core_req_valid & core_req_ready & core_req_rw);
|
||||
|
||||
if (CORE_TAG_ID_BITS != 0) begin
|
||||
assign perf_crsp_stall_per_cycle = $countones(core_rsp_valid & {NUM_REQS{!core_rsp_ready}});
|
||||
end else begin
|
||||
assign perf_crsp_stall_per_cycle = $countones(core_rsp_valid & ~core_rsp_ready);
|
||||
end
|
||||
|
||||
reg [63:0] perf_core_reads;
|
||||
reg [63:0] perf_core_writes;
|
||||
reg [63:0] perf_crsp_stalls;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (reset) begin
|
||||
perf_core_reads <= 0;
|
||||
perf_core_writes <= 0;
|
||||
perf_crsp_stalls <= 0;
|
||||
end else begin
|
||||
perf_core_reads <= perf_core_reads + 64'(perf_core_reads_per_cycle);
|
||||
perf_core_writes <= perf_core_writes + 64'(perf_core_writes_per_cycle);
|
||||
perf_crsp_stalls <= perf_crsp_stalls + 64'(perf_crsp_stall_per_cycle);
|
||||
end
|
||||
end
|
||||
|
||||
assign perf_cache_if.reads = perf_core_reads;
|
||||
assign perf_cache_if.writes = perf_core_writes;
|
||||
assign perf_cache_if.read_misses = '0;
|
||||
assign perf_cache_if.write_misses = '0;
|
||||
assign perf_cache_if.mshr_stalls = '0;
|
||||
assign perf_cache_if.pipe_stalls = '0;
|
||||
assign perf_cache_if.crsp_stalls = '0;
|
||||
assign perf_cache_if.crsp_stalls = perf_crsp_stalls;
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -29,13 +29,6 @@ module VX_fp_div #(
|
|||
wire stall = ~ready_out && valid_out;
|
||||
wire enable = ~stall;
|
||||
|
||||
wire _reset;
|
||||
VX_reset_relay reset_relay (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.reset_out (_reset)
|
||||
);
|
||||
|
||||
for (genvar i = 0; i < LANES; i++) begin
|
||||
`ifdef VERILATOR
|
||||
reg [31:0] r;
|
||||
|
|
@ -52,7 +45,7 @@ module VX_fp_div #(
|
|||
.RESETW (1)
|
||||
) shift_req_dpi (
|
||||
.clk (clk),
|
||||
.reset (_reset),
|
||||
.reset (reset),
|
||||
.enable (enable),
|
||||
.data_in (r),
|
||||
.data_out (result[i])
|
||||
|
|
@ -60,7 +53,7 @@ module VX_fp_div #(
|
|||
`else
|
||||
acl_fdiv fdiv (
|
||||
.clk (clk),
|
||||
.areset (_reset),
|
||||
.areset (reset),
|
||||
.en (enable),
|
||||
.a (dataa[i]),
|
||||
.b (datab[i]),
|
||||
|
|
|
|||
|
|
@ -26,14 +26,7 @@ module VX_fp_sqrt #(
|
|||
output wire valid_out
|
||||
);
|
||||
wire stall = ~ready_out && valid_out;
|
||||
wire enable = ~stall;
|
||||
|
||||
wire _reset;
|
||||
VX_reset_relay reset_relay (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.reset_out (_reset)
|
||||
);
|
||||
wire enable = ~stall;
|
||||
|
||||
for (genvar i = 0; i < LANES; i++) begin
|
||||
`ifdef VERILATOR
|
||||
|
|
@ -51,7 +44,7 @@ module VX_fp_sqrt #(
|
|||
.RESETW (1)
|
||||
) shift_req_dpi (
|
||||
.clk (clk),
|
||||
.reset (_reset),
|
||||
.reset (reset),
|
||||
.enable (enable),
|
||||
.data_in (r),
|
||||
.data_out (result[i])
|
||||
|
|
@ -59,7 +52,7 @@ module VX_fp_sqrt #(
|
|||
`else
|
||||
acl_fsqrt fsqrt (
|
||||
.clk (clk),
|
||||
.areset (_reset),
|
||||
.areset (reset),
|
||||
.en (enable),
|
||||
.a (dataa[i]),
|
||||
.q (result[i])
|
||||
|
|
|
|||
|
|
@ -71,12 +71,21 @@ module VX_fpu_fpga #(
|
|||
endcase
|
||||
end
|
||||
|
||||
wire [NUM_FPC-1:0] fpu_reset;
|
||||
VX_reset_relay #(
|
||||
.NUM_NODES(NUM_FPC)
|
||||
) reset_relay (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.reset_o (fpu_reset)
|
||||
);
|
||||
|
||||
VX_fp_fma #(
|
||||
.TAGW (TAGW),
|
||||
.LANES(`NUM_THREADS)
|
||||
) fp_fma (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.reset (fpu_reset[FPU_FMA]),
|
||||
.valid_in (valid_in && (core_select == FPU_FMA)),
|
||||
.ready_in (per_core_ready_in[FPU_FMA]),
|
||||
.tag_in (tag_in),
|
||||
|
|
@ -100,7 +109,7 @@ module VX_fpu_fpga #(
|
|||
.LANES(`NUM_THREADS)
|
||||
) fp_div (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.reset (fpu_reset[FPU_DIV]),
|
||||
.valid_in (valid_in && (core_select == FPU_DIV)),
|
||||
.ready_in (per_core_ready_in[FPU_DIV]),
|
||||
.tag_in (tag_in),
|
||||
|
|
@ -120,7 +129,7 @@ module VX_fpu_fpga #(
|
|||
.LANES(`NUM_THREADS)
|
||||
) fp_sqrt (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.reset (fpu_reset[FPU_SQRT]),
|
||||
.valid_in (valid_in && (core_select == FPU_SQRT)),
|
||||
.ready_in (per_core_ready_in[FPU_SQRT]),
|
||||
.tag_in (tag_in),
|
||||
|
|
@ -139,7 +148,7 @@ module VX_fpu_fpga #(
|
|||
.LANES(`NUM_THREADS)
|
||||
) fp_cvt (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.reset (fpu_reset[FPU_CVT]),
|
||||
.valid_in (valid_in && (core_select == FPU_CVT)),
|
||||
.ready_in (per_core_ready_in[FPU_CVT]),
|
||||
.tag_in (tag_in),
|
||||
|
|
@ -160,7 +169,7 @@ module VX_fpu_fpga #(
|
|||
.LANES(`NUM_THREADS)
|
||||
) fp_ncomp (
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.reset (fpu_reset[FPU_NCP]),
|
||||
.valid_in (valid_in && (core_select == FPU_NCP)),
|
||||
.ready_in (per_core_ready_in[FPU_NCP]),
|
||||
.tag_in (tag_in),
|
||||
|
|
|
|||
|
|
@ -0,0 +1,514 @@
|
|||
:020000040000FA
|
||||
:0400000020000004D8
|
||||
:040001001FF00800E4
|
||||
:040002001FE01FE4F8
|
||||
:040003001FD047992A
|
||||
:040004001FC07F0694
|
||||
:040005001FB0C6154D
|
||||
:040006001FA11CAE6C
|
||||
:040007001F9182BA09
|
||||
:040008001F81F82339
|
||||
:040009001F727CD214
|
||||
:04000A001F6310B1AF
|
||||
:04000B001F53B3A824
|
||||
:04000C001F4465A286
|
||||
:04000D001F352689EC
|
||||
:04000E001F25F6486C
|
||||
:04000F001F16D4C81C
|
||||
:040010001F07C1F411
|
||||
:040011001EF8BDB761
|
||||
:040012001EE9C7FC20
|
||||
:040013001EDAE0AE63
|
||||
:040014001ECC07B740
|
||||
:040015001EBD3D03CC
|
||||
:040016001EAE807F1B
|
||||
:040017001E9FD21442
|
||||
:040018001E9131B054
|
||||
:040019001E829F3E66
|
||||
:04001A001E741AA98D
|
||||
:04001B001E65A3E0DB
|
||||
:04001C001E573ACD64
|
||||
:04001D001E48DF5D3D
|
||||
:04001E001E3A917E77
|
||||
:04001F001E2C511B27
|
||||
:040020001E1E1E2260
|
||||
:040021001E0FF88036
|
||||
:040022001E01E022B9
|
||||
:040023001DF3D4F500
|
||||
:040024001DE5D6E818
|
||||
:040025001DD7E5E717
|
||||
:040026001DCA01E10D
|
||||
:040027001DBC2AC210
|
||||
:040028001DAE607B2E
|
||||
:040029001DA0A2F77D
|
||||
:04002A001D92F2270A
|
||||
:04002B001D854DF8EA
|
||||
:04002C001D77B6592D
|
||||
:04002D001D6A2B38E5
|
||||
:04002E001D5CAC8425
|
||||
:04002F001D4F3A2DFA
|
||||
:040030001D41D42179
|
||||
:040031001D347A50B0
|
||||
:040032001D272CA8B2
|
||||
:040033001D19EB198F
|
||||
:040034001D0CB59357
|
||||
:040035001CFF8C061A
|
||||
:040036001CF26E60EA
|
||||
:040037001CE55C93D5
|
||||
:040038001CD8568DED
|
||||
:040039001CCB5C3F41
|
||||
:04003A001CBE6D9AE1
|
||||
:04003B001CB18A8DDD
|
||||
:04003C001CA4B30944
|
||||
:04003D001C97E6FF27
|
||||
:04003E001C8B265F92
|
||||
:04003F001C7E711A98
|
||||
:040040001C71C72048
|
||||
:040041001C652864AE
|
||||
:040042001C5894D5DD
|
||||
:040043001C4C0C65E0
|
||||
:040044001C3F8F06C8
|
||||
:040045001C331CA8A4
|
||||
:040046001C26B53D82
|
||||
:040047001C1A58B770
|
||||
:040048001C0E07077C
|
||||
:040049001C01C020B6
|
||||
:04004A001BF583F22D
|
||||
:04004B001BE95271EA
|
||||
:04004C001BDD2B8EFF
|
||||
:04004D001BD10F3A7A
|
||||
:04004E001BC4FD6969
|
||||
:04004F001BB8F60DD7
|
||||
:040050001BACF919D3
|
||||
:040051001BA1067E6B
|
||||
:040052001B951E2FAD
|
||||
:040053001B89401FA6
|
||||
:040054001B7D6C4262
|
||||
:040055001B71A289F0
|
||||
:040056001B65E2E85C
|
||||
:040057001B5A2D51B2
|
||||
:040058001B4E81B901
|
||||
:040059001B42E01254
|
||||
:04005A001B37484FB9
|
||||
:04005B001B2BBA643D
|
||||
:04005C001B203644EB
|
||||
:04005D001B14BBE4D1
|
||||
:04005E001B094B36F9
|
||||
:04005F001AFDE42E74
|
||||
:040060001AF286C149
|
||||
:040061001AE732E187
|
||||
:040062001ADBE88439
|
||||
:040063001AD0A79C6C
|
||||
:040064001AC5701F2A
|
||||
:040065001ABA420081
|
||||
:040066001AAF1D337D
|
||||
:040067001AA401AE28
|
||||
:040068001A98EF648F
|
||||
:040069001A8DE64ABC
|
||||
:04006A001A82E655BB
|
||||
:04006B001A77EF7998
|
||||
:04006C001A6D01AB5D
|
||||
:04006D001A621CDF18
|
||||
:04006E001A57410BD1
|
||||
:04006F001A4C6E2495
|
||||
:040070001A41A41E6F
|
||||
:040071001A36E2EF6A
|
||||
:040072001A2C2A8C8E
|
||||
:040073001A217AE9EB
|
||||
:040074001A16D3FD88
|
||||
:040075001A0C35BD6F
|
||||
:040076001A01A01EAD
|
||||
:0400770019F713154D
|
||||
:0400780019EC8E9958
|
||||
:0400790019E2129ED8
|
||||
:04007A0019D79F1BD8
|
||||
:04007B0019CD340661
|
||||
:04007C0019C2D15381
|
||||
:04007D0019B876F93F
|
||||
:04007E0019AE24EEA5
|
||||
:04007F0019A3DB28BE
|
||||
:040080001999999E93
|
||||
:04008100198F60442F
|
||||
:0400820019852F129B
|
||||
:04008300197B05FDE3
|
||||
:040084001970E4FC0F
|
||||
:040085001966CC0626
|
||||
:04008600195CBB1036
|
||||
:040087001952B21147
|
||||
:040088001948B10161
|
||||
:04008900193EB7D590
|
||||
:04008A001934C684DB
|
||||
:04008B00192ADD044D
|
||||
:04008C001920FB4EEE
|
||||
:04008D0019172157C7
|
||||
:04008E00190D4F16E3
|
||||
:04008F00190384834A
|
||||
:0400900018F9C19406
|
||||
:0400910018F006401D
|
||||
:0400920018E6527F9B
|
||||
:0400930018DCA64887
|
||||
:0400940018D30191EB
|
||||
:0400950018C96453CF
|
||||
:0400960018BFCE843D
|
||||
:0400970018B6401D3A
|
||||
:0400980018ACB913D4
|
||||
:0400990018A339600F
|
||||
:04009A001899C0FAF7
|
||||
:04009B0018904FD991
|
||||
:04009C001886E5F5E8
|
||||
:04009D00187D834502
|
||||
:04009E00187427C1EA
|
||||
:04009F00186AD361A7
|
||||
:0400A0001861861C41
|
||||
:0400A10018583FECC0
|
||||
:0400A200184F00C62D
|
||||
:0400A3001845C8A58F
|
||||
:0400A400183C977FEE
|
||||
:0400A50018336D4C53
|
||||
:0400A600182A4A05C5
|
||||
:0400A70018212DA34C
|
||||
:0400A8001818181CF0
|
||||
:0400A900180F096AB9
|
||||
:0400AA0018060184AF
|
||||
:0400AB0017FD0064D9
|
||||
:0400AC0017F406013E
|
||||
:0400AD0017EB1254E7
|
||||
:0400AE0017E22555DB
|
||||
:0400AF0017D93EFE21
|
||||
:0400B00017D05F45C1
|
||||
:0400B10017C78625C2
|
||||
:0400B20017BEB3962C
|
||||
:0400B30017B5E79006
|
||||
:0400B40017AD220D55
|
||||
:0400B50017A4630425
|
||||
:0400B600179BAA707A
|
||||
:0400B7001792F8485C
|
||||
:0400B800178A4C85D2
|
||||
:0400B9001781A722E2
|
||||
:0400BA001779081694
|
||||
:0400BB0017706F5AF1
|
||||
:0400BC001767DCE8FE
|
||||
:0400BD00175F50B9C0
|
||||
:0400BE001756CAC641
|
||||
:0400BF00174E4B0885
|
||||
:0400C0001745D17897
|
||||
:0400C100173D5E1079
|
||||
:0400C2001734F0C936
|
||||
:0400C300172C899CD1
|
||||
:0400C4001724288352
|
||||
:0400C500171BCD77C1
|
||||
:0400C6001713787222
|
||||
:0400C700170B296C7E
|
||||
:0400C8001702E060DB
|
||||
:0400C90016FA9D473F
|
||||
:0400CA0016F2601BAF
|
||||
:0400CB0016EA28D534
|
||||
:0400CC0016E1F76FD3
|
||||
:0400CD0016D9CBE392
|
||||
:0400CE0016D1A62A77
|
||||
:0400CF0016C9863F89
|
||||
:0400D00016C16C1BCE
|
||||
:0400D10016B957B74E
|
||||
:0400D20016B1490F0B
|
||||
:0400D30016A9401B0F
|
||||
:0400D40016A13CD560
|
||||
:0400D50016993F3900
|
||||
:0400D6001691473FF9
|
||||
:0400D700168954E151
|
||||
:0400D8001681681A0B
|
||||
:0400D900167980E52F
|
||||
:0400DA0016719F3AC2
|
||||
:0400DB001669C314CB
|
||||
:0400DC001661EC6E4F
|
||||
:0400DD00165A1B4252
|
||||
:0400DE0016524F89DE
|
||||
:0400DF00164A893FF5
|
||||
:0400E0001642C85D9F
|
||||
:0400E100163B0CDEE0
|
||||
:0400E200163356BDBE
|
||||
:0400E300162BA5F340
|
||||
:0400E4001623FA7B6A
|
||||
:0400E500161C545041
|
||||
:0400E6001614B36CCD
|
||||
:0400E700160D17CA11
|
||||
:0400E8001605816414
|
||||
:0400E90015FDF035DC
|
||||
:0400EA0015F664386B
|
||||
:0400EB0015EEDD67CA
|
||||
:0400EC0015E75BBDFC
|
||||
:0400ED0015DFDF3408
|
||||
:0400EE0015D867C8F2
|
||||
:0400EF0015D0F573C0
|
||||
:0400F00015C9883076
|
||||
:0400F10015C21FF91C
|
||||
:0400F20015BABCCAB5
|
||||
:0400F30015B35E9E45
|
||||
:0400F40015AC056FD3
|
||||
:0400F50015A4B13865
|
||||
:0400F600159D61F5FE
|
||||
:0400F700159617A0A3
|
||||
:0400F800158ED2345B
|
||||
:0400F900158791AD29
|
||||
:0400FA001580560512
|
||||
:0400FB0015791F381C
|
||||
:0400FC001571ED404D
|
||||
:0400FD00156AC019A7
|
||||
:0400FE00156397BE31
|
||||
:0400FF00155C742BED
|
||||
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|
||||
:0300AD0009BB4A42
|
||||
:0300AE0009B42072
|
||||
:0300AA0009D12E4B
|
||||
:0300AB0009C9D0B0
|
||||
:0300AC0009C28402
|
||||
:0300AD0009BB4C40
|
||||
:0300AE0009B4246E
|
||||
:0300AF0009AD0692
|
||||
:0300B00009A5FBA4
|
||||
:0300B100099EFBAA
|
||||
:0300B20009980F9B
|
||||
:0300B30009913080
|
||||
:0300B400098A5F57
|
||||
:0300B50009839E1E
|
||||
:0300B600097CEDD5
|
||||
:0300B7000976487F
|
||||
:0300B800096FAF1E
|
||||
:0300B900096925AD
|
||||
:0300BA000962AB2D
|
||||
:0300B00009A5F8A7
|
||||
:0300B100099EFAAB
|
||||
:0300B20009980E9C
|
||||
:0300B3000991327E
|
||||
:0300B400098A6452
|
||||
:0300B5000983A21A
|
||||
:0300B600097CECD6
|
||||
:0300B70009764483
|
||||
:0300B800096FB21B
|
||||
:0300B900096928AA
|
||||
:0300BA000962AA2E
|
||||
:0300BB00095C3CA1
|
||||
:0300BC000955D90A
|
||||
:0300BD00094F8464
|
||||
:0300BE0009493EAF
|
||||
:0300BC000955DA09
|
||||
:0300BD00094F8662
|
||||
:0300BE0009493AB3
|
||||
:0300BF00094302F0
|
||||
:0300C000093CD424
|
||||
:0300C1000936AE4F
|
||||
:0300C20009309A68
|
||||
:0300C000093CD226
|
||||
:0300C1000936B04D
|
||||
:0300C20009309C66
|
||||
:0300C300092A8E79
|
||||
:0300C4000924917B
|
||||
:0300C500091E9E73
|
||||
:0300C6000918B75F
|
||||
:0300C7000912DA41
|
||||
:0300C800090D0B14
|
||||
:0300C900090745DF
|
||||
:0300CA0009018D9C
|
||||
:0300CB0008FBDB54
|
||||
:0300CC0008F635FE
|
||||
:0300CD0008F09B9D
|
||||
:0300C4000924927A
|
||||
:0300C500091EA071
|
||||
:0300C6000918B462
|
||||
:0300C7000912DE3D
|
||||
:0300C800090D0C13
|
||||
:0300C900090746DE
|
||||
:0300CA00090188A1
|
||||
:0300CB0008FBDA55
|
||||
:0300CC0008F63AF9
|
||||
:0300CD0008F09E9A
|
||||
:0300CE0008EB0C30
|
||||
:0300CF0008E588B9
|
||||
:0300D00008E00D38
|
||||
:0300D10008DA9BAF
|
||||
:0300D20008D5341A
|
||||
:0300D30008CFD87B
|
||||
:0300D40008CA85D2
|
||||
:0300D50008C53B20
|
||||
:0300D60008BFFA66
|
||||
:0300D70008BAC3A1
|
||||
:0300D80008B595D3
|
||||
:0300D00008E00E37
|
||||
:0300D10008DA9CAE
|
||||
:0300D20008D5321C
|
||||
:0300D30008CFD47F
|
||||
:0300D40008CA84D3
|
||||
:0300D50008C53A21
|
||||
:0300D60008BFF66A
|
||||
:0300D70008BAC4A0
|
||||
:0300D80008B590D8
|
||||
:0300D90008B070FC
|
||||
:0300DA0008AB521E
|
||||
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|
||||
:0300DC0008A13741
|
||||
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|
||||
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|
||||
:0300DE0008974040
|
||||
:0300DF0008924F35
|
||||
:0300E000088D6622
|
||||
:0300E10008888903
|
||||
:0300E2000883AFE1
|
||||
:0300E300087EE1B3
|
||||
:0300E400087A1E79
|
||||
:0300E50008755B40
|
||||
:0300E6000870A9F6
|
||||
:0300E700086BF9AA
|
||||
:0300E80008675155
|
||||
:0300E9000862B3F7
|
||||
:0300EA00085E1D90
|
||||
:0300EB0008598C25
|
||||
:0300EC00085503B1
|
||||
:0300ED0008508434
|
||||
:0300EE00084C0AB1
|
||||
:0300EF000847952A
|
||||
:0300F00008432999
|
||||
:0300DF0008925034
|
||||
:0300E000088D6A1E
|
||||
:0300E10008888804
|
||||
:0300E2000883B4DC
|
||||
:0300E300087EE6AE
|
||||
:0300E400087A1C7B
|
||||
:0300E50008755E3D
|
||||
:0300E6000870ACF3
|
||||
:0300E700086BF6AD
|
||||
:0300E80008675452
|
||||
:0300E9000862B2F8
|
||||
:0300EA00085E1895
|
||||
:0300EB0008598A27
|
||||
:0300EC00085504B0
|
||||
:0300ED0008508038
|
||||
:0300EE00084C0CAF
|
||||
:0300EF000847942B
|
||||
:0300F00008432C96
|
||||
:0300F100083EC600
|
||||
:0300F200083A6564
|
||||
:0300F30008360FBD
|
||||
:0300F200083A6A5F
|
||||
:0300F300083612BA
|
||||
:0300F4000831C010
|
||||
:0300F500082D785B
|
||||
:0300F600082934A2
|
||||
:0300F7000824F8E2
|
||||
:0300F8000820C419
|
||||
:0300F900081C964A
|
||||
:0300FA0008186E75
|
||||
:0300FB0008144E98
|
||||
:0300FC00081031B8
|
||||
:0300FD00080C1AD2
|
||||
:0300FE0008080BE4
|
||||
:0300FF00080402F0
|
||||
:0300F500082D7A59
|
||||
:0300F60008293A9C
|
||||
:0300F7000824FCDE
|
||||
:0300F8000820C21B
|
||||
:0300F900081C944C
|
||||
:0300FA0008187073
|
||||
:0300FB000814489E
|
||||
:0300FC00081030B9
|
||||
:0300FD00080C1ECE
|
||||
:0300FE0008080EE1
|
||||
:0300FF000803FEF5
|
||||
:00000001ff
|
||||
|
|
@ -127,132 +127,132 @@
|
|||
:02007D000E90E3
|
||||
:02007E000E92E0
|
||||
:02007F000E94DD
|
||||
:020080000A6014
|
||||
:020080000A6212
|
||||
:020081000A7201
|
||||
:020082000A82F0
|
||||
:020083000A8FE2
|
||||
:020084000AA3CD
|
||||
:020085000AB1BE
|
||||
:020083000A90E1
|
||||
:020084000AA0D0
|
||||
:020085000AB0BF
|
||||
:020086000ABEB0
|
||||
:020087000AD09D
|
||||
:020088000ADC90
|
||||
:020089000AED7E
|
||||
:02008A000AF971
|
||||
:02008B000B095F
|
||||
:02008C000B1552
|
||||
:020087000ACAA3
|
||||
:020088000ADE8E
|
||||
:020089000AE883
|
||||
:02008A000AF872
|
||||
:02008B000B0662
|
||||
:02008C000B1255
|
||||
:02008D000B2244
|
||||
:02008E000B2E37
|
||||
:02008F000B3D27
|
||||
:020090000B481B
|
||||
:020091000B540E
|
||||
:020092000B5F02
|
||||
:020093000B6FF1
|
||||
:020094000B79E6
|
||||
:020095000B83DB
|
||||
:020096000B92CB
|
||||
:020097000B9BC1
|
||||
:020098000BA8B3
|
||||
:020099000BB1A9
|
||||
:02008E000B3035
|
||||
:02008F000B3E26
|
||||
:020090000B4A19
|
||||
:020091000B560C
|
||||
:020092000B62FF
|
||||
:020093000B70F0
|
||||
:020094000B7AE5
|
||||
:020095000B82DC
|
||||
:020096000B90CD
|
||||
:020097000B9AC2
|
||||
:020098000BA2B9
|
||||
:020099000BB6A4
|
||||
:02009A000BBC9D
|
||||
:02009B000BC890
|
||||
:02009C000BD285
|
||||
:02009D000BDB7B
|
||||
:02009E000BE471
|
||||
:02009F000BED67
|
||||
:02009B000BC296
|
||||
:02009C000BD087
|
||||
:02009D000BD87E
|
||||
:02009E000BE66F
|
||||
:02009F000BF064
|
||||
:0200A0000BFA59
|
||||
:0200A1000C034E
|
||||
:0200A2000C0D43
|
||||
:0200A3000C153A
|
||||
:0200A4000C1D31
|
||||
:0200A5000C2726
|
||||
:0200A6000C2F1D
|
||||
:0200A7000C3912
|
||||
:0200A8000C4109
|
||||
:0200A1000C024F
|
||||
:0200A2000C0A46
|
||||
:0200A3000C1639
|
||||
:0200A4000C1E30
|
||||
:0200A5000C2A23
|
||||
:0200A6000C321A
|
||||
:0200A7000C3615
|
||||
:0200A8000C4406
|
||||
:0200A9000C4AFF
|
||||
:0200AA000C52F6
|
||||
:0200AB000C59EE
|
||||
:0200AC000C61E5
|
||||
:0200AD000C6DD8
|
||||
:0200AE000C73D1
|
||||
:0200AA000C54F4
|
||||
:0200AB000C5EE9
|
||||
:0200AC000C66E0
|
||||
:0200AD000C6ADB
|
||||
:0200AE000C70D4
|
||||
:0200AF000C7AC9
|
||||
:0200B0000C80C2
|
||||
:0200B1000C8BB6
|
||||
:0200B2000C91AF
|
||||
:0200B3000C99A6
|
||||
:0200B4000CA19D
|
||||
:0200B5000CA796
|
||||
:0200B6000CAC90
|
||||
:0200B7000CB388
|
||||
:0200B8000CBC7E
|
||||
:0200B9000CC277
|
||||
:0200BA000CC771
|
||||
:0200B0000C84BE
|
||||
:0200B1000C8CB5
|
||||
:0200B2000C92AE
|
||||
:0200B3000C96A9
|
||||
:0200B4000C9CA2
|
||||
:0200B5000CA499
|
||||
:0200B6000CAE8E
|
||||
:0200B7000CB685
|
||||
:0200B8000CB882
|
||||
:0200B9000CC079
|
||||
:0200BA000CC870
|
||||
:0200BB000CCE69
|
||||
:0200BC000CD660
|
||||
:0200BC000CD462
|
||||
:0200BD000CDC59
|
||||
:0200BE000CE153
|
||||
:0200BE000CE450
|
||||
:0200BF000CE84B
|
||||
:0200C0000CED45
|
||||
:0200C1000CF73A
|
||||
:0200C0000CF042
|
||||
:0200C1000CF43D
|
||||
:0200C2000CFA36
|
||||
:0200C3000D022C
|
||||
:0200C4000D0726
|
||||
:0200C5000D0D1F
|
||||
:0200C6000D1318
|
||||
:0200C7000D1911
|
||||
:0200C8000D1E0B
|
||||
:0200C9000D2305
|
||||
:0200CA000D2700
|
||||
:0200CB000D2FF7
|
||||
:0200CC000D35F0
|
||||
:0200CD000D3AEA
|
||||
:0200C4000D0627
|
||||
:0200C5000D0A22
|
||||
:0200C6000D1417
|
||||
:0200C7000D1614
|
||||
:0200C8000D1C0D
|
||||
:0200C9000D2404
|
||||
:0200CA000D2CFB
|
||||
:0200CB000D2EF8
|
||||
:0200CC000D30F5
|
||||
:0200CD000D38EC
|
||||
:0200CE000D3EE5
|
||||
:0200CF000D42E0
|
||||
:0200D0000D47DA
|
||||
:0200D1000D4DD3
|
||||
:0200D2000D51CE
|
||||
:0200D3000D55C9
|
||||
:0200D4000D59C4
|
||||
:0200D5000D5EBE
|
||||
:0200D6000D63B8
|
||||
:0200D7000D68B2
|
||||
:0200D8000D6CAD
|
||||
:0200D0000D46DB
|
||||
:0200D1000D4CD4
|
||||
:0200D2000D54CB
|
||||
:0200D3000D58C6
|
||||
:0200D4000D5AC3
|
||||
:0200D5000D60BC
|
||||
:0200D6000D66B5
|
||||
:0200D7000D66B4
|
||||
:0200D8000D70A9
|
||||
:0200D9000D72A6
|
||||
:0200DA000D789F
|
||||
:0200DB000D7C9A
|
||||
:0200DC000D7F96
|
||||
:0200DC000D7E97
|
||||
:0200DD000D8292
|
||||
:0200DE000D868D
|
||||
:0200DF000D8C86
|
||||
:0200E0000D9180
|
||||
:0200E1000D937D
|
||||
:0200E2000D9B74
|
||||
:0200E3000D9E70
|
||||
:0200E4000D9F6E
|
||||
:0200E5000DA864
|
||||
:0200E6000DA863
|
||||
:0200E7000DAD5D
|
||||
:0200E8000DB257
|
||||
:0200E9000DB454
|
||||
:0200EA000DB750
|
||||
:0200DF000D8A88
|
||||
:0200E0000D8E83
|
||||
:0200E1000D947C
|
||||
:0200E2000D9679
|
||||
:0200E3000D9A74
|
||||
:0200E4000DA26B
|
||||
:0200E5000DA468
|
||||
:0200E6000DA467
|
||||
:0200E7000DAE5C
|
||||
:0200E8000DB059
|
||||
:0200E9000DB652
|
||||
:0200EA000DBC4B
|
||||
:0200EB000DBC4A
|
||||
:0200EC000DBF46
|
||||
:0200ED000DC143
|
||||
:0200EE000DC53E
|
||||
:0200EF000DCB37
|
||||
:0200F0000DCE33
|
||||
:0200EC000DC045
|
||||
:0200ED000DC440
|
||||
:0200EE000DC241
|
||||
:0200EF000DCA38
|
||||
:0200F0000DCC35
|
||||
:0200F1000DD030
|
||||
:0200F2000DD728
|
||||
:0200F3000DDA24
|
||||
:0200F2000DD22D
|
||||
:0200F3000DD826
|
||||
:0200F4000DDC21
|
||||
:0200F5000DDF1D
|
||||
:0200F6000DE417
|
||||
:0200F7000DE713
|
||||
:0200F8000DE910
|
||||
:0200F5000DDC20
|
||||
:0200F6000DDE1D
|
||||
:0200F7000DE416
|
||||
:0200F8000DEC0D
|
||||
:0200F9000DEC0C
|
||||
:0200FA000DEE09
|
||||
:0200FB000DF006
|
||||
:0200FC000DF500
|
||||
:0200FD000DF9FB
|
||||
:0200FE000DFCF7
|
||||
:0200FF000DFFF3
|
||||
:0200FB000DF600
|
||||
:0200FC000DF401
|
||||
:0200FD000DF6FE
|
||||
:0200FE000DF8FB
|
||||
:0200FF000E02EF
|
||||
:00000001ff
|
||||
|
|
@ -7,7 +7,7 @@ module VX_reset_relay #(
|
|||
) (
|
||||
input wire clk,
|
||||
input wire reset,
|
||||
output wire [NUM_NODES-1:0] reset_out
|
||||
output wire [NUM_NODES-1:0] reset_o
|
||||
);
|
||||
|
||||
if (DEPTH > 1) begin
|
||||
|
|
@ -25,7 +25,7 @@ module VX_reset_relay #(
|
|||
reset_r[0] <= {NUM_NODES{reset}};
|
||||
end
|
||||
end
|
||||
assign reset_out = reset_r[DEPTH-1];
|
||||
assign reset_o = reset_r[DEPTH-1];
|
||||
end else if (DEPTH == 1) begin
|
||||
reg [NUM_NODES-1:0] reset_r;
|
||||
if (ASYNC) begin
|
||||
|
|
@ -37,10 +37,10 @@ module VX_reset_relay #(
|
|||
reset_r <= {NUM_NODES{reset}};
|
||||
end
|
||||
end
|
||||
assign reset_out = reset_r;
|
||||
assign reset_o = reset_r;
|
||||
end else begin
|
||||
`UNUSED_VAR (clk)
|
||||
assign reset_out = {NUM_NODES{reset}};
|
||||
assign reset_o = {NUM_NODES{reset}};
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -40,8 +40,11 @@ set_global_assignment -name VERILOG_MACRO SYNTHESIS
|
|||
set_global_assignment -name VERILOG_MACRO NDEBUG
|
||||
set_global_assignment -name MESSAGE_DISABLE 16818
|
||||
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||
|
||||
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name USE_HIGH_SPEED_ADDER ON
|
||||
set_global_assignment -name MUX_RESTRUCTURE ON
|
||||
#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
|
||||
#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue