mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-24 13:57:17 -04:00
Fixed Verilator
This commit is contained in:
felsabbagh3
parent
4184980188
commit
3a45375596
3 changed files with 131 additions and 91 deletions
|
|
@ -12,7 +12,7 @@
|
|||
|
||||
// `define SYN 1
|
||||
// `define ASIC 1
|
||||
`define SYN_FUNC 1
|
||||
// `define SYN_FUNC 1
|
||||
|
||||
`define NUM_BARRIERS 4
|
||||
|
||||
|
|
@ -128,14 +128,16 @@
|
|||
|
||||
// `define PARAM
|
||||
|
||||
// oooooo
|
||||
|
||||
//Cache configurations
|
||||
//Cache configurations
|
||||
//Bytes
|
||||
`define ICACHE_SIZE 1024
|
||||
`define ICACHE_SIZE 4096
|
||||
`define ICACHE_WAYS 2
|
||||
//Bytes
|
||||
`define ICACHE_BLOCK 16
|
||||
`define ICACHE_BANKS 1
|
||||
`define ICACHE_BLOCK 64
|
||||
`define ICACHE_BANKS 4
|
||||
`define ICACHE_LOG_NUM_BANKS `CLOG2(`ICACHE_BANKS)
|
||||
|
||||
`define ICACHE_NUM_WORDS_PER_BLOCK (`ICACHE_BLOCK / (`ICACHE_BANKS * 4))
|
||||
|
|
|
|||
20
rtl/Vortex.v
20
rtl/Vortex.v
|
|
@ -44,6 +44,26 @@ module Vortex
|
|||
);
|
||||
|
||||
|
||||
reg[31:0] icache_banks = `ICACHE_BANKS;
|
||||
reg[31:0] icache_num_words_per_block = `ICACHE_NUM_WORDS_PER_BLOCK;
|
||||
|
||||
|
||||
reg[31:0] dcache_banks = `DCACHE_BANKS;
|
||||
reg[31:0] dcache_num_words_per_block = `DCACHE_NUM_WORDS_PER_BLOCK;
|
||||
|
||||
reg[31:0] number_threads = `NT;
|
||||
reg[31:0] number_warps = `NW;
|
||||
|
||||
always @(posedge clk) begin
|
||||
icache_banks <= icache_banks;
|
||||
icache_num_words_per_block <= icache_num_words_per_block;
|
||||
|
||||
dcache_banks <= dcache_banks;
|
||||
dcache_num_words_per_block <= dcache_num_words_per_block;
|
||||
|
||||
number_threads <= number_threads;
|
||||
number_warps <= number_warps;
|
||||
end
|
||||
|
||||
wire memory_delay;
|
||||
wire gpr_stage_delay;
|
||||
|
|
|
|||
|
|
@ -46,8 +46,10 @@ class Vortex
|
|||
VVortex * vortex;
|
||||
|
||||
unsigned start_pc;
|
||||
bool refill;
|
||||
unsigned refill_addr;
|
||||
bool refill_d;
|
||||
unsigned refill_addr_d;
|
||||
bool refill_i;
|
||||
unsigned refill_addr_i;
|
||||
long int curr_cycle;
|
||||
bool stop;
|
||||
bool unit_test;
|
||||
|
|
@ -154,38 +156,66 @@ void Vortex::print_stats(bool cycle_test)
|
|||
bool Vortex::ibus_driver()
|
||||
{
|
||||
|
||||
////////////////////// IBUS //////////////////////
|
||||
unsigned new_PC;
|
||||
bool stop = false;
|
||||
uint32_t curr_inst = 0;
|
||||
vortex->i_m_ready_i = false;
|
||||
|
||||
curr_inst = 0xdeadbeef;
|
||||
|
||||
new_PC = vortex->icache_request_pc_address;
|
||||
ram.getWord(new_PC, &curr_inst);
|
||||
vortex->icache_response_instruction = curr_inst;
|
||||
|
||||
// std::cout << std::hex << "IReq: " << vortex->icache_request_pc_address << "\tResp: " << curr_inst << "\n";
|
||||
|
||||
// printf("\n\n---------------------------------------------\n(%x) Inst: %x\n", new_PC, curr_inst);
|
||||
// printf("\n");
|
||||
////////////////////// IBUS //////////////////////
|
||||
|
||||
|
||||
////////////////////// STATS //////////////////////
|
||||
|
||||
|
||||
if (((((unsigned int)curr_inst) != 0) && (((unsigned int)curr_inst) != 0xffffffff)))
|
||||
{
|
||||
++stats_dynamic_inst;
|
||||
stop = false;
|
||||
} else
|
||||
{
|
||||
// printf("Ibus requesting stop: %x\n", curr_inst);
|
||||
stop = true;
|
||||
|
||||
// int dcache_num_words_per_block
|
||||
|
||||
if (refill_i)
|
||||
{
|
||||
refill_i = false;
|
||||
vortex->i_m_ready_i = true;
|
||||
|
||||
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
|
||||
{
|
||||
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
|
||||
{
|
||||
unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
|
||||
unsigned curr_addr = refill_addr_i + (4*curr_index);
|
||||
|
||||
unsigned curr_value;
|
||||
ram.getWord(curr_addr, &curr_value);
|
||||
|
||||
vortex->i_m_readdata_i[curr_bank][curr_word] = curr_value;
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (vortex->o_m_valid_i)
|
||||
{
|
||||
|
||||
if (vortex->o_m_read_or_write_i)
|
||||
{
|
||||
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
|
||||
unsigned base_addr = vortex->o_m_evict_addr_i;
|
||||
|
||||
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__icache_banks; curr_bank++)
|
||||
{
|
||||
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__icache_num_words_per_block; curr_word++)
|
||||
{
|
||||
unsigned curr_index = (curr_word * vortex->Vortex__DOT__icache_banks) + curr_bank;
|
||||
unsigned curr_addr = base_addr + (4*curr_index);
|
||||
|
||||
unsigned curr_value = vortex->o_m_writedata_i[curr_bank][curr_word];
|
||||
|
||||
ram.writeWord( curr_addr, &curr_value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Respond next cycle
|
||||
refill_i = true;
|
||||
refill_addr_i = vortex->o_m_read_addr_i;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return stop;
|
||||
|
||||
return false;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -197,6 +227,7 @@ void Vortex::io_handler()
|
|||
|
||||
char c = (char) data_write;
|
||||
std::cerr << c;
|
||||
std::cout << c;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -204,75 +235,62 @@ void Vortex::io_handler()
|
|||
bool Vortex::dbus_driver()
|
||||
{
|
||||
|
||||
// printf("****************************\n");
|
||||
vortex->i_m_ready_d = false;
|
||||
|
||||
vortex->i_m_ready_d = 0;
|
||||
for (int i = 0; i < CACHE_NUM_BANKS; i++)
|
||||
{
|
||||
for (int j = 0; j < CACHE_WORDS_PER_BLOCK; j++)
|
||||
|
||||
// int dcache_num_words_per_block
|
||||
|
||||
if (refill_d)
|
||||
{
|
||||
vortex->i_m_readdata_d[i][j] = 0;
|
||||
}
|
||||
}
|
||||
refill_d = false;
|
||||
vortex->i_m_ready_d = true;
|
||||
|
||||
|
||||
if (this->refill)
|
||||
{
|
||||
this->refill = false;
|
||||
|
||||
vortex->i_m_ready_d = 1;
|
||||
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
|
||||
{
|
||||
unsigned new_addr = this->refill_addr + (4*curr_e);
|
||||
|
||||
|
||||
unsigned addr_without_byte = new_addr >> 2;
|
||||
unsigned bank_num = addr_without_byte & 0x7;
|
||||
unsigned addr_wihtout_bank = addr_without_byte >> 3;
|
||||
unsigned offset_num = addr_wihtout_bank & 0x3;
|
||||
|
||||
unsigned value;
|
||||
ram.getWord(new_addr, &value);
|
||||
|
||||
// printf("-------- (%x) i_m_readdata_d[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
|
||||
vortex->i_m_readdata_d[bank_num][offset_num] = value;
|
||||
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (vortex->o_m_valid_d)
|
||||
{
|
||||
// printf("Valid o_m_valid_d\n");
|
||||
if (vortex->o_m_read_or_write_d)
|
||||
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
|
||||
{
|
||||
// printf("Valid write\n");
|
||||
|
||||
for (int curr_e = 0; curr_e < (CACHE_NUM_BANKS*CACHE_WORDS_PER_BLOCK); curr_e++)
|
||||
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
|
||||
{
|
||||
unsigned new_addr = vortex->o_m_evict_addr_d + (4*curr_e);
|
||||
unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
|
||||
unsigned curr_addr = refill_addr_d + (4*curr_index);
|
||||
|
||||
unsigned curr_value;
|
||||
ram.getWord(curr_addr, &curr_value);
|
||||
|
||||
unsigned addr_without_byte = new_addr >> 2;
|
||||
unsigned bank_num = addr_without_byte & 0x7;
|
||||
unsigned addr_wihtout_bank = addr_without_byte >> 3;
|
||||
unsigned offset_num = addr_wihtout_bank & 0x3;
|
||||
vortex->i_m_readdata_d[curr_bank][curr_word] = curr_value;
|
||||
|
||||
|
||||
unsigned new_value = vortex->o_m_writedata_d[bank_num][offset_num];
|
||||
|
||||
ram.writeWord( new_addr, &new_value);
|
||||
|
||||
// printf("+++++++ (%x) writeback[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, new_value);
|
||||
// printf("+++++++ (%x) i_m_readdata_d[%d][%d] (%d) = %d\n", new_addr, bank_num, offset_num, curr_e, value);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
// Respond next cycle
|
||||
this->refill = true;
|
||||
this->refill_addr = vortex->o_m_read_addr_d;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (vortex->o_m_valid_d)
|
||||
{
|
||||
|
||||
if (vortex->o_m_read_or_write_d)
|
||||
{
|
||||
// fprintf(stderr, "++++++++++++++++++++++++++++++++\n");
|
||||
unsigned base_addr = vortex->o_m_evict_addr_d;
|
||||
|
||||
for (int curr_bank = 0; curr_bank < vortex->Vortex__DOT__dcache_banks; curr_bank++)
|
||||
{
|
||||
for (int curr_word = 0; curr_word < vortex->Vortex__DOT__dcache_num_words_per_block; curr_word++)
|
||||
{
|
||||
unsigned curr_index = (curr_word * vortex->Vortex__DOT__dcache_banks) + curr_bank;
|
||||
unsigned curr_addr = base_addr + (4*curr_index);
|
||||
|
||||
unsigned curr_value = vortex->o_m_writedata_d[curr_bank][curr_word];
|
||||
|
||||
ram.writeWord( curr_addr, &curr_value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Respond next cycle
|
||||
refill_d = true;
|
||||
refill_addr_d = vortex->o_m_read_addr_d;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue