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Connected cache to bank
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felsabbagh3
parent
fc5621cd1d
commit
3a970bbe7b
4 changed files with 132 additions and 97 deletions
42
rtl/VX_cache/VX_bank.v
Normal file
42
rtl/VX_cache/VX_bank.v
Normal file
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@ -0,0 +1,42 @@
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`include "VX_cache_config.v"
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module VX_bank (
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input wire clk,
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input wire reset,
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// Input Core Request
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input wire [`NUMBER_REQUESTS-1:0] bank_valids,
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input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr,
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input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata,
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input wire [4:0] bank_rd,
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input wire [1:0] bank_wb,
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input wire [`NW_M1:0] bank_warp_num,
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input wire [2:0] bank_mem_read,
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input wire [2:0] bank_mem_write,
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// Output Core WB
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input wire bank_wb_pop,
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output wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] bank_wb_tid,
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output wire [4:0] bank_wb_rd,
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output wire [1:0] bank_wb_wb,
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output wire [`NW_M1:0] bank_wb_warp_num,
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output wire [31:0] bank_wb_data,
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// Dram Fill Requests
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output wire dram_fill_req,
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output wire[31:0] dram_fill_req_addr,
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input wire dram_fill_req_queue_full,
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// Dram Fill Response
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_addr,
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input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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// Dram WB Requests
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input wire dram_wb_queue_pop,
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output wire dram_wb_req,
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output wire[31:0] dram_wb_req_addr,
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output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data
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);
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endmodule
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@ -41,23 +41,23 @@ module VX_cache (
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);
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wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids;
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wire [`NUMBER_BANKS-1:0] per_bank_wb_pop;
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wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid;
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wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
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wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
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wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
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wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data;
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wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_valids;
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wire [`NUMBER_BANKS-1:0] per_bank_wb_pop;
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wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid;
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wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd;
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wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb;
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wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num;
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wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data;
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wire dfqq_full;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req;
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wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
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wire dfqq_full;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_fill_req;
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wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_fill_req_addr;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req;
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wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
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wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_queue_pop;
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wire[`NUMBER_BANKS-1:0] per_bank_dram_wb_req;
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wire[`NUMBER_BANKS-1:0][31:0] per_bank_dram_wb_req_addr;
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wire[`NUMBER_BANKS-1]:0[`BANK_LINE_SIZE_RNG][31:0] per_bank_dram_wb_req_data;
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VX_cache_dram_req_arb VX_cache_dram_req_arb(
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.clk (clk),
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@ -103,34 +103,34 @@ module VX_cache (
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generate
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integer curr_bank;
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for (curr_bank = 0; curr_bank < `NUMBER_BANKS; curr_bank=curr_bank+1) begin
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wire [`NUMBER_REQUESTS-1:0] curr_bank_valids;
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wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
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wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata;
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wire [4:0] curr_bank_rd;
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wire [1:0] curr_bank_wb;
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wire [`NW_M1:0] curr_bank_warp_num;
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wire [2:0] curr_bank_mem_read;
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wire [2:0] curr_bank_mem_write;
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wire [`NUMBER_REQUESTS-1:0] curr_bank_valids;
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wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_addr;
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wire [`NUMBER_REQUESTS-1:0][31:0] curr_bank_writedata;
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wire [4:0] curr_bank_rd;
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wire [1:0] curr_bank_wb;
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wire [`NW_M1:0] curr_bank_warp_num;
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wire [2:0] curr_bank_mem_read;
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wire [2:0] curr_bank_mem_write;
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wire curr_bank_wb_pop;
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wire [`NUMBER_REQUESTS-1:0] curr_bank_wb_tid;
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wire [4:0] curr_bank_wb_rd;
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wire [1:0] curr_bank_wb_wb;
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wire [`NW_M1:0] curr_bank_wb_warp_num;
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wire [31:0] curr_bank_wb_data;
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wire curr_bank_wb_pop;
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wire [`vx_clog2(`NUMBER_REQUESTS)-1:0] curr_bank_wb_tid;
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wire [4:0] curr_bank_wb_rd;
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wire [1:0] curr_bank_wb_wb;
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wire [`NW_M1:0] curr_bank_wb_warp_num;
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wire [31:0] curr_bank_wb_data;
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wire curr_bank_dram_fill_rsp;
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wire [31:0] curr_bank_dram_fill_rsp_addr;
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wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data;
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wire curr_bank_dram_fill_rsp;
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wire [31:0] curr_bank_dram_fill_rsp_addr;
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wire [`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_fill_rsp_data;
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wire curr_bank_dfqq_full;
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wire curr_bank_dram_fill_req;
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wire[31:0] curr_bank_dram_fill_req_addr;
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wire curr_bank_dfqq_full;
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wire curr_bank_dram_fill_req;
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wire[31:0] curr_bank_dram_fill_req_addr;
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wire curr_bank_dram_wb_queue_pop;
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wire curr_bank_dram_wb_req;
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wire[31:0] curr_bank_dram_wb_req_addr;
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wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data;
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wire curr_bank_dram_wb_queue_pop;
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wire curr_bank_dram_wb_req;
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wire[31:0] curr_bank_dram_wb_req_addr;
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wire[`BANK_LINE_SIZE_RNG][31:0] curr_bank_dram_wb_req_data;
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// Core Req
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assign curr_bank_valids = per_bank_valids[curr_bank];
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@ -150,16 +150,16 @@ module VX_cache (
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assign per_bank_wb_warp_num[curr_bank] = curr_bank_wb_warp_num;
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assign per_bank_wb_data [curr_bank] = curr_bank_wb_data;
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// Dram fill response
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assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
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assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
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assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
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// Dram fill request
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assign curr_bank_dfqq_full = dfqq_full;
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assign per_bank_dram_fill_req[curr_bank] = curr_bank_dram_fill_req;
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assign per_bank_dram_fill_req_addr[curr_bank] = curr_bank_dram_fill_req_addr;
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// Dram fill response
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assign curr_bank_dram_fill_rsp = (`NUMBER_BANKS == 1) || (dram_fill_addr[`BANK_SELECT_ADDR_RNG] == curr_bank);
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assign curr_bank_dram_fill_rsp_addr = dram_fill_rsp_addr;
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assign curr_bank_dram_fill_rsp_data = dram_fill_rsp_data;
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// Dram writeback request
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assign curr_bank_dram_wb_queue_pop = per_bank_dram_wb_queue_pop[curr_bank];
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assign per_bank_dram_wb_req[curr_bank] = curr_bank_dram_wb_req;
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@ -167,8 +167,42 @@ module VX_cache (
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assign per_bank_dram_wb_req_data[curr_bank] = curr_bank_dram_wb_req_data;
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VX_cache_bank bank (
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VX_bank bank (
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.clk (clk),
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.reset (reset),
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// Core req
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.bank_valids (curr_bank_valids),
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.bank_addr (curr_bank_addr),
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.bank_writedata (curr_bank_writedata),
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.bank_rd (curr_bank_rd),
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.bank_wb (curr_bank_wb),
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.bank_warp_num (curr_bank_warp_num),
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.bank_mem_read (curr_bank_mem_read),
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.bank_mem_write (curr_bank_mem_write),
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// Output core wb
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.bank_wb_pop (curr_bank_wb_pop),
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.bank_wb_tid (curr_bank_wb_tid),
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.bank_wb_rd (curr_bank_wb_rd),
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.bank_wb_wb (curr_bank_wb_wb),
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.bank_wb_warp_num (curr_bank_wb_warp_num),
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.bank_wb_data (curr_bank_wb_data),
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// Dram fill req
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.dram_fill_req (curr_bank_dram_fill_req),
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.dram_fill_req_addr (curr_bank_dram_fill_req_addr),
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.dram_fill_req_queue_full(curr_bank_dfqq_full),
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// Dram fill rsp
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.dram_fill_rsp (curr_bank_dram_fill_rsp),
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.dram_fill_addr (curr_bank_dram_fill_rsp_addr),
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.dram_fill_rsp_data (curr_bank_dram_fill_rsp_data),
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// Dram writeback
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.dram_wb_queue_pop (curr_bank_dram_wb_queue_pop),
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.dram_wb_req (curr_bank_dram_wb_req),
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.dram_wb_req_addr (curr_bank_dram_wb_req_addr),
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.dram_wb_req_data (curr_bank_dram_wb_req_data)
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);
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end
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@ -1,41 +0,0 @@
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`include "VX_cache_config.v"
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module VX_cache_bank (
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input wire clk,
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input wire reset,
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// Input Core Request
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input wire [`NUMBER_REQUESTS-1:0] bank_valids,
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input wire [`NUMBER_REQUESTS-1:0][31:0] bank_addr,
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input wire [`NUMBER_REQUESTS-1:0][31:0] bank_writedata,
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input wire [4:0] bank_rd,
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input wire [`NW_M1:0] bank_warp_num,
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input wire [2:0] bank_mem_read,
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input wire [2:0] bank_mem_write,
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// Output Core WB
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input wire bank_wb_pop,
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output wire [`NUMBER_REQUESTS-1:0] bank_wb_valid,
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output wire [4:0] bank_wb_rd,
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output wire [1:0] bank_wb_wb,
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output wire [`NW_M1:0] bank_wb_warp_num,
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output wire [31:0] bank_wb_data,
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// Dram Fill Requests
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output wire dram_fill_req,
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output wire[31:0] dram_fill_req_addr,
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input wire dram_fill_req_queue_full,
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// Dram Fill Response
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input wire dram_fill_rsp,
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input wire [31:0] dram_fill_addr,
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input wire[`BANK_LINE_SIZE_RNG][31:0] dram_fill_rsp_data,
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// Dram WB Requests
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input wire dram_wb_queue_pop,
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output wire dram_wb_req,
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output wire[31:0] dram_wb_req_addr,
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output wire[`BANK_LINE_SIZE_RNG][31:0] dram_wb_req_data
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);
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endmodule
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@ -4,21 +4,21 @@
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module VX_cache_wb_sel_merge (
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// Per Bank WB
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input wire [`NUMBER_BANKS-1:0][`NUMBER_REQUESTS-1:0] per_bank_wb_tid,
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input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd,
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input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb,
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input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num,
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input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data,
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output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop,
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input wire [`NUMBER_BANKS-1:0][`vx_clog2(`NUMBER_REQUESTS)-1:0] per_bank_wb_tid,
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input wire [`NUMBER_BANKS-1:0][4:0] per_bank_wb_rd,
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input wire [`NUMBER_BANKS-1:0][1:0] per_bank_wb_wb,
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input wire [`NUMBER_BANKS-1:0][`NW_M1:0] per_bank_wb_warp_num,
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input wire [`NUMBER_BANKS-1:0][31:0] per_bank_wb_data,
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output wire [`NUMBER_BANKS-1:0] per_bank_wb_pop,
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// Core Writeback
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input wire core_no_wb_slot,
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output reg [`NUMBER_REQUESTS-1:0] core_wb_valid,
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output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata
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output wire [4:0] core_wb_req_rd,
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output wire [1:0] core_wb_req_wb,
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output wire [`NW_M1:0] core_wb_warp_num,
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input wire core_no_wb_slot,
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output reg [`NUMBER_REQUESTS-1:0] core_wb_valid,
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output reg [`NUMBER_REQUESTS-1:0][31:0] core_wb_readdata
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output wire [4:0] core_wb_req_rd,
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output wire [1:0] core_wb_req_wb,
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output wire [`NW_M1:0] core_wb_warp_num,
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);
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