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Using LUTRAM for elastic buffers

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This commit is contained in:
Blaise Tine 2024-07-09 13:35:58 -07:00
parent 3efced37c5
commit 3ab353ab61
4 changed files with 110 additions and 95 deletions
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24
hw/rtl/libs/VX_elastic_buffer.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -19,14 +19,14 @@ module VX_elastic_buffer #(
parameter SIZE = 1,
parameter OUT_REG = 0,
parameter LUTRAM = 0
) (
) (
input wire clk,
input wire reset,
input wire valid_in,
output wire ready_in,
output wire ready_in,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
input wire ready_out,
output wire valid_out
@ -55,7 +55,7 @@ module VX_elastic_buffer #(
.ready_out (ready_out)
);
end else if (SIZE == 2) begin
end else if (SIZE == 2 && LUTRAM == 0) begin
VX_skid_buffer #(
.DATAW (DATAW),
@ -71,9 +71,9 @@ module VX_elastic_buffer #(
.data_out (data_out),
.ready_out (ready_out)
);
end else begin
wire empty, full;
wire [DATAW-1:0] data_out_t;
@ -93,7 +93,7 @@ module VX_elastic_buffer #(
.push (push),
.pop (pop),
.data_in(data_in),
.data_out(data_out_t),
.data_out(data_out_t),
.empty (empty),
.full (full),
`UNUSED_PIN (alm_empty),
@ -105,15 +105,15 @@ module VX_elastic_buffer #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (OUT_REG == 2)
.SIZE ((OUT_REG == 2) ? 1 : 0)
) out_buf (
.clk (clk),
.reset (reset),
.valid_in (~empty),
.data_in (data_out_t),
.ready_in (ready_out_t),
.ready_in (ready_out_t),
.valid_out (valid_out),
.data_out (data_out),
.data_out (data_out),
.ready_out (ready_out)
);

84
hw/rtl/libs/VX_fifo_queue.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -22,28 +22,28 @@ module VX_fifo_queue #(
parameter OUT_REG = 0,
parameter LUTRAM = 1,
parameter SIZEW = `CLOG2(DEPTH+1)
) (
) (
input wire clk,
input wire reset,
input wire reset,
input wire push,
input wire pop,
input wire pop,
input wire [DATAW-1:0] data_in,
output wire [DATAW-1:0] data_out,
output wire empty,
output wire empty,
output wire alm_empty,
output wire full,
output wire full,
output wire alm_full,
output wire [SIZEW-1:0] size
);
localparam ADDRW = `CLOG2(DEPTH);
);
localparam ADDRW = `CLOG2(DEPTH);
`STATIC_ASSERT(ALM_FULL > 0, ("alm_full must be greater than 0!"))
`STATIC_ASSERT(ALM_FULL < DEPTH, ("alm_full must be smaller than size!"))
`STATIC_ASSERT(ALM_EMPTY > 0, ("alm_empty must be greater than 0!"))
`STATIC_ASSERT(ALM_EMPTY < DEPTH, ("alm_empty must be smaller than size!"))
`STATIC_ASSERT(`IS_POW2(DEPTH), ("size must be a power of 2!"))
if (DEPTH == 1) begin
reg [DATAW-1:0] head_r;
@ -52,7 +52,7 @@ module VX_fifo_queue #(
always @(posedge clk) begin
if (reset) begin
head_r <= '0;
size_r <= '0;
size_r <= '0;
end else begin
`ASSERT(~push || ~full, ("runtime error: writing to a full queue"));
`ASSERT(~pop || ~empty, ("runtime error: reading an empty queue"));
@ -63,11 +63,11 @@ module VX_fifo_queue #(
end else if (pop) begin
size_r <= '0;
end
if (push) begin
if (push) begin
head_r <= data_in;
end
end
end
end
assign data_out = head_r;
assign empty = (size_r == 0);
@ -77,7 +77,7 @@ module VX_fifo_queue #(
assign size = size_r;
end else begin
reg empty_r, alm_empty_r;
reg full_r, alm_full_r;
reg [ADDRW-1:0] used_r;
@ -86,8 +86,8 @@ module VX_fifo_queue #(
always @(posedge clk) begin
if (reset) begin
empty_r <= 1;
alm_empty_r <= 1;
full_r <= 0;
alm_empty_r <= 1;
full_r <= 0;
alm_full_r <= 0;
used_r <= '0;
end else begin
@ -106,21 +106,21 @@ module VX_fifo_queue #(
end else if (pop) begin
full_r <= 0;
if (used_r == ADDRW'(ALM_FULL))
alm_full_r <= 0;
alm_full_r <= 0;
if (used_r == ADDRW'(1))
empty_r <= 1;
if (used_r == ADDRW'(ALM_EMPTY+1))
alm_empty_r <= 1;
end
used_r <= used_n;
end
end
used_r <= used_n;
end
end
if (DEPTH == 2) begin
if (DEPTH == 2 && LUTRAM == 0) begin
assign used_n = used_r ^ (push ^ pop);
if (0 == OUT_REG) begin
if (0 == OUT_REG) begin
reg [1:0][DATAW-1:0] shift_reg;
@ -131,8 +131,8 @@ module VX_fifo_queue #(
end
end
assign data_out = shift_reg[!used_r[0]];
assign data_out = shift_reg[!used_r[0]];
end else begin
reg [DATAW-1:0] data_out_r;
@ -152,16 +152,16 @@ module VX_fifo_queue #(
assign data_out = data_out_r;
end
end else begin
assign used_n = $signed(used_r) + ADDRW'($signed(2'(push) - 2'(pop)));
if (0 == OUT_REG) begin
if (0 == OUT_REG) begin
reg [ADDRW-1:0] rd_ptr_r;
reg [ADDRW-1:0] wr_ptr_r;
always @(posedge clk) begin
if (reset) begin
rd_ptr_r <= '0;
@ -169,7 +169,7 @@ module VX_fifo_queue #(
end else begin
wr_ptr_r <= wr_ptr_r + ADDRW'(push);
rd_ptr_r <= rd_ptr_r + ADDRW'(pop);
end
end
end
VX_dp_ram #(
@ -179,8 +179,8 @@ module VX_fifo_queue #(
) dp_ram (
.clk(clk),
.read (1'b1),
.write (push),
`UNUSED_PIN (wren),
.write (push),
`UNUSED_PIN (wren),
.waddr (wr_ptr_r),
.wdata (data_in),
.raddr (rd_ptr_r),
@ -196,18 +196,18 @@ module VX_fifo_queue #(
reg [ADDRW-1:0] rd_ptr_n_r;
always @(posedge clk) begin
if (reset) begin
if (reset) begin
wr_ptr_r <= '0;
rd_ptr_r <= '0;
rd_ptr_n_r <= 1;
end else begin
wr_ptr_r <= wr_ptr_r + ADDRW'(push);
if (pop) begin
rd_ptr_r <= rd_ptr_n_r;
if (DEPTH > 2) begin
rd_ptr_r <= rd_ptr_n_r;
if (DEPTH > 2) begin
rd_ptr_n_r <= rd_ptr_r + ADDRW'(2);
end else begin // (DEPTH == 2);
rd_ptr_n_r <= ~rd_ptr_n_r;
rd_ptr_n_r <= ~rd_ptr_n_r;
end
end
end
@ -227,13 +227,13 @@ module VX_fifo_queue #(
) dp_ram (
.clk (clk),
.read (1'b1),
.write (push),
`UNUSED_PIN (wren),
.write (push),
`UNUSED_PIN (wren),
.waddr (wr_ptr_r),
.wdata (data_in),
.raddr (rd_ptr_n_r),
.rdata (dout)
);
);
always @(posedge clk) begin
if (push && (empty_r || (going_empty && pop))) begin
@ -246,12 +246,12 @@ module VX_fifo_queue #(
assign data_out = dout_r;
end
end
assign empty = empty_r;
assign empty = empty_r;
assign alm_empty = alm_empty_r;
assign full = full_r;
assign alm_full = alm_full_r;
assign size = {full_r, used_r};
assign size = {full_r, used_r};
end
endmodule

68
hw/rtl/libs/VX_stream_arb.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -20,7 +20,8 @@ module VX_stream_arb #(
parameter DATAW = 1,
parameter `STRING ARBITER = "P",
parameter MAX_FANOUT = `MAX_FANOUT,
parameter OUT_BUF = 0 ,
parameter OUT_BUF = 0,
parameter LUTRAM = 0,
parameter NUM_REQS = `CDIV(NUM_INPUTS, NUM_OUTPUTS),
parameter LOG_NUM_REQS = `CLOG2(NUM_REQS),
parameter NUM_REQS_W = `UP(LOG_NUM_REQS)
@ -42,7 +43,7 @@ module VX_stream_arb #(
if (NUM_OUTPUTS > 1) begin
// (#inputs > #outputs) and (#outputs > 1)
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
localparam BATCH_BEGIN = i * NUM_REQS;
@ -57,7 +58,8 @@ module VX_stream_arb #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (OUT_BUF)
.OUT_BUF (OUT_BUF),
.LUTRAM (LUTRAM)
) arb_slice (
.clk (clk),
.reset (slice_reset),
@ -81,8 +83,8 @@ module VX_stream_arb #(
wire [NUM_BATCHES-1:0] valid_tmp;
wire [NUM_BATCHES-1:0][DATAW+LOG_NUM_REQS2-1:0] data_tmp;
wire [NUM_BATCHES-1:0] ready_tmp;
wire [NUM_BATCHES-1:0] ready_tmp;
for (genvar i = 0; i < NUM_BATCHES; ++i) begin
localparam BATCH_BEGIN = i * MAX_FANOUT;
@ -97,18 +99,19 @@ module VX_stream_arb #(
if (MAX_FANOUT != 1) begin
VX_stream_arb #(
.NUM_INPUTS (BATCH_SIZE),
.NUM_OUTPUTS (1),
.NUM_OUTPUTS (1),
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (OUT_BUF)
.OUT_BUF (OUT_BUF),
.LUTRAM (LUTRAM)
) fanout_slice_arb (
.clk (clk),
.reset (slice_reset),
.valid_in (valid_in[BATCH_END-1: BATCH_BEGIN]),
.data_in (data_in[BATCH_END-1: BATCH_BEGIN]),
.ready_in (ready_in[BATCH_END-1: BATCH_BEGIN]),
.valid_out (valid_tmp[i]),
.ready_in (ready_in[BATCH_END-1: BATCH_BEGIN]),
.valid_out (valid_tmp[i]),
.data_out (data_tmp_u),
.sel_out (sel_tmp_u),
.ready_out (ready_tmp[i])
@ -123,11 +126,12 @@ module VX_stream_arb #(
VX_stream_arb #(
.NUM_INPUTS (NUM_BATCHES),
.NUM_OUTPUTS (1),
.NUM_OUTPUTS (1),
.DATAW (DATAW + LOG_NUM_REQS2),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (OUT_BUF)
.OUT_BUF (OUT_BUF),
.LUTRAM (LUTRAM)
) fanout_join_arb (
.clk (clk),
.reset (reset),
@ -150,7 +154,7 @@ module VX_stream_arb #(
wire valid_in_r;
wire [DATAW-1:0] data_in_r;
wire ready_in_r;
wire arb_valid;
wire [NUM_REQS_W-1:0] arb_index;
wire [NUM_REQS-1:0] arb_onehot;
@ -181,7 +185,8 @@ module VX_stream_arb #(
VX_elastic_buffer #(
.DATAW (LOG_NUM_REQS + DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)),
.LUTRAM (LUTRAM)
) out_buf (
.clk (clk),
.reset (reset),
@ -214,7 +219,8 @@ module VX_stream_arb #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (OUT_BUF)
.OUT_BUF (OUT_BUF),
.LUTRAM (LUTRAM)
) arb_slice (
.clk (clk),
.reset (slice_reset),
@ -248,19 +254,20 @@ module VX_stream_arb #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (OUT_BUF)
.OUT_BUF (OUT_BUF),
.LUTRAM (LUTRAM)
) fanout_fork_arb (
.clk (clk),
.reset (reset),
.valid_in (valid_in),
.ready_in (ready_in),
.data_in (data_in),
.data_in (data_in),
.data_out (data_tmp),
.valid_out (valid_tmp),
.ready_out (ready_tmp),
`UNUSED_PIN (sel_out)
);
for (genvar i = 0; i < NUM_BATCHES; ++i) begin
localparam BATCH_BEGIN = i * MAX_FANOUT;
@ -271,11 +278,12 @@ module VX_stream_arb #(
VX_stream_arb #(
.NUM_INPUTS (1),
.NUM_OUTPUTS (BATCH_SIZE),
.NUM_OUTPUTS (BATCH_SIZE),
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (OUT_BUF)
.OUT_BUF (OUT_BUF),
.LUTRAM (LUTRAM)
) fanout_slice_arb (
.clk (clk),
.reset (slice_reset),
@ -293,8 +301,8 @@ module VX_stream_arb #(
// (#inputs == 1) and (#outputs <= max_fanout)
wire [NUM_OUTPUTS-1:0] ready_in_r;
wire [NUM_OUTPUTS-1:0] ready_in_r;
wire [NUM_OUTPUTS-1:0] arb_requests;
wire arb_valid;
wire [NUM_OUTPUTS-1:0] arb_onehot;
@ -320,9 +328,10 @@ module VX_stream_arb #(
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)),
.LUTRAM (LUTRAM)
) out_buf (
.clk (clk),
.reset (reset),
@ -337,7 +346,7 @@ module VX_stream_arb #(
end
assign sel_out = 0;
end else begin
// #Inputs == #Outputs
@ -349,7 +358,8 @@ module VX_stream_arb #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)),
.LUTRAM (LUTRAM)
) out_buf (
.clk (clk),
.reset (out_buf_reset),
@ -363,6 +373,6 @@ module VX_stream_arb #(
assign sel_out[i] = NUM_REQS_W'(i);
end
end
endmodule
`TRACING_ON

29
hw/rtl/libs/VX_stream_xbar.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -22,6 +22,7 @@ module VX_stream_xbar #(
parameter OUT_WIDTH = `LOG2UP(NUM_OUTPUTS),
parameter ARBITER = "P",
parameter OUT_BUF = 0,
parameter LUTRAM = 0,
parameter MAX_FANOUT = `MAX_FANOUT,
parameter PERF_CTR_BITS = `CLOG2(NUM_INPUTS+1)
) (
@ -36,7 +37,7 @@ module VX_stream_xbar #(
output wire [NUM_INPUTS-1:0] ready_in,
output wire [NUM_OUTPUTS-1:0] valid_out,
output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out,
output wire [NUM_OUTPUTS-1:0][DATAW-1:0] data_out,
output wire [NUM_OUTPUTS-1:0][IN_WIDTH-1:0] sel_out,
input wire [NUM_OUTPUTS-1:0] ready_out
);
@ -66,7 +67,8 @@ module VX_stream_xbar #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (OUT_BUF)
.OUT_BUF (OUT_BUF),
.LUTRAM (LUTRAM)
) xbar_arb (
.clk (clk),
.reset (slice_reset),
@ -94,7 +96,8 @@ module VX_stream_xbar #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_BUF (OUT_BUF)
.OUT_BUF (OUT_BUF),
.LUTRAM (LUTRAM)
) xbar_arb (
.clk (clk),
.reset (reset),
@ -124,13 +127,14 @@ module VX_stream_xbar #(
assign ready_in = ready_out_r[sel_in];
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
`RESET_RELAY (out_buf_reset, reset);
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)),
.LUTRAM (LUTRAM)
) out_buf (
.clk (clk),
.reset (out_buf_reset),
@ -152,7 +156,8 @@ module VX_stream_xbar #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF)),
.LUTRAM (LUTRAM)
) out_buf (
.clk (clk),
.reset (reset),
@ -172,7 +177,7 @@ module VX_stream_xbar #(
// compute inputs collision
// we have a collision when there exists a valid transfer with multiple input candicates
// we count the unique duplicates each cycle.
reg [NUM_INPUTS-1:0] per_cycle_collision, per_cycle_collision_r;
wire [`CLOG2(NUM_INPUTS+1)-1:0] collision_count;
reg [PERF_CTR_BITS-1:0] collisions_r;
@ -182,14 +187,14 @@ module VX_stream_xbar #(
for (integer i = 0; i < NUM_INPUTS; ++i) begin
for (integer j = 1; j < (NUM_INPUTS-i); ++j) begin
per_cycle_collision[i] |= valid_in[i]
&& valid_in[j+i]
&& valid_in[j+i]
&& (sel_in[i] == sel_in[j+i])
&& (ready_in[i] | ready_in[j+i]);
end
end
end
`BUFFER(per_cycle_collision_r, per_cycle_collision);
`BUFFER(per_cycle_collision_r, per_cycle_collision);
`POP_COUNT(collision_count, per_cycle_collision_r);
always @(posedge clk) begin