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register vs combinational signals naming consistency

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This commit is contained in:
Blaise Tine 2024-08-24 16:59:18 -07:00
parent 4570a20eee
commit 3b336d7fb3
12 changed files with 302 additions and 302 deletions
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8
hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -414,12 +414,12 @@ module VX_cache_bank #(
wire [LINE_SIZE-1:0] dirty_byteen_st1;
if (`CS_WORDS_PER_LINE > 1) begin
reg [LINE_SIZE-1:0] write_byteen_r;
reg [`CS_WORDS_PER_LINE-1:0][WORD_SIZE-1:0] write_byteen_w;
always @(*) begin
write_byteen_r = '0;
write_byteen_r[wsel_st1 * WORD_SIZE +: WORD_SIZE] = byteen_st1;
write_byteen_w = '0;
write_byteen_w[wsel_st1] = byteen_st1;
end
assign write_byteen_st1 = write_byteen_r;
assign write_byteen_st1 = write_byteen_w;
end else begin
assign write_byteen_st1 = byteen_st1;
end

20
hw/rtl/cache/VX_cache_bypass.sv vendored
View file

@ -158,21 +158,21 @@ module VX_cache_bypass #(
wire [CORE_TAG_ID_BITS-1:0] core_req_in_id = core_req_nc_sel_tag[CORE_TAG_ID_BITS-1:0];
if (WORDS_PER_LINE > 1) begin
reg [WORDS_PER_LINE-1:0][WORD_SIZE-1:0] mem_req_byteen_in_r;
reg [WORDS_PER_LINE-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_r;
reg [WORDS_PER_LINE-1:0][WORD_SIZE-1:0] mem_req_byteen_in_w;
reg [WORDS_PER_LINE-1:0][CORE_DATA_WIDTH-1:0] mem_req_data_in_w;
wire [WSEL_BITS-1:0] req_wsel = core_req_nc_sel_addr[WSEL_BITS-1:0];
always @(*) begin
mem_req_byteen_in_r = '0;
mem_req_byteen_in_r[req_wsel] = core_req_nc_sel_byteen;
mem_req_byteen_in_w = '0;
mem_req_byteen_in_w[req_wsel] = core_req_nc_sel_byteen;
mem_req_data_in_r = 'x;
mem_req_data_in_r[req_wsel] = core_req_nc_sel_data;
mem_req_data_in_w = 'x;
mem_req_data_in_w[req_wsel] = core_req_nc_sel_data;
end
assign mem_req_out_byteen = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.byteen : mem_req_byteen_in_r;
assign mem_req_out_data = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.data : mem_req_data_in_r;
assign mem_req_out_byteen = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.byteen : mem_req_byteen_in_w;
assign mem_req_out_data = mem_bus_in_if.req_valid ? mem_bus_in_if.req_data.data : mem_req_data_in_w;
if (NUM_REQS > 1) begin
assign mem_req_tag_id_bypass = MEM_TAG_ID_BITS'({core_req_nc_idx, req_wsel, core_req_in_id});
end else begin
@ -268,10 +268,10 @@ module VX_cache_bypass #(
assign rsp_idx = 1'b0;
end
wire [NUM_REQS-1:0] rsp_nc_valid_r = NUM_REQS'(is_mem_rsp_nc) << rsp_idx;
wire [NUM_REQS-1:0] rsp_nc_valid = NUM_REQS'(is_mem_rsp_nc) << rsp_idx;
for (genvar i = 0; i < NUM_REQS; ++i) begin
assign core_rsp_in_valid[i] = core_bus_out_if[i].rsp_valid || rsp_nc_valid_r[i];
assign core_rsp_in_valid[i] = core_bus_out_if[i].rsp_valid || rsp_nc_valid[i];
assign core_bus_out_if[i].rsp_ready = core_rsp_in_ready[i];
end

152
hw/rtl/core/VX_csr_data.sv
View file

@ -155,41 +155,41 @@ import VX_fpu_pkg::*;
// CSRs read //////////////////////////////////////////////////////////////
reg [`XLEN-1:0] read_data_ro_r;
reg [`XLEN-1:0] read_data_rw_r;
reg read_addr_valid_r;
reg [`XLEN-1:0] read_data_ro_w;
reg [`XLEN-1:0] read_data_rw_w;
reg read_addr_valid_w;
always @(*) begin
read_data_ro_r = '0;
read_data_rw_r = '0;
read_addr_valid_r = 1;
read_data_ro_w = '0;
read_data_rw_w = '0;
read_addr_valid_w = 1;
case (read_addr)
`VX_CSR_MVENDORID : read_data_ro_r = `XLEN'(`VENDOR_ID);
`VX_CSR_MARCHID : read_data_ro_r = `XLEN'(`ARCHITECTURE_ID);
`VX_CSR_MIMPID : read_data_ro_r = `XLEN'(`IMPLEMENTATION_ID);
`VX_CSR_MISA : read_data_ro_r = `XLEN'({2'(`CLOG2(`XLEN/16)), 30'(`MISA_STD)});
`VX_CSR_MVENDORID : read_data_ro_w = `XLEN'(`VENDOR_ID);
`VX_CSR_MARCHID : read_data_ro_w = `XLEN'(`ARCHITECTURE_ID);
`VX_CSR_MIMPID : read_data_ro_w = `XLEN'(`IMPLEMENTATION_ID);
`VX_CSR_MISA : read_data_ro_w = `XLEN'({2'(`CLOG2(`XLEN/16)), 30'(`MISA_STD)});
`ifdef EXT_F_ENABLE
`VX_CSR_FFLAGS : read_data_rw_r = `XLEN'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]);
`VX_CSR_FRM : read_data_rw_r = `XLEN'(fcsr[read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]);
`VX_CSR_FCSR : read_data_rw_r = `XLEN'(fcsr[read_wid]);
`VX_CSR_FFLAGS : read_data_rw_w = `XLEN'(fcsr[read_wid][`FP_FLAGS_BITS-1:0]);
`VX_CSR_FRM : read_data_rw_w = `XLEN'(fcsr[read_wid][`INST_FRM_BITS+`FP_FLAGS_BITS-1:`FP_FLAGS_BITS]);
`VX_CSR_FCSR : read_data_rw_w = `XLEN'(fcsr[read_wid]);
`endif
`VX_CSR_MSCRATCH : read_data_rw_r = mscratch;
`VX_CSR_MSCRATCH : read_data_rw_w = mscratch;
`VX_CSR_WARP_ID : read_data_ro_r = `XLEN'(read_wid);
`VX_CSR_CORE_ID : read_data_ro_r = `XLEN'(CORE_ID);
`VX_CSR_ACTIVE_THREADS: read_data_ro_r = `XLEN'(thread_masks[read_wid]);
`VX_CSR_ACTIVE_WARPS: read_data_ro_r = `XLEN'(active_warps);
`VX_CSR_NUM_THREADS: read_data_ro_r = `XLEN'(`NUM_THREADS);
`VX_CSR_NUM_WARPS : read_data_ro_r = `XLEN'(`NUM_WARPS);
`VX_CSR_NUM_CORES : read_data_ro_r = `XLEN'(`NUM_CORES * `NUM_CLUSTERS);
`VX_CSR_LOCAL_MEM_BASE: read_data_ro_r = `XLEN'(`LMEM_BASE_ADDR);
`VX_CSR_WARP_ID : read_data_ro_w = `XLEN'(read_wid);
`VX_CSR_CORE_ID : read_data_ro_w = `XLEN'(CORE_ID);
`VX_CSR_ACTIVE_THREADS: read_data_ro_w = `XLEN'(thread_masks[read_wid]);
`VX_CSR_ACTIVE_WARPS: read_data_ro_w = `XLEN'(active_warps);
`VX_CSR_NUM_THREADS: read_data_ro_w = `XLEN'(`NUM_THREADS);
`VX_CSR_NUM_WARPS : read_data_ro_w = `XLEN'(`NUM_WARPS);
`VX_CSR_NUM_CORES : read_data_ro_w = `XLEN'(`NUM_CORES * `NUM_CLUSTERS);
`VX_CSR_LOCAL_MEM_BASE: read_data_ro_w = `XLEN'(`LMEM_BASE_ADDR);
`CSR_READ_64(`VX_CSR_MCYCLE, read_data_ro_r, cycles);
`CSR_READ_64(`VX_CSR_MCYCLE, read_data_ro_w, cycles);
`VX_CSR_MPM_RESERVED : read_data_ro_r = 'x;
`VX_CSR_MPM_RESERVED_H : read_data_ro_r = 'x;
`VX_CSR_MPM_RESERVED : read_data_ro_w = 'x;
`VX_CSR_MPM_RESERVED_H : read_data_ro_w = 'x;
`CSR_READ_64(`VX_CSR_MINSTRET, read_data_ro_r, commit_csr_if.instret);
`CSR_READ_64(`VX_CSR_MINSTRET, read_data_ro_w, commit_csr_if.instret);
`VX_CSR_SATP,
`VX_CSR_MSTATUS,
@ -200,77 +200,77 @@ import VX_fpu_pkg::*;
`VX_CSR_MTVEC,
`VX_CSR_MEPC,
`VX_CSR_PMPCFG0,
`VX_CSR_PMPADDR0 : read_data_ro_r = `XLEN'(0);
`VX_CSR_PMPADDR0 : read_data_ro_w = `XLEN'(0);
default: begin
read_addr_valid_r = 0;
read_addr_valid_w = 0;
if ((read_addr >= `VX_CSR_MPM_USER && read_addr < (`VX_CSR_MPM_USER + 32))
|| (read_addr >= `VX_CSR_MPM_USER_H && read_addr < (`VX_CSR_MPM_USER_H + 32))) begin
read_addr_valid_r = 1;
read_addr_valid_w = 1;
`ifdef PERF_ENABLE
case (base_dcrs.mpm_class)
`VX_DCR_MPM_CLASS_CORE: begin
case (read_addr)
// PERF: pipeline
`CSR_READ_64(`VX_CSR_MPM_SCHED_ID, read_data_ro_r, pipeline_perf_if.sched.idles);
`CSR_READ_64(`VX_CSR_MPM_SCHED_ST, read_data_ro_r, pipeline_perf_if.sched.stalls);
`CSR_READ_64(`VX_CSR_MPM_IBUF_ST, read_data_ro_r, pipeline_perf_if.issue.ibf_stalls);
`CSR_READ_64(`VX_CSR_MPM_SCRB_ST, read_data_ro_r, pipeline_perf_if.issue.scb_stalls);
`CSR_READ_64(`VX_CSR_MPM_OPDS_ST, read_data_ro_r, pipeline_perf_if.issue.opd_stalls);
`CSR_READ_64(`VX_CSR_MPM_SCRB_ALU, read_data_ro_r, pipeline_perf_if.issue.units_uses[`EX_ALU]);
`CSR_READ_64(`VX_CSR_MPM_SCHED_ID, read_data_ro_w, pipeline_perf_if.sched.idles);
`CSR_READ_64(`VX_CSR_MPM_SCHED_ST, read_data_ro_w, pipeline_perf_if.sched.stalls);
`CSR_READ_64(`VX_CSR_MPM_IBUF_ST, read_data_ro_w, pipeline_perf_if.issue.ibf_stalls);
`CSR_READ_64(`VX_CSR_MPM_SCRB_ST, read_data_ro_w, pipeline_perf_if.issue.scb_stalls);
`CSR_READ_64(`VX_CSR_MPM_OPDS_ST, read_data_ro_w, pipeline_perf_if.issue.opd_stalls);
`CSR_READ_64(`VX_CSR_MPM_SCRB_ALU, read_data_ro_w, pipeline_perf_if.issue.units_uses[`EX_ALU]);
`ifdef EXT_F_ENABLE
`CSR_READ_64(`VX_CSR_MPM_SCRB_FPU, read_data_ro_r, pipeline_perf_if.issue.units_uses[`EX_FPU]);
`CSR_READ_64(`VX_CSR_MPM_SCRB_FPU, read_data_ro_w, pipeline_perf_if.issue.units_uses[`EX_FPU]);
`else
`CSR_READ_64(`VX_CSR_MPM_SCRB_FPU, read_data_ro_r, `PERF_CTR_BITS'(0));
`CSR_READ_64(`VX_CSR_MPM_SCRB_FPU, read_data_ro_w, `PERF_CTR_BITS'(0));
`endif
`CSR_READ_64(`VX_CSR_MPM_SCRB_LSU, read_data_ro_r, pipeline_perf_if.issue.units_uses[`EX_LSU]);
`CSR_READ_64(`VX_CSR_MPM_SCRB_SFU, read_data_ro_r, pipeline_perf_if.issue.units_uses[`EX_SFU]);
`CSR_READ_64(`VX_CSR_MPM_SCRB_CSRS, read_data_ro_r, pipeline_perf_if.issue.sfu_uses[`SFU_CSRS]);
`CSR_READ_64(`VX_CSR_MPM_SCRB_WCTL, read_data_ro_r, pipeline_perf_if.issue.sfu_uses[`SFU_WCTL]);
`CSR_READ_64(`VX_CSR_MPM_SCRB_LSU, read_data_ro_w, pipeline_perf_if.issue.units_uses[`EX_LSU]);
`CSR_READ_64(`VX_CSR_MPM_SCRB_SFU, read_data_ro_w, pipeline_perf_if.issue.units_uses[`EX_SFU]);
`CSR_READ_64(`VX_CSR_MPM_SCRB_CSRS, read_data_ro_w, pipeline_perf_if.issue.sfu_uses[`SFU_CSRS]);
`CSR_READ_64(`VX_CSR_MPM_SCRB_WCTL, read_data_ro_w, pipeline_perf_if.issue.sfu_uses[`SFU_WCTL]);
// PERF: memory
`CSR_READ_64(`VX_CSR_MPM_IFETCHES, read_data_ro_r, pipeline_perf_if.ifetches);
`CSR_READ_64(`VX_CSR_MPM_LOADS, read_data_ro_r, pipeline_perf_if.loads);
`CSR_READ_64(`VX_CSR_MPM_STORES, read_data_ro_r, pipeline_perf_if.stores);
`CSR_READ_64(`VX_CSR_MPM_IFETCH_LT, read_data_ro_r, pipeline_perf_if.ifetch_latency);
`CSR_READ_64(`VX_CSR_MPM_LOAD_LT, read_data_ro_r, pipeline_perf_if.load_latency);
`CSR_READ_64(`VX_CSR_MPM_IFETCHES, read_data_ro_w, pipeline_perf_if.ifetches);
`CSR_READ_64(`VX_CSR_MPM_LOADS, read_data_ro_w, pipeline_perf_if.loads);
`CSR_READ_64(`VX_CSR_MPM_STORES, read_data_ro_w, pipeline_perf_if.stores);
`CSR_READ_64(`VX_CSR_MPM_IFETCH_LT, read_data_ro_w, pipeline_perf_if.ifetch_latency);
`CSR_READ_64(`VX_CSR_MPM_LOAD_LT, read_data_ro_w, pipeline_perf_if.load_latency);
default:;
endcase
end
`VX_DCR_MPM_CLASS_MEM: begin
case (read_addr)
// PERF: icache
`CSR_READ_64(`VX_CSR_MPM_ICACHE_READS, read_data_ro_r, mem_perf_if.icache.reads);
`CSR_READ_64(`VX_CSR_MPM_ICACHE_MISS_R, read_data_ro_r, mem_perf_if.icache.read_misses);
`CSR_READ_64(`VX_CSR_MPM_ICACHE_MSHR_ST, read_data_ro_r, mem_perf_if.icache.mshr_stalls);
`CSR_READ_64(`VX_CSR_MPM_ICACHE_READS, read_data_ro_w, mem_perf_if.icache.reads);
`CSR_READ_64(`VX_CSR_MPM_ICACHE_MISS_R, read_data_ro_w, mem_perf_if.icache.read_misses);
`CSR_READ_64(`VX_CSR_MPM_ICACHE_MSHR_ST, read_data_ro_w, mem_perf_if.icache.mshr_stalls);
// PERF: dcache
`CSR_READ_64(`VX_CSR_MPM_DCACHE_READS, read_data_ro_r, mem_perf_if.dcache.reads);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_WRITES, read_data_ro_r, mem_perf_if.dcache.writes);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_MISS_R, read_data_ro_r, mem_perf_if.dcache.read_misses);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_MISS_W, read_data_ro_r, mem_perf_if.dcache.write_misses);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_BANK_ST, read_data_ro_r, mem_perf_if.dcache.bank_stalls);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_MSHR_ST, read_data_ro_r, mem_perf_if.dcache.mshr_stalls);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_READS, read_data_ro_w, mem_perf_if.dcache.reads);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_WRITES, read_data_ro_w, mem_perf_if.dcache.writes);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_MISS_R, read_data_ro_w, mem_perf_if.dcache.read_misses);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_MISS_W, read_data_ro_w, mem_perf_if.dcache.write_misses);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_BANK_ST, read_data_ro_w, mem_perf_if.dcache.bank_stalls);
`CSR_READ_64(`VX_CSR_MPM_DCACHE_MSHR_ST, read_data_ro_w, mem_perf_if.dcache.mshr_stalls);
// PERF: lmem
`CSR_READ_64(`VX_CSR_MPM_LMEM_READS, read_data_ro_r, mem_perf_if.lmem.reads);
`CSR_READ_64(`VX_CSR_MPM_LMEM_WRITES, read_data_ro_r, mem_perf_if.lmem.writes);
`CSR_READ_64(`VX_CSR_MPM_LMEM_BANK_ST, read_data_ro_r, mem_perf_if.lmem.bank_stalls);
`CSR_READ_64(`VX_CSR_MPM_LMEM_READS, read_data_ro_w, mem_perf_if.lmem.reads);
`CSR_READ_64(`VX_CSR_MPM_LMEM_WRITES, read_data_ro_w, mem_perf_if.lmem.writes);
`CSR_READ_64(`VX_CSR_MPM_LMEM_BANK_ST, read_data_ro_w, mem_perf_if.lmem.bank_stalls);
// PERF: l2cache
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_READS, read_data_ro_r, mem_perf_if.l2cache.reads);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_WRITES, read_data_ro_r, mem_perf_if.l2cache.writes);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MISS_R, read_data_ro_r, mem_perf_if.l2cache.read_misses);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MISS_W, read_data_ro_r, mem_perf_if.l2cache.write_misses);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_BANK_ST, read_data_ro_r, mem_perf_if.l2cache.bank_stalls);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MSHR_ST, read_data_ro_r, mem_perf_if.l2cache.mshr_stalls);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_READS, read_data_ro_w, mem_perf_if.l2cache.reads);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_WRITES, read_data_ro_w, mem_perf_if.l2cache.writes);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MISS_R, read_data_ro_w, mem_perf_if.l2cache.read_misses);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MISS_W, read_data_ro_w, mem_perf_if.l2cache.write_misses);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_BANK_ST, read_data_ro_w, mem_perf_if.l2cache.bank_stalls);
`CSR_READ_64(`VX_CSR_MPM_L2CACHE_MSHR_ST, read_data_ro_w, mem_perf_if.l2cache.mshr_stalls);
// PERF: l3cache
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_READS, read_data_ro_r, mem_perf_if.l3cache.reads);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_WRITES, read_data_ro_r, mem_perf_if.l3cache.writes);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_MISS_R, read_data_ro_r, mem_perf_if.l3cache.read_misses);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_MISS_W, read_data_ro_r, mem_perf_if.l3cache.write_misses);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_BANK_ST, read_data_ro_r, mem_perf_if.l3cache.bank_stalls);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_MSHR_ST, read_data_ro_r, mem_perf_if.l3cache.mshr_stalls);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_READS, read_data_ro_w, mem_perf_if.l3cache.reads);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_WRITES, read_data_ro_w, mem_perf_if.l3cache.writes);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_MISS_R, read_data_ro_w, mem_perf_if.l3cache.read_misses);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_MISS_W, read_data_ro_w, mem_perf_if.l3cache.write_misses);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_BANK_ST, read_data_ro_w, mem_perf_if.l3cache.bank_stalls);
`CSR_READ_64(`VX_CSR_MPM_L3CACHE_MSHR_ST, read_data_ro_w, mem_perf_if.l3cache.mshr_stalls);
// PERF: memory
`CSR_READ_64(`VX_CSR_MPM_MEM_READS, read_data_ro_r, mem_perf_if.mem.reads);
`CSR_READ_64(`VX_CSR_MPM_MEM_WRITES, read_data_ro_r, mem_perf_if.mem.writes);
`CSR_READ_64(`VX_CSR_MPM_MEM_LT, read_data_ro_r, mem_perf_if.mem.latency);
`CSR_READ_64(`VX_CSR_MPM_MEM_READS, read_data_ro_w, mem_perf_if.mem.reads);
`CSR_READ_64(`VX_CSR_MPM_MEM_WRITES, read_data_ro_w, mem_perf_if.mem.writes);
`CSR_READ_64(`VX_CSR_MPM_MEM_LT, read_data_ro_w, mem_perf_if.mem.latency);
default:;
endcase
end
@ -282,12 +282,12 @@ import VX_fpu_pkg::*;
endcase
end
assign read_data_ro = read_data_ro_r;
assign read_data_rw = read_data_rw_r;
assign read_data_ro = read_data_ro_w;
assign read_data_rw = read_data_rw_w;
`UNUSED_VAR (base_dcrs)
`RUNTIME_ASSERT(~read_enable || read_addr_valid_r, ("%t: *** invalid CSR read address: 0x%0h (#%0d)", $time, read_addr, read_uuid))
`RUNTIME_ASSERT(~read_enable || read_addr_valid_w, ("%t: *** invalid CSR read address: 0x%0h (#%0d)", $time, read_addr, read_uuid))
`ifdef PERF_ENABLE
`UNUSED_VAR (mem_perf_if.icache);

20
hw/rtl/core/VX_decode.sv
View file

@ -15,15 +15,15 @@
`ifdef EXT_F_ENABLE
`define USED_IREG(x) \
x``_r = {1'b0, ``x}; \
x``_v = {1'b0, ``x}; \
use_``x = 1
`define USED_FREG(x) \
x``_r = {1'b1, ``x}; \
x``_v = {1'b1, ``x}; \
use_``x = 1
`else
`define USED_IREG(x) \
x``_r = ``x; \
x``_v = ``x; \
use_``x = 1
`endif
@ -50,7 +50,7 @@ module VX_decode import VX_gpu_pkg::*; #(
reg [`EX_BITS-1:0] ex_type;
reg [`INST_OP_BITS-1:0] op_type;
op_args_t op_args;
reg [`NR_BITS-1:0] rd_r, rs1_r, rs2_r, rs3_r;
reg [`NR_BITS-1:0] rd_v, rs1_v, rs2_v, rs3_v;
reg use_rd, use_rs1, use_rs2, use_rs3;
reg is_wstall;
@ -155,10 +155,10 @@ module VX_decode import VX_gpu_pkg::*; #(
ex_type = '0;
op_type = 'x;
op_args = 'x;
rd_r = '0;
rs1_r = '0;
rs2_r = '0;
rs3_r = '0;
rd_v = '0;
rs1_v = '0;
rs2_v = '0;
rs3_v = '0;
use_rd = 0;
use_rs1 = 0;
use_rs2 = 0;
@ -527,7 +527,7 @@ module VX_decode import VX_gpu_pkg::*; #(
end
// disable write to integer register r0
wire wb = use_rd && (rd_r != 0);
wire wb = use_rd && (rd_v != 0);
VX_elastic_buffer #(
.DATAW (DATAW),
@ -537,7 +537,7 @@ module VX_decode import VX_gpu_pkg::*; #(
.reset (reset),
.valid_in (fetch_if.valid),
.ready_in (fetch_if.ready),
.data_in ({fetch_if.data.uuid, fetch_if.data.wid, fetch_if.data.tmask, fetch_if.data.PC, ex_type, op_type, op_args, wb, rd_r, rs1_r, rs2_r, rs3_r}),
.data_in ({fetch_if.data.uuid, fetch_if.data.wid, fetch_if.data.tmask, fetch_if.data.PC, ex_type, op_type, op_args, wb, rd_v, rs1_v, rs2_v, rs3_v}),
.data_out ({decode_if.data.uuid, decode_if.data.wid, decode_if.data.tmask, decode_if.data.PC, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_args, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3}),
.valid_out (decode_if.valid),
.ready_out (decode_if.ready)

20
hw/rtl/core/VX_gather_unit.sv
View file

@ -94,31 +94,31 @@ module VX_gather_unit import VX_gpu_pkg::*; #(
.ready_out (commit_tmp_if.ready)
);
logic [`NUM_THREADS-1:0] commit_tmask_r;
logic [`NUM_THREADS-1:0][`XLEN-1:0] commit_data_r;
logic [`NUM_THREADS-1:0] commit_tmask_w;
logic [`NUM_THREADS-1:0][`XLEN-1:0] commit_data_w;
if (PID_BITS != 0) begin
always @(*) begin
commit_tmask_r = '0;
commit_data_r = 'x;
commit_tmask_w = '0;
commit_data_w = 'x;
for (integer j = 0; j < NUM_LANES; ++j) begin
commit_tmask_r[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.tmask[j];
commit_data_r[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.data[j];
commit_tmask_w[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.tmask[j];
commit_data_w[commit_tmp_if.data.pid * NUM_LANES + j] = commit_tmp_if.data.data[j];
end
end
end else begin
assign commit_tmask_r = commit_tmp_if.data.tmask;
assign commit_data_r = commit_tmp_if.data.data;
assign commit_tmask_w = commit_tmp_if.data.tmask;
assign commit_data_w = commit_tmp_if.data.data;
end
assign commit_out_if[i].valid = commit_tmp_if.valid;
assign commit_out_if[i].data = {
commit_tmp_if.data.uuid,
commit_tmp_if.data.wid,
commit_tmask_r,
commit_tmask_w,
commit_tmp_if.data.PC,
commit_tmp_if.data.wb,
commit_tmp_if.data.rd,
commit_data_r,
commit_data_w,
1'b0, // PID
commit_tmp_if.data.sop,
commit_tmp_if.data.eop

22
hw/rtl/core/VX_lsu_slice.sv
View file

@ -158,30 +158,30 @@ module VX_lsu_slice import VX_gpu_pkg::*; #(
// byte enable formatting
for (genvar i = 0; i < NUM_LANES; ++i) begin
reg [LSU_WORD_SIZE-1:0] mem_req_byteen_r;
reg [LSU_WORD_SIZE-1:0] mem_req_byteen_w;
always @(*) begin
mem_req_byteen_r = '0;
mem_req_byteen_w = '0;
case (`INST_LSU_WSIZE(execute_if.data.op_type))
0: begin // 8-bit
mem_req_byteen_r[req_align[i]] = 1'b1;
mem_req_byteen_w[req_align[i]] = 1'b1;
end
1: begin // 16 bit
mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:1], 1'b0}] = 1'b1;
mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:1], 1'b1}] = 1'b1;
mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:1], 1'b0}] = 1'b1;
mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:1], 1'b1}] = 1'b1;
end
`ifdef XLEN_64
2: begin // 32 bit
mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:2], 2'b00}] = 1'b1;
mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:2], 2'b01}] = 1'b1;
mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:2], 2'b10}] = 1'b1;
mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:2], 2'b11}] = 1'b1;
mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:2], 2'b00}] = 1'b1;
mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:2], 2'b01}] = 1'b1;
mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:2], 2'b10}] = 1'b1;
mem_req_byteen_w[{req_align[i][REQ_ASHIFT-1:2], 2'b11}] = 1'b1;
end
`endif
// 3: 64 bit
default : mem_req_byteen_r = {LSU_WORD_SIZE{1'b1}};
default : mem_req_byteen_w = {LSU_WORD_SIZE{1'b1}};
endcase
end
assign mem_req_byteen[i] = mem_req_byteen_r;
assign mem_req_byteen[i] = mem_req_byteen_w;
end
// memory misalignment not supported!

10
hw/rtl/fpu/VX_fpu_dsp.sv
View file

@ -315,15 +315,15 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
`ifdef FPU_RV64F
reg [`XLEN-1:0] result_r;
reg [`XLEN-1:0] result_w;
always @(*) begin
case (op_ret_int_out)
2'b11: result_r = `XLEN'($signed(result_s[i]));
2'b01: result_r = {32'h00000000, result_s[i]};
default: result_r = {32'hffffffff, result_s[i]};
2'b11: result_w = `XLEN'($signed(result_s[i]));
2'b01: result_w = {32'h00000000, result_s[i]};
default: result_w = {32'hffffffff, result_s[i]};
endcase
end
assign result[i] = result_r;
assign result[i] = result_w;
`else
assign result[i] = result_s[i];
`endif

12
hw/rtl/libs/VX_onehot_encoder.sv
View file

@ -87,29 +87,29 @@ module VX_onehot_encoder #(
end else begin
reg [LN-1:0] index_r;
reg [LN-1:0] index_w;
if (REVERSE != 0) begin
always @(*) begin
index_r = 'x;
index_w = 'x;
for (integer i = N-1; i >= 0; --i) begin
if (data_in[i]) begin
index_r = LN'(N-1-i);
index_w = LN'(N-1-i);
end
end
end
end else begin
always @(*) begin
index_r = 'x;
index_w = 'x;
for (integer i = 0; i < N; ++i) begin
if (data_in[i]) begin
index_r = LN'(i);
index_w = LN'(i);
end
end
end
end
assign data_out = index_r;
assign data_out = index_w;
assign valid_out = (| data_in);
end

110
hw/rtl/libs/VX_onehot_mux.sv
View file

@ -31,86 +31,86 @@ module VX_onehot_mux #(
`UNUSED_VAR (sel_in)
assign data_out = sel_in[0] ? data_in[0] : data_in[1];
end else if (LUT_OPT && N == 3) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
3'b001: data_out_r = data_in[0];
3'b010: data_out_r = data_in[1];
3'b100: data_out_r = data_in[2];
default: data_out_r = 'x;
3'b001: data_out_w = data_in[0];
3'b010: data_out_w = data_in[1];
3'b100: data_out_w = data_in[2];
default: data_out_w = 'x;
endcase
end
assign data_out = data_out_r;
assign data_out = data_out_w;
end else if (LUT_OPT && N == 4) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
4'b0001: data_out_r = data_in[0];
4'b0010: data_out_r = data_in[1];
4'b0100: data_out_r = data_in[2];
4'b1000: data_out_r = data_in[3];
default: data_out_r = 'x;
4'b0001: data_out_w = data_in[0];
4'b0010: data_out_w = data_in[1];
4'b0100: data_out_w = data_in[2];
4'b1000: data_out_w = data_in[3];
default: data_out_w = 'x;
endcase
end
assign data_out = data_out_r;
assign data_out = data_out_w;
end else if (LUT_OPT && N == 5) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
5'b00001: data_out_r = data_in[0];
5'b00010: data_out_r = data_in[1];
5'b00100: data_out_r = data_in[2];
5'b01000: data_out_r = data_in[3];
5'b10000: data_out_r = data_in[4];
default: data_out_r = 'x;
5'b00001: data_out_w = data_in[0];
5'b00010: data_out_w = data_in[1];
5'b00100: data_out_w = data_in[2];
5'b01000: data_out_w = data_in[3];
5'b10000: data_out_w = data_in[4];
default: data_out_w = 'x;
endcase
end
assign data_out = data_out_r;
assign data_out = data_out_w;
end else if (LUT_OPT && N == 6) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
6'b000001: data_out_r = data_in[0];
6'b000010: data_out_r = data_in[1];
6'b000100: data_out_r = data_in[2];
6'b001000: data_out_r = data_in[3];
6'b010000: data_out_r = data_in[4];
6'b100000: data_out_r = data_in[5];
default: data_out_r = 'x;
6'b000001: data_out_w = data_in[0];
6'b000010: data_out_w = data_in[1];
6'b000100: data_out_w = data_in[2];
6'b001000: data_out_w = data_in[3];
6'b010000: data_out_w = data_in[4];
6'b100000: data_out_w = data_in[5];
default: data_out_w = 'x;
endcase
end
assign data_out = data_out_r;
assign data_out = data_out_w;
end else if (LUT_OPT && N == 7) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
7'b0000001: data_out_r = data_in[0];
7'b0000010: data_out_r = data_in[1];
7'b0000100: data_out_r = data_in[2];
7'b0001000: data_out_r = data_in[3];
7'b0010000: data_out_r = data_in[4];
7'b0100000: data_out_r = data_in[5];
7'b1000000: data_out_r = data_in[6];
default: data_out_r = 'x;
7'b0000001: data_out_w = data_in[0];
7'b0000010: data_out_w = data_in[1];
7'b0000100: data_out_w = data_in[2];
7'b0001000: data_out_w = data_in[3];
7'b0010000: data_out_w = data_in[4];
7'b0100000: data_out_w = data_in[5];
7'b1000000: data_out_w = data_in[6];
default: data_out_w = 'x;
endcase
end
assign data_out = data_out_r;
assign data_out = data_out_w;
end else if (LUT_OPT && N == 8) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] data_out_w;
always @(*) begin
case (sel_in)
8'b00000001: data_out_r = data_in[0];
8'b00000010: data_out_r = data_in[1];
8'b00000100: data_out_r = data_in[2];
8'b00001000: data_out_r = data_in[3];
8'b00010000: data_out_r = data_in[4];
8'b00100000: data_out_r = data_in[5];
8'b01000000: data_out_r = data_in[6];
8'b10000000: data_out_r = data_in[7];
default: data_out_r = 'x;
8'b00000001: data_out_w = data_in[0];
8'b00000010: data_out_w = data_in[1];
8'b00000100: data_out_w = data_in[2];
8'b00001000: data_out_w = data_in[3];
8'b00010000: data_out_w = data_in[4];
8'b00100000: data_out_w = data_in[5];
8'b01000000: data_out_w = data_in[6];
8'b10000000: data_out_w = data_in[7];
default: data_out_w = 'x;
endcase
end
assign data_out = data_out_r;
assign data_out = data_out_w;
end else if (MODEL == 1) begin
wire [N-1:0][DATAW-1:0] mask;
for (genvar i = 0; i < N; ++i) begin
@ -134,16 +134,16 @@ module VX_onehot_mux #(
`UNUSED_PIN (valid_out)
);
end else if (MODEL == 3) begin
reg [DATAW-1:0] data_out_r;
reg [DATAW-1:0] data_out_w;
always @(*) begin
data_out_r = 'x;
data_out_w = 'x;
for (integer i = 0; i < N; ++i) begin
if (sel_in[i]) begin
data_out_r = data_in[i];
data_out_w = data_in[i];
end
end
end
assign data_out = data_out_r;
assign data_out = data_out_w;
end
endmodule

60
hw/rtl/libs/VX_popcount.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -21,21 +21,21 @@ module VX_popcount63(
reg [2:0] sum;
always @(*) begin
case (data_in)
6'd0: sum=3'd0; 6'd1: sum=3'd1; 6'd2: sum=3'd1; 6'd3: sum=3'd2;
6'd0: sum=3'd0; 6'd1: sum=3'd1; 6'd2: sum=3'd1; 6'd3: sum=3'd2;
6'd4: sum=3'd1; 6'd5: sum=3'd2; 6'd6: sum=3'd2; 6'd7: sum=3'd3;
6'd8: sum=3'd1; 6'd9: sum=3'd2; 6'd10: sum=3'd2; 6'd11: sum=3'd3;
6'd8: sum=3'd1; 6'd9: sum=3'd2; 6'd10: sum=3'd2; 6'd11: sum=3'd3;
6'd12: sum=3'd2; 6'd13: sum=3'd3; 6'd14: sum=3'd3; 6'd15: sum=3'd4;
6'd16: sum=3'd1; 6'd17: sum=3'd2; 6'd18: sum=3'd2; 6'd19: sum=3'd3;
6'd16: sum=3'd1; 6'd17: sum=3'd2; 6'd18: sum=3'd2; 6'd19: sum=3'd3;
6'd20: sum=3'd2; 6'd21: sum=3'd3; 6'd22: sum=3'd3; 6'd23: sum=3'd4;
6'd24: sum=3'd2; 6'd25: sum=3'd3; 6'd26: sum=3'd3; 6'd27: sum=3'd4;
6'd24: sum=3'd2; 6'd25: sum=3'd3; 6'd26: sum=3'd3; 6'd27: sum=3'd4;
6'd28: sum=3'd3; 6'd29: sum=3'd4; 6'd30: sum=3'd4; 6'd31: sum=3'd5;
6'd32: sum=3'd1; 6'd33: sum=3'd2; 6'd34: sum=3'd2; 6'd35: sum=3'd3;
6'd32: sum=3'd1; 6'd33: sum=3'd2; 6'd34: sum=3'd2; 6'd35: sum=3'd3;
6'd36: sum=3'd2; 6'd37: sum=3'd3; 6'd38: sum=3'd3; 6'd39: sum=3'd4;
6'd40: sum=3'd2; 6'd41: sum=3'd3; 6'd42: sum=3'd3; 6'd43: sum=3'd4;
6'd40: sum=3'd2; 6'd41: sum=3'd3; 6'd42: sum=3'd3; 6'd43: sum=3'd4;
6'd44: sum=3'd3; 6'd45: sum=3'd4; 6'd46: sum=3'd4; 6'd47: sum=3'd5;
6'd48: sum=3'd2; 6'd49: sum=3'd3; 6'd50: sum=3'd3; 6'd51: sum=3'd4;
6'd48: sum=3'd2; 6'd49: sum=3'd3; 6'd50: sum=3'd3; 6'd51: sum=3'd4;
6'd52: sum=3'd3; 6'd53: sum=3'd4; 6'd54: sum=3'd4; 6'd55: sum=3'd5;
6'd56: sum=3'd3; 6'd57: sum=3'd4; 6'd58: sum=3'd4; 6'd59: sum=3'd5;
6'd56: sum=3'd3; 6'd57: sum=3'd4; 6'd58: sum=3'd4; 6'd59: sum=3'd5;
6'd60: sum=3'd4; 6'd61: sum=3'd5; 6'd62: sum=3'd5; 6'd63: sum=3'd6;
endcase
end
@ -49,7 +49,7 @@ module VX_popcount32(
reg [1:0] sum;
always @(*) begin
case (data_in)
3'd0: sum=2'd0; 3'd1: sum=2'd1; 3'd2: sum=2'd1; 3'd3: sum=2'd2;
3'd0: sum=2'd0; 3'd1: sum=2'd1; 3'd2: sum=2'd1; 3'd3: sum=2'd2;
3'd4: sum=2'd1; 3'd5: sum=2'd2; 3'd6: sum=2'd2; 3'd7: sum=2'd3;
endcase
end
@ -88,12 +88,12 @@ endmodule
module VX_popcount #(
parameter MODEL = 1,
parameter N = 1,
parameter M = `CLOG2(N+1)
parameter M = `CLOG2(N+1)
) (
input wire [N-1:0] data_in,
output wire [M-1:0] data_out
);
`UNUSED_PARAM (MODEL)
`UNUSED_PARAM (MODEL)
`ifndef SYNTHESIS
assign data_out = $countones(data_in);
@ -113,10 +113,10 @@ module VX_popcount #(
t_in[N-1:0] = data_in;
end
VX_popcount32 pc32(t_in, t_out);
assign data_out = t_out[M-1:0];
assign data_out = t_out[M-1:0];
end else if (N <= 6) begin
reg [5:0] t_in;
wire [2:0] t_out;
always @(*) begin
@ -125,9 +125,9 @@ module VX_popcount #(
end
VX_popcount63 pc63(t_in, t_out);
assign data_out = t_out[M-1:0];
end else if (N <= 9) begin
reg [8:0] t_in;
wire [4:0] t1_out;
wire [3:0] t2_out;
@ -141,7 +141,7 @@ module VX_popcount #(
assign data_out = t2_out[M-1:0];
end else if (N <= 12) begin
reg [11:0] t_in;
wire [5:0] t1_out;
wire [3:0] t2_out;
@ -155,7 +155,7 @@ module VX_popcount #(
assign data_out = t2_out[M-1:0];
end else if (N <= 18) begin
reg [17:0] t_in;
wire [8:0] t1_out;
wire [5:0] t2_out;
@ -177,17 +177,17 @@ module VX_popcount #(
localparam LOGPN = `CLOG2(PN);
`IGNORE_UNOPTFLAT_BEGIN
wire [M-1:0] tmp [LOGPN-1:0][PN-1:0];
wire [M-1:0] tmp [LOGPN-1:0][PN-1:0];
`IGNORE_UNOPTFLAT_END
for (genvar j = 0; j < LOGPN; ++j) begin
localparam D = j + 1;
localparam Q = (D < LOGPN) ? (D + 1) : M;
for (genvar i = 0; i < (1 << (LOGPN-j-1)); ++i) begin
for (genvar i = 0; i < (1 << (LOGPN-j-1)); ++i) begin
localparam l = i * 2;
localparam r = i * 2 + 1;
wire [Q-1:0] res;
if (j == 0) begin
wire [Q-1:0] res;
if (j == 0) begin
if (r < N) begin
assign res = data_in[l] + data_in[r];
end else if (l < N) begin
@ -203,20 +203,20 @@ module VX_popcount #(
end
assign data_out = tmp[LOGPN-1][0];
end else begin
reg [M-1:0] cnt_r;
reg [M-1:0] cnt_w;
always @(*) begin
cnt_r = '0;
cnt_w = '0;
for (integer i = 0; i < N; ++i) begin
cnt_r = cnt_r + M'(data_in[i]);
cnt_w = cnt_w + M'(data_in[i]);
end
end
assign data_out = cnt_r;
assign data_out = cnt_w;
end
`endif

16
hw/rtl/libs/VX_priority_encoder.sv
View file

@ -106,22 +106,22 @@ module VX_priority_encoder #(
end else begin
reg [LN-1:0] index_r;
reg [N-1:0] onehot_r;
reg [LN-1:0] index_w;
reg [N-1:0] onehot_w;
always @(*) begin
index_r = 'x;
onehot_r = 'x;
index_w = 'x;
onehot_w = 'x;
for (integer i = N-1; i >= 0; --i) begin
if (reversed[i]) begin
index_r = LN'(i);
onehot_r = N'(1) << i;
index_w = LN'(i);
onehot_w = N'(1) << i;
end
end
end
assign index_out = index_r;
assign onehot_out = onehot_r;
assign index_out = index_w;
assign onehot_out = onehot_w;
assign valid_out = (| reversed);
end

154
hw/rtl/libs/VX_rr_arbiter.sv
View file

@ -40,16 +40,16 @@ module VX_rr_arbiter #(
end else if (LUT_OPT && NUM_REQS == 2) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [LOG_NUM_REQS-1:0] state;
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
3'b0_01,
3'b1_?1: begin grant_index_r = LOG_NUM_REQS'(0); end
3'b1_?1: begin grant_index_w = LOG_NUM_REQS'(0); end
3'b0_1?,
3'b1_10: begin grant_index_r = LOG_NUM_REQS'(1); end
default: begin grant_index_r = 'x; end
3'b1_10: begin grant_index_w = LOG_NUM_REQS'(1); end
default: begin grant_index_w = 'x; end
endcase
end
@ -57,31 +57,31 @@ module VX_rr_arbiter #(
if (reset) begin
state <= '0;
end else if (grant_ready) begin
state <= grant_index_r;
state <= grant_index_w;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_index = grant_index_w;
assign grant_onehot = NUM_REQS'(1) << grant_index_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 3) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [LOG_NUM_REQS-1:0] state;
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
5'b00_001,
5'b01_0?1,
5'b10_??1: begin grant_index_r = LOG_NUM_REQS'(0); end
5'b10_??1: begin grant_index_w = LOG_NUM_REQS'(0); end
5'b00_?1?,
5'b01_010,
5'b10_?10: begin grant_index_r = LOG_NUM_REQS'(1); end
5'b10_?10: begin grant_index_w = LOG_NUM_REQS'(1); end
5'b00_10?,
5'b01_1??,
5'b10_100: begin grant_index_r = LOG_NUM_REQS'(2); end
default: begin grant_index_r = 'x; end
5'b10_100: begin grant_index_w = LOG_NUM_REQS'(2); end
default: begin grant_index_w = 'x; end
endcase
end
@ -89,38 +89,38 @@ module VX_rr_arbiter #(
if (reset) begin
state <= '0;
end else if (grant_ready) begin
state <= grant_index_r;
state <= grant_index_w;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_index = grant_index_w;
assign grant_onehot = NUM_REQS'(1) << grant_index_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 4) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [LOG_NUM_REQS-1:0] state;
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
6'b00_0001,
6'b01_00?1,
6'b10_0??1,
6'b11_???1: begin grant_index_r = LOG_NUM_REQS'(0); end
6'b11_???1: begin grant_index_w = LOG_NUM_REQS'(0); end
6'b00_??1?,
6'b01_0010,
6'b10_0?10,
6'b11_??10: begin grant_index_r = LOG_NUM_REQS'(1); end
6'b11_??10: begin grant_index_w = LOG_NUM_REQS'(1); end
6'b00_?10?,
6'b01_?1??,
6'b10_0100,
6'b11_?100: begin grant_index_r = LOG_NUM_REQS'(2); end
6'b11_?100: begin grant_index_w = LOG_NUM_REQS'(2); end
6'b00_100?,
6'b01_10??,
6'b10_1???,
6'b11_1000: begin grant_index_r = LOG_NUM_REQS'(3); end
default: begin grant_index_r = 'x; end
6'b11_1000: begin grant_index_w = LOG_NUM_REQS'(3); end
default: begin grant_index_w = 'x; end
endcase
end
@ -128,18 +128,18 @@ module VX_rr_arbiter #(
if (reset) begin
state <= '0;
end else if (grant_ready) begin
state <= grant_index_r;
state <= grant_index_w;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_index = grant_index_w;
assign grant_onehot = NUM_REQS'(1) << grant_index_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 5) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [LOG_NUM_REQS-1:0] state;
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
@ -147,28 +147,28 @@ module VX_rr_arbiter #(
8'b001_000?1,
8'b010_00??1,
8'b011_0???1,
8'b100_????1: begin grant_index_r = LOG_NUM_REQS'(0); end
8'b100_????1: begin grant_index_w = LOG_NUM_REQS'(0); end
8'b000_???1?,
8'b001_00010,
8'b010_00?10,
8'b011_0??10,
8'b100_???10: begin grant_index_r = LOG_NUM_REQS'(1); end
8'b100_???10: begin grant_index_w = LOG_NUM_REQS'(1); end
8'b000_??10?,
8'b001_??1??,
8'b010_00100,
8'b011_0?100,
8'b100_??100: begin grant_index_r = LOG_NUM_REQS'(2); end
8'b100_??100: begin grant_index_w = LOG_NUM_REQS'(2); end
8'b000_?100?,
8'b001_?10??,
8'b010_?1???,
8'b011_01000,
8'b100_?1000: begin grant_index_r = LOG_NUM_REQS'(3); end
8'b100_?1000: begin grant_index_w = LOG_NUM_REQS'(3); end
8'b000_1000?,
8'b001_100??,
8'b010_10???,
8'b011_1????,
8'b100_10000: begin grant_index_r = LOG_NUM_REQS'(4); end
default: begin grant_index_r = 'x; end
8'b100_10000: begin grant_index_w = LOG_NUM_REQS'(4); end
default: begin grant_index_w = 'x; end
endcase
end
@ -176,18 +176,18 @@ module VX_rr_arbiter #(
if (reset) begin
state <= '0;
end else if (grant_ready) begin
state <= grant_index_r;
state <= grant_index_w;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_index = grant_index_w;
assign grant_onehot = NUM_REQS'(1) << grant_index_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 6) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [LOG_NUM_REQS-1:0] state;
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
@ -196,38 +196,38 @@ module VX_rr_arbiter #(
9'b010_000??1,
9'b011_00???1,
9'b100_0????1,
9'b101_?????1: begin grant_index_r = LOG_NUM_REQS'(0); end
9'b101_?????1: begin grant_index_w = LOG_NUM_REQS'(0); end
9'b000_????1?,
9'b001_000010,
9'b010_000?10,
9'b011_00??10,
9'b100_0???10,
9'b101_????10: begin grant_index_r = LOG_NUM_REQS'(1); end
9'b101_????10: begin grant_index_w = LOG_NUM_REQS'(1); end
9'b000_???10?,
9'b001_???1??,
9'b010_000100,
9'b011_00?100,
9'b100_0??100,
9'b101_???100: begin grant_index_r = LOG_NUM_REQS'(2); end
9'b101_???100: begin grant_index_w = LOG_NUM_REQS'(2); end
9'b000_??100?,
9'b001_??10??,
9'b010_??1???,
9'b011_001000,
9'b100_0?1000,
9'b101_??1000: begin grant_index_r = LOG_NUM_REQS'(3); end
9'b101_??1000: begin grant_index_w = LOG_NUM_REQS'(3); end
9'b000_?1000?,
9'b001_?100??,
9'b010_?10???,
9'b011_?1????,
9'b100_010000,
9'b101_?10000: begin grant_index_r = LOG_NUM_REQS'(4); end
9'b101_?10000: begin grant_index_w = LOG_NUM_REQS'(4); end
9'b000_10000?,
9'b001_1000??,
9'b010_100???,
9'b011_10????,
9'b100_1?????,
9'b101_100000: begin grant_index_r = LOG_NUM_REQS'(5); end
default: begin grant_index_r = 'x; end
9'b101_100000: begin grant_index_w = LOG_NUM_REQS'(5); end
default: begin grant_index_w = 'x; end
endcase
end
@ -235,18 +235,18 @@ module VX_rr_arbiter #(
if (reset) begin
state <= '0;
end else if (grant_ready) begin
state <= grant_index_r;
state <= grant_index_w;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_index = grant_index_w;
assign grant_onehot = NUM_REQS'(1) << grant_index_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 7) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [LOG_NUM_REQS-1:0] state;
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
@ -256,50 +256,50 @@ module VX_rr_arbiter #(
10'b011_000???1,
10'b100_000???1,
10'b101_00????1,
10'b110_??????1: begin grant_index_r = LOG_NUM_REQS'(0); end
10'b110_??????1: begin grant_index_w = LOG_NUM_REQS'(0); end
10'b000_?????1?,
10'b001_0000010,
10'b010_0000?10,
10'b011_000??10,
10'b100_00???10,
10'b101_0????10,
10'b110_?????10: begin grant_index_r = LOG_NUM_REQS'(1); end
10'b110_?????10: begin grant_index_w = LOG_NUM_REQS'(1); end
10'b000_????10?,
10'b001_????1??,
10'b010_0000100,
10'b011_000?100,
10'b100_00??100,
10'b101_0???100,
10'b110_????100: begin grant_index_r = LOG_NUM_REQS'(2); end
10'b110_????100: begin grant_index_w = LOG_NUM_REQS'(2); end
10'b000_???100?,
10'b001_???10??,
10'b010_???1???,
10'b011_0001000,
10'b100_00?1000,
10'b101_0??1000,
10'b110_???1000: begin grant_index_r = LOG_NUM_REQS'(3); end
10'b110_???1000: begin grant_index_w = LOG_NUM_REQS'(3); end
10'b000_??1000?,
10'b001_??100??,
10'b010_??10???,
10'b011_??1????,
10'b100_0010000,
10'b101_0?10000,
10'b110_??10000: begin grant_index_r = LOG_NUM_REQS'(4); end
10'b110_??10000: begin grant_index_w = LOG_NUM_REQS'(4); end
10'b000_?10000?,
10'b001_?1000??,
10'b010_?100???,
10'b011_?10????,
10'b100_?1?????,
10'b101_0100000,
10'b110_?100000: begin grant_index_r = LOG_NUM_REQS'(5); end
10'b110_?100000: begin grant_index_w = LOG_NUM_REQS'(5); end
10'b000_100000?,
10'b001_10000??,
10'b010_1000???,
10'b011_100????,
10'b100_10?????,
10'b101_1??????,
10'b110_1000000: begin grant_index_r = LOG_NUM_REQS'(6); end
default: begin grant_index_r = 'x; end
10'b110_1000000: begin grant_index_w = LOG_NUM_REQS'(6); end
default: begin grant_index_w = 'x; end
endcase
end
@ -307,18 +307,18 @@ module VX_rr_arbiter #(
if (reset) begin
state <= '0;
end else if (grant_ready) begin
state <= grant_index_r;
state <= grant_index_w;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_index = grant_index_w;
assign grant_onehot = NUM_REQS'(1) << grant_index_w;
assign grant_valid = (| requests);
end else if (LUT_OPT && NUM_REQS == 8) begin
reg [LOG_NUM_REQS-1:0] grant_index_r;
reg [LOG_NUM_REQS-1:0] state;
reg [LOG_NUM_REQS-1:0] grant_index_w;
reg [LOG_NUM_REQS-1:0] state;
always @(*) begin
casez ({state, requests})
@ -329,7 +329,7 @@ module VX_rr_arbiter #(
11'b100_000????1,
11'b101_00?????1,
11'b110_0??????1,
11'b111_???????1: begin grant_index_r = LOG_NUM_REQS'(0); end
11'b111_???????1: begin grant_index_w = LOG_NUM_REQS'(0); end
11'b000_??????1?,
11'b001_00000010,
11'b010_00000?10,
@ -337,7 +337,7 @@ module VX_rr_arbiter #(
11'b100_000???10,
11'b101_00????10,
11'b110_0?????10,
11'b111_??????10: begin grant_index_r = LOG_NUM_REQS'(1); end
11'b111_??????10: begin grant_index_w = LOG_NUM_REQS'(1); end
11'b000_?????10?,
11'b001_?????1??,
11'b010_00000100,
@ -345,7 +345,7 @@ module VX_rr_arbiter #(
11'b100_000??100,
11'b101_00???100,
11'b110_0????100,
11'b111_?????100: begin grant_index_r = LOG_NUM_REQS'(2); end
11'b111_?????100: begin grant_index_w = LOG_NUM_REQS'(2); end
11'b000_????100?,
11'b001_????10??,
11'b010_????1???,
@ -353,7 +353,7 @@ module VX_rr_arbiter #(
11'b100_000?1000,
11'b101_00??1000,
11'b110_0???1000,
11'b111_????1000: begin grant_index_r = LOG_NUM_REQS'(3); end
11'b111_????1000: begin grant_index_w = LOG_NUM_REQS'(3); end
11'b000_???1000?,
11'b001_???100??,
11'b010_???10???,
@ -361,7 +361,7 @@ module VX_rr_arbiter #(
11'b100_00010000,
11'b101_00?10000,
11'b110_0??10000,
11'b111_???10000: begin grant_index_r = LOG_NUM_REQS'(4); end
11'b111_???10000: begin grant_index_w = LOG_NUM_REQS'(4); end
11'b000_??10000?,
11'b001_??1000??,
11'b010_??100???,
@ -369,7 +369,7 @@ module VX_rr_arbiter #(
11'b100_??1?????,
11'b101_00100000,
11'b110_0?100000,
11'b111_??100000: begin grant_index_r = LOG_NUM_REQS'(5); end
11'b111_??100000: begin grant_index_w = LOG_NUM_REQS'(5); end
11'b000_?100000?,
11'b001_?10000??,
11'b010_?1000???,
@ -377,7 +377,7 @@ module VX_rr_arbiter #(
11'b100_?10?????,
11'b101_?1??????,
11'b110_01000000,
11'b111_?1000000: begin grant_index_r = LOG_NUM_REQS'(6); end
11'b111_?1000000: begin grant_index_w = LOG_NUM_REQS'(6); end
11'b000_1000000?,
11'b001_100000??,
11'b010_10000???,
@ -385,8 +385,8 @@ module VX_rr_arbiter #(
11'b100_100?????,
11'b101_10??????,
11'b110_1???????,
11'b111_10000000: begin grant_index_r = LOG_NUM_REQS'(7); end
default: begin grant_index_r = 'x; end
11'b111_10000000: begin grant_index_w = LOG_NUM_REQS'(7); end
default: begin grant_index_w = 'x; end
endcase
end
@ -394,12 +394,12 @@ module VX_rr_arbiter #(
if (reset) begin
state <= '0;
end else if (grant_ready) begin
state <= grant_index_r;
state <= grant_index_w;
end
end
assign grant_index = grant_index_r;
assign grant_onehot = NUM_REQS'(1) << grant_index_r;
assign grant_index = grant_index_w;
assign grant_onehot = NUM_REQS'(1) << grant_index_w;
assign grant_valid = (| requests);
end else if (MODEL == 1) begin