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minor update

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This commit is contained in:
Blaise Tine 2021-07-31 03:30:35 -07:00
parent 79fd92a1b4
commit 3b7da61245
5 changed files with 12 additions and 24 deletions
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4
hw/rtl/VX_alu_unit.v
View file

@ -154,7 +154,7 @@ module VX_alu_unit #(
assign mul_ready_out = ~stall_out;
assign result_valid = mul_valid_out | (alu_req_if.valid && ~is_mul_op);
assign result_valid = mul_valid_out || (alu_req_if.valid && ~is_mul_op);
assign result_wid = mul_valid_out ? mul_wid : alu_req_if.wid;
assign result_tmask = mul_valid_out ? mul_tmask : alu_req_if.tmask;
assign result_PC = mul_valid_out ? mul_PC : alu_req_if.PC;
@ -165,7 +165,7 @@ module VX_alu_unit #(
`else
assign stall_in = 0;
assign stall_in = stall_out;
assign result_valid = alu_req_if.valid;
assign result_wid = alu_req_if.wid;

8
hw/rtl/VX_gpu_unit.v
View file

@ -78,7 +78,7 @@ module VX_gpu_unit #(
wire stall = ~gpu_commit_if.ready && gpu_commit_if.valid;
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + `GPU_TMC_SIZE + `GPU_WSPAWN_SIZE + `GPU_SPLIT_SIZE + `GPU_BARRIER_SIZE),
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + `GPU_TMC_BITS + `GPU_WSPAWN_BITS + `GPU_SPLIT_BITS + `GPU_BARRIER_BITS),
.RESETW (1)
) pipe_reg (
.clk (clk),
@ -96,12 +96,6 @@ module VX_gpu_unit #(
// can accept new request?
assign gpu_req_if.ready = ~stall;
`SCOPE_ASSIGN (gpu_req_fire, gpu_req_if.valid && gpu_req_if.ready);
`SCOPE_ASSIGN (gpu_req_wid, gpu_req_if.wid);
`SCOPE_ASSIGN (gpu_req_tmask, gpu_req_if.tmask);
`SCOPE_ASSIGN (gpu_req_op_type, gpu_req_if.op_type);
`SCOPE_ASSIGN (gpu_req_rs1, gpu_req_if.rs1_data[0]);
`SCOPE_ASSIGN (gpu_req_rs2, gpu_req_if.rs2_data);
`SCOPE_ASSIGN (gpu_rsp_valid, warp_ctl_if.valid);
`SCOPE_ASSIGN (gpu_rsp_wid, warp_ctl_if.wid);
`SCOPE_ASSIGN (gpu_rsp_tmc, warp_ctl_if.tmc);

8
hw/rtl/VX_types.vh
View file

@ -28,7 +28,7 @@ typedef struct packed {
logic [`NUM_THREADS-1:0] tmask;
} gpu_tmc_t;
`define GPU_TMC_SIZE (1+`NUM_THREADS)
`define GPU_TMC_BITS (1+`NUM_THREADS)
typedef struct packed {
logic valid;
@ -36,7 +36,7 @@ typedef struct packed {
logic [31:0] pc;
} gpu_wspawn_t;
`define GPU_WSPAWN_SIZE (1+`NUM_WARPS+32)
`define GPU_WSPAWN_BITS (1+`NUM_WARPS+32)
typedef struct packed {
logic valid;
@ -46,7 +46,7 @@ typedef struct packed {
logic [31:0] pc;
} gpu_split_t;
`define GPU_SPLIT_SIZE (1+1+`NUM_THREADS+`NUM_THREADS+32)
`define GPU_SPLIT_BITS (1+1+`NUM_THREADS+`NUM_THREADS+32)
typedef struct packed {
logic valid;
@ -54,6 +54,6 @@ typedef struct packed {
logic [`NW_BITS-1:0] size_m1;
} gpu_barrier_t;
`define GPU_BARRIER_SIZE (1+`NB_BITS+`NW_BITS)
`define GPU_BARRIER_BITS (1+`NB_BITS+`NW_BITS)
`endif

14
hw/scripts/scope.json
View file

@ -146,18 +146,12 @@
"wsched_warp_pc": "32"
},
"afu/vortex/cluster/core/pipeline/execute/gpu_unit": {
"?gpu_req_fire": 1,
"gpu_req_wid": "`NW_BITS",
"gpu_req_tmask": "`NUM_THREADS",
"gpu_req_op_type": "`GPU_BITS",
"gpu_req_rs1": "32",
"gpu_req_rs2": "32",
"?gpu_rsp_valid": 1,
"gpu_rsp_wid": "`NW_BITS",
"gpu_rsp_tmc": "`GPU_TMC_SIZE",
"gpu_rsp_wspawn": "`GPU_WSPAWN_SIZE",
"gpu_rsp_split": "`GPU_SPLIT_SIZE",
"gpu_rsp_barrier": "`GPU_BARRIER_SIZE"
"gpu_rsp_tmc": "`GPU_TMC_BITS",
"gpu_rsp_wspawn": "`GPU_WSPAWN_BITS",
"gpu_rsp_split": "`GPU_SPLIT_BITS",
"gpu_rsp_barrier": "`GPU_BARRIER_BITS"
},
"afu/vortex/cluster/core/pipeline/execute/lsu_unit": {
"?dcache_req_fire":"`NUM_THREADS",

2
hw/scripts/scope.py
View file

@ -240,7 +240,7 @@ def expand_text(text, params):
iter = 0
while True:
if iter > 99:
if iter > 65536:
raise Exception("Macro recursion!")
has_func = False
while True: