Add synthesized configuration statistics

This commit is contained in:
wgulian3 2020-04-05 23:33:52 -04:00
parent 829042f472
commit 3bcb7b0e83

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results/synth_data.csv Normal file
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build_name,Fmax_Slow_900mV_100C,m20k,logic_utilization,total_registers,total_power,static_power
1cl-2c-8w-4t-8Kl2-4Kd-1Ki,154.01,2.3590121636564687,16.956694756554306,99408.0,3.64785,1.88908
1cl-2c-8w-8t-16Kl2-8Kd-1Ki,137.78,2.3590121636564687,23.021769662921347,134668.0,4.29923,1.95073
1cl-2c-8w-8t-8Kl2-4Kd-1Ki,131.22,2.3590121636564687,23.179541198501873,134129.0,4.31822,1.94177
1cl-4c-16w-8t-16Kl2-8Kd-1Ki,106.37,4.128271286398821,62.116573033707866,356954.0,7.92994,2.28735
1cl-4c-8w-8t-16Kl2-4Kd-1Ki,118.51,4.128271286398821,43.340823970037455,251029.0,6.34737,2.09685
1cl-4c-8w-8t-16Kl2-8Kd-1Ki,123.49,4.128271286398821,43.34199438202247,250895.0,6.34987,2.11429
2cl-4c-8w-4t-8Kl2-4Kd-1Ki,132.75,6.1924069295982305,56.91058052434457,322475.0,7.63097,2.27641
1 build_name Fmax_Slow_900mV_100C m20k logic_utilization total_registers total_power static_power
2 1cl-2c-8w-4t-8Kl2-4Kd-1Ki 154.01 2.3590121636564687 16.956694756554306 99408.0 3.64785 1.88908
3 1cl-2c-8w-8t-16Kl2-8Kd-1Ki 137.78 2.3590121636564687 23.021769662921347 134668.0 4.29923 1.95073
4 1cl-2c-8w-8t-8Kl2-4Kd-1Ki 131.22 2.3590121636564687 23.179541198501873 134129.0 4.31822 1.94177
5 1cl-4c-16w-8t-16Kl2-8Kd-1Ki 106.37 4.128271286398821 62.116573033707866 356954.0 7.92994 2.28735
6 1cl-4c-8w-8t-16Kl2-4Kd-1Ki 118.51 4.128271286398821 43.340823970037455 251029.0 6.34737 2.09685
7 1cl-4c-8w-8t-16Kl2-8Kd-1Ki 123.49 4.128271286398821 43.34199438202247 250895.0 6.34987 2.11429
8 2cl-4c-8w-4t-8Kl2-4Kd-1Ki 132.75 6.1924069295982305 56.91058052434457 322475.0 7.63097 2.27641