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Passes all tests except MEM and lui?

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This commit is contained in:
felsabbagh3 2019-02-10 05:46:18 -05:00
parent 0c3a73a896
commit 3c74a13009
169 changed files with 26599 additions and 443 deletions
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19
src/core.cpp
View file

@ -116,6 +116,12 @@ Warp::Warp(Core *c, Word id) :
shadowTmask.push_back(true);
}
Word csrNum(0);
for (Word i = 0; i < (1<<12); i++)
{
csr.push_back(Reg<uint16_t>(id, regNum++));
}
/* Set initial register contents. */
reg[0][0] = (core->a.getNThds()<<(core->a.getWordSize()*8 / 2)) | id;
}
@ -130,6 +136,8 @@ void Warp::step() {
D(3, "in step pc=0x" << hex << pc);
// std::cout << "pc: " << hex << pc << "\n";
/* Fetch and decode. */
if (wordSize < sizeof(pc)) pc &= ((1ll<<(wordSize*8))-1);
Instruction *inst;
@ -243,8 +251,13 @@ bool Warp::interrupt(Word r0) {
}
void Warp::printStats() const {
cout << "Steps: " << steps << endl
<< "Insts: " << insts << endl
<< "Loads: " << loads << endl
cout << "Steps : " << steps << endl
<< "Insts : " << insts << endl
<< "Loads : " << loads << endl
<< "Stores: " << stores << endl;
unsigned const grade = reg[0][28];
if (grade == 1) cout << "GRADE: PASSED\n";
else cout << "GRADE: FAILED " << (grade >> 1) << "\n";
}

265
src/enc.cpp
View file

@ -102,86 +102,86 @@ void Decoder::decodeChunk(TextChunk &dest, const DataChunk &src) {
Instruction *ByteDecoder::decode(const vector<Byte> &v, Size &n) {
Instruction &inst = *(new Instruction());
uint8_t pred = readByte(v, n);
if (pred != 0xff) inst.setPred(pred);
// uint8_t pred = readByte(v, n);
// if (pred != 0xff) inst.setPred(pred);
unsigned op = readByte(v, n);
inst.setOpcode(Instruction::Opcode(op));
// unsigned op = readByte(v, n);
// inst.setOpcode(Instruction::Opcode(op));
bool usedImm = false;
// bool usedImm = false;
switch (Instruction::instTable[op].argClass) {
case Instruction::AC_NONE:
break;
case Instruction::AC_2REG:
inst.setDestReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
break;
case Instruction::AC_2IMM:
inst.setDestReg(readByte(v, n));
inst.setSrcImm(readWord(v, n, wordSize));
usedImm = true;
break;
case Instruction::AC_3REG:
inst.setDestReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
break;
case Instruction::AC_3PREG:
inst.setDestPReg(readByte(v, n));
inst.setSrcPReg(readByte(v, n));
inst.setSrcPReg(readByte(v, n));
break;
case Instruction::AC_3IMM:
inst.setDestReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
inst.setSrcImm(readWord(v, n, wordSize));
usedImm = true;
break;
case Instruction::AC_3REGSRC:
inst.setSrcReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
break;
case Instruction::AC_1IMM:
inst.setSrcImm(readWord(v, n, wordSize));
usedImm = true;
break;
case Instruction::AC_1REG:
inst.setSrcReg(readByte(v, n));
break;
case Instruction::AC_3IMMSRC:
inst.setSrcReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
inst.setSrcImm(readWord(v, n, wordSize));
usedImm = true;
break;
case Instruction::AC_PREG_REG:
inst.setDestPReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
break;
case Instruction::AC_2PREG:
inst.setDestPReg(readByte(v, n));
inst.setSrcPReg(readByte(v, n));
break;
case Instruction::AC_2REGSRC:
inst.setSrcReg(readByte(v, n));
inst.setSrcReg(readByte(v, n));
break;
default:
decodeError("Unknown argument class.");
}
// switch ((Instruction::instTable[op]).argClass) {
// case Instruction::AC_NONE:
// break;
// case Instruction::AC_2REG:
// inst.setDestReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// break;
// case Instruction::AC_2IMM:
// inst.setDestReg(readByte(v, n));
// inst.setSrcImm(readWord(v, n, wordSize));
// usedImm = true;
// break;
// case Instruction::AC_3REG:
// inst.setDestReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// break;
// case Instruction::AC_3PREG:
// inst.setDestPReg(readByte(v, n));
// inst.setSrcPReg(readByte(v, n));
// inst.setSrcPReg(readByte(v, n));
// break;
// case Instruction::AC_3IMM:
// inst.setDestReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// inst.setSrcImm(readWord(v, n, wordSize));
// usedImm = true;
// break;
// case Instruction::AC_3REGSRC:
// inst.setSrcReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// break;
// case Instruction::AC_1IMM:
// inst.setSrcImm(readWord(v, n, wordSize));
// usedImm = true;
// break;
// case Instruction::AC_1REG:
// inst.setSrcReg(readByte(v, n));
// break;
// case Instruction::AC_3IMMSRC:
// inst.setSrcReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// inst.setSrcImm(readWord(v, n, wordSize));
// usedImm = true;
// break;
// case Instruction::AC_PREG_REG:
// inst.setDestPReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// break;
// case Instruction::AC_2PREG:
// inst.setDestPReg(readByte(v, n));
// inst.setSrcPReg(readByte(v, n));
// break;
// case Instruction::AC_2REGSRC:
// inst.setSrcReg(readByte(v, n));
// inst.setSrcReg(readByte(v, n));
// break;
// default:
// decodeError("Unknown argument class.");
// }
if (haveRefs && usedImm &&
refMap.find(n - wordSize) != refMap.end()) {
OffsetRef *oref = dynamic_cast<OffsetRef*>(refMap[n - wordSize]);
if (!oref) {
decodeError("Expected OffsetRef when decoding instruction stream.");
}
Ref *r = new SimpleRef(oref->name, *(Addr*)(inst.setSrcImm()),
inst.hasRelImm());
inst.setImmRef(*r);
}
// if (haveRefs && usedImm &&
// refMap.find(n - wordSize) != refMap.end()) {
// OffsetRef *oref = dynamic_cast<OffsetRef*>(refMap[n - wordSize]);
// if (!oref) {
// decodeError("Expected OffsetRef when decoding instruction stream.");
// }
// Ref *r = new SimpleRef(oref->name, *(Addr*)(inst.setSrcImm()),
// inst.hasRelImm());
// inst.setImmRef(*r);
// }
return &inst;
}
@ -191,38 +191,39 @@ ByteEncoder::ByteEncoder(const ArchDef &ad) {
}
Size ByteEncoder::encode(Ref *&ref, vector<Byte> &v, Size n0, Instruction &i) {
Size n(n0);
// Size n(n0);
if (i.hasPred()) writeByte(v, n, i.getPred());
else writeByte(v, n, 0xff);
// if (i.hasPred()) writeByte(v, n, i.getPred());
// else writeByte(v, n, 0xff);
writeByte(v, n, Byte(i.getOpcode()));
// writeByte(v, n, Byte(i.getOpcode()));
if (i.hasRDest()) {
writeByte(v, n, Byte(i.getRDest()));
} else if (i.hasPDest()) {
writeByte(v, n, Byte(i.getPDest()));
}
// if (i.hasRDest()) {
// writeByte(v, n, Byte(i.getRDest()));
// } else if (i.hasPDest()) {
// writeByte(v, n, Byte(i.getPDest()));
// }
for (RegNum j = 0; j < i.getNRSrc(); j++) {
writeByte(v, n, Byte(i.getRSrc(j)));
}
// for (RegNum j = 0; j < i.getNRSrc(); j++) {
// writeByte(v, n, Byte(i.getRSrc(j)));
// }
for (RegNum j = 0; j < i.getNPSrc(); j++) {
writeByte(v, n, Byte(i.getPSrc(j)));
}
// for (RegNum j = 0; j < i.getNPSrc(); j++) {
// writeByte(v, n, Byte(i.getPSrc(j)));
// }
ref = NULL;
if (i.hasImm()) {
if (i.hasRefLiteral()) {
Ref *r = i.getRefLiteral();
ref = new OffsetRef(r->name, v, n, wordSize*8, wordSize, i.hasRelImm());
}
// ref = NULL;
// if (i.hasImm()) {
// if (i.hasRefLiteral()) {
// Ref *r = i.getRefLiteral();
// ref = new OffsetRef(r->name, v, n, wordSize*8, wordSize, i.hasRelImm());
// }
writeWord(v, n, wordSize, i.getImm());
}
// writeWord(v, n, wordSize, i.getImm());
// }
return n - n0;
// return n - n0;
return 0;
}
static unsigned ceilLog2(RegNum x) {
@ -272,91 +273,97 @@ WordDecoder::WordDecoder(const ArchDef &arch) {
}
Word signExt(Word w, Size bit, Word mask) {
static Word signExt(Word w, Size bit, Word mask) {
if (w>>(bit-1)) w |= ~mask;
return w;
}
Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx) {
Word code(readWord(v, idx, n/8));
Word code(readWord(v, idx, inst_s/8));
// std::cout << "code: " << (int) code << " v: " << v << " indx: " << idx << "\n";
Instruction &inst = * new Instruction();
// bool predicated = (code>>(n-1));
bool predicated = false;
if (predicated) { inst.setPred((code>>(n-p-1))&pMask); }
if (predicated) { inst.setPred((code>>(inst_s-p-1))&pMask); }
Instruction::Opcode op = (Instruction::Opcode)((code>>shift_opcode)&opcode_mask);
Opcode op = (Opcode)((code>>shift_opcode)&opcode_mask);
// std::cout << "opcode: " << op << "\n";
inst.setOpcode(op);
bool usedImm(false);
switch(Instruction::instTable[op].iType)
Word imeed, dest_bits, imm_bits, bit_11, bits_4_1, bit_10_5,
bit_12, bits_19_12, bits_10_1, bit_20, unordered;
switch(instTable[op].iType)
{
case Instruction::InstType::N_TYPE:
case InstType::N_TYPE:
break;
case Instruction::InstType::R_TYPE:
case InstType::R_TYPE:
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setFunc3 ((code>>shift_func3) & func3_mask);
inst.setFunc7 ((code>>shift_func7) & func7_mask);
break;
case Instruction::InstType::I_TYPE
case InstType::I_TYPE:
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setFunc3 ((code>>shift_func3) & func3_mask);
inst.setSrcImm(signExt(code>>shift_i_immed, 12, i_immed_mask));
usedImm = true;
break;
case Instruction::InstType::S_TYPE:
case InstType::S_TYPE:
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setFunc3 ((code>>shift_func3) & func3_mask);
word dest_bits = (code>>shift_rd) & reg_mask;
Word imm_bits = (code>>shift_s_b_immed & func7_mask);
Word imeed = (imm_bits << reg_s) | dest_bits;
dest_bits = (code>>shift_rd) & reg_mask;
imm_bits = (code>>shift_s_b_immed & func7_mask);
imeed = (imm_bits << reg_s) | dest_bits;
inst.setSrcImm(signExt(imeed, 12, s_immed_mask));
usedImm = true;
break;
case Instruction::InstType::B_TYPE:
case InstType::B_TYPE:
inst.setSrcReg((code>>shift_rs1) & reg_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setFunc3 ((code>>shift_func3) & func3_mask);
word dest_bits = (code>>shift_rd) & reg_mask;
Word imm_bits = (code>>shift_s_b_immed & func7_mask);
dest_bits = (code>>shift_rd) & reg_mask;
imm_bits = (code>>shift_s_b_immed & func7_mask);
Word bit_11 = dest_bits & 0x1;
Word bit_4_1 = dest_bits >> 1;
Word bit_10_5 = imm_bits & 0x3f;
Word bit_12 = imm_bits >> 6;
bit_11 = dest_bits & 0x1;
bits_4_1 = dest_bits >> 1;
bit_10_5 = imm_bits & 0x3f;
bit_12 = imm_bits >> 6;
Word imeed = 0 | (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
imeed = 0 | (bits_4_1 << 1) | (bit_10_5 << 5) | (bit_11 << 11) | (bit_12 << 12);
inst.setSrcImm(signExt(imeed, 13, b_immed_mask));
usedImm = true;
break;
case Instruction::InstType::U_TYPE:
case InstType::U_TYPE:
inst.setDestReg((code>>shift_rd) & reg_mask);
inst.setSrcImm(signExt(code>>shift_j_u_immed, 20, u_immed_mask));
usedImm = true;
break;
case Instruction::InstType::J_TYPE:
case InstType::J_TYPE:
inst.setDestReg((code>>shift_rd) & reg_mask);
// [20 | 10:1 | 11 | 19:12]
Word unordered = code>>shift_j_u_immed;
unordered = code>>shift_j_u_immed;
Word bits_19_12 = unordered & 0xff;
Word bit_11 = (unordered>>8) & 0x1;
Word bits_10_1 = (unordered >> 9) & 0x3ff;
Word bit_20 = (unordered>>19) & 0x1;
bits_19_12 = unordered & 0xff;
bit_11 = (unordered>>8) & 0x1;
bits_10_1 = (unordered >> 9) & 0x3ff;
bit_20 = (unordered>>19) & 0x1;
Word imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit20 << 20);
imeed = 0 | (bits_10_1 << 1) | (bit_11 << 11) | (bits_19_12 << 12) | (bit_20 << 20);
inst.setSrcImm(signExt(imeed, 20, j_immed_mask));
usedImm = true;

212
src/firmware/firmware.c Normal file
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@ -0,0 +1,212 @@
/*
* PicoSoC - A simple example SoC using PicoRV32
*
* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include <stdint.h>
#include <stdbool.h>
// #if !defined(ICEBREAKER) && !defined(HX8KDEMO)
// # error "Set -DICEBREAKER or -DHX8KDEMO when compiling firmware.c"
// #endif
// a pointer to this is a null pointer, but the compiler does not
// know that because "sram" is a linker symbol from sections.lds.
#define reg_uart_data (*(volatile uint32_t*)0xFF000000)
// --------------------------------------------------------
// --------------------------------------------------------
int main()
{
// FUNC DEFINITIONS
void putchar(char);
void print(const char *);
char getchar_prompt(char *);
void getsent_prompt(char *, char *);
char arr[2];
arr[1] = 0;
char c;
print("$ Booting..\n");
while ((c = getchar_prompt("$ Press ENTER to continue.. ")) != '\n')
{
// arr[0] = c;
// print("char printed[ ");
// print(arr);
// print(" ]\n");
}
// getchar_prompt("Press ENTER to continue..\n");
print("$ \n");
print(" ______ __ __ _______ ______ ______ ______ __ __ \n");
print(" / \\ | \\ | \\ | \\| \\/ \\ / \\ | \\ | \\\n");
print("| $$$$$$\\ ______ | $$____ \\$$_______ __ __ | $$$$$$$\\\\$$$$$| $$$$$$| $$$$$$\\ | $$ | $$\n");
print("| $$___\\$$/ \\| $$ \\| | \\| \\ / \\ | $$__| $$ | $$ | $$___\\$| $$ \\$_____| $$ | $$\n");
print(" \\$$ \\| $$$$$$| $$$$$$$| $| $$$$$$$\\\\$$\\/ $$ | $$ $$ | $$ \\$$ \\| $$ | \\$$\\ / $$\n");
print(" _\\$$$$$$| $$ | $| $$ | $| $| $$ | $$ >$$ $$ | $$$$$$$\\ | $$ _\\$$$$$$| $$ __\\$$$$$$\\$$\\ $$ \n");
print("| \\__| $| $$__/ $| $$ | $| $| $$ | $$/ $$$$\\ | $$ | $$_| $$_| \\__| $| $$__/ \\ \\$$ $$ \n");
print(" \\$$ $| $$ $| $$ | $| $| $$ | $| $$ \\$$\\ | $$ | $| $$ \\\\$$ $$\\$$ $$ \\$$$ \n");
print(" \\$$$$$$| $$$$$$$ \\$$ \\$$\\$$\\$$ \\$$\\$$ \\$$ \\$$ \\$$\\$$$$$$ \\$$$$$$ \\$$$$$$ \\$ \n");
print(" | $$ \n");
print(" | $$ \n");
print(" \\$$ \n");
print("\n");
char buf[50];
while (1)
{
getsent_prompt("$ Do you want to play a guessing game? [y/n] ", buf);
c = buf[0];
if (c == 'y')
{
break;
} else if (c == 'n')
{
return 0;
} else
{
print("\n$ Wrong input, please try again\n");
}
}
char n = '5';
while (1)
{
getsent_prompt("> Guess a number between 0 and 9: ", buf);
c = buf[0];
if (c < n)
{
print("> The number is larger\n");
} else if (c > n)
{
print("> The number is smaller\n");
} else
{
print(" _ _ _ _ _ _ \n");
print(" | | | | | | (_) | | |\n");
print(" ___ ___ _ __ __ _ _ __ __ _| |_ _ _| | __ _| |_ _ ___ _ __ ___| | |\n");
print(" / __/ _ \\| '_ \\ / _` | '__/ _` | __| | | | |/ _` | __| |/ _ \\| '_ \\/ __| | |\n");
print(" | (_| (_) | | | | (_| | | | (_| | |_| |_| | | (_| | |_| | (_) | | | \\__ \\_|_|\n");
print(" \\___\\___/|_| |_|\\__, |_| \\__,_|\\__|\\__,_|_|\\__,_|\\__|_|\\___/|_| |_|___(_|_)\n");
print(" __/ | \n");
print(" |___/ \n");
print("\n");
break;
}
}
print("$ Press CNTR-C to exit ");
return 0;
}
void putchar(char c)
{
if (c == '\n')
putchar('\r');
reg_uart_data = c;
}
void print(const char *p)
{
while (*p)
putchar(*(p++));
}
char getchar_prompt(char *prompt)
{
int32_t c = -1;
uint32_t cycles_begin, cycles_now, cycles;
__asm__ volatile ("rdcycle %0" : "=r"(cycles_begin));
cycles = 0;
if (prompt)
print(prompt);
while (c == -1) {
__asm__ volatile ("rdcycle %0" : "=r"(cycles_now));
cycles = cycles_now - cycles_begin;
// if (cycles > 1200000) {
// if (prompt)
// print(prompt);
// cycles_begin = cycles_now;
// }
c = reg_uart_data;
}
print("\n");
return c;
}
void getsent_prompt(char *prompt, char * buf)
{
int32_t c = -1;
uint32_t cycles_begin, cycles_now, cycles;
__asm__ volatile ("rdcycle %0" : "=r"(cycles_begin));
cycles = 0;
if (prompt)
print(prompt);
int inx = 0;
while (c != (int) '\n') {
__asm__ volatile ("rdcycle %0" : "=r"(cycles_now));
cycles = cycles_now - cycles_begin;
// if (cycles > 1200000) {
// if (prompt)
// print(prompt);
// cycles_begin = cycles_now;
// }
c = reg_uart_data;
if (c != -1)
{
buf[inx] = c;
inx++;
}
}
// print("\n");
return;
}

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src/firmware/firmware.dump Normal file
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src/firmware/firmware.elf Executable file
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201
src/firmware/firmware.hex Normal file
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@ -0,0 +1,201 @@
:0200000480007A
:10000000130101FB23261104232481041304010599
:10001000A30604FEB707008113850700EF00C02583
:1000200013000000B707008113850701EF00C02906
:1000300093070500A307F4FE0347F4FE9307A0000F
:10004000E312F7FEB707008113850703EF00C02214
:10005000B707008113858703EF000022B7070081EF
:100060001385470AEF004021B70700811385071168
:10007000EF008020B70700811385C717EF00C01F6E
:10008000B70700811385871EEF00001FB7070081A7
:1000900013854725EF00401EB70700811385072C05
:1000A000EF00801DB70700811385C732EF00C01C29
:1000B000B707008113858739EF00001CB70700815F
:1000C00013854740EF00401BB70700811385474069
:1000D000EF00801AB707008113850747EF00C019AA
:1000E000B70700811385C74DEF000019930784FB04
:1000F00093850700B70700811385074EEF000026A0
:10010000834784FBA307F4FE0347F4FE930790079D
:100110006304F7020347F4FE9307E0066316F70053
:10012000930700006F00400FB70700811385075148
:10013000EF0080146FF09FFB130000009307500343
:100140002307F4FE930784FB93850700B70700811C
:1001500013854753EF008020834784FBA307F4FEF9
:100160000347F4FE8347E4FE637AF700B707008194
:1001700013858755EF0040106FF0DFFC0347F4FE56
:100180008347E4FE63FAE700B7070081138547570A
:10019000EF00800E6FF01FFBB70700811385075932
:1001A000EF00800DB70700811385075EEF00C00CDC
:1001B000B707008113850763EF00000CB7070081C4
:1001C00013850768EF00400BB70700811385076DA3
:1001D000EF00800AB707008113850772EF00C0099E
:1001E000B707008113850777EF000009B707008183
:1001F0001385077CEF004008B70700811385C74DC2
:10020000EF00800713000000B717008113850781F6
:10021000EF00800693070000138507008320C104C8
:10022000032481041301010567800000130101FE0E
:10023000232E1100232C81001304010293070500D3
:10024000A307F4FE0347F4FE9307A0006316F7002C
:100250001305D000EFF09FFDB70700FF0347F4FE42
:1002600023A0E700130000008320C10103248101C3
:100270001301010267800000130101FE232E11000B
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:100290008327C4FE138717002326E4FE83C70700C5
:1002A00013850700EFF09FF88327C4FE83C707007C
:1002B000E39007FE130000008320C10103248101A5
:1002C0001301010267800000130101FD23261102C2
:1002D0002324810213040103232EA4FC9307F0FFBF
:1002E0002326F4FEF32700C02324F4FE232204FE79
:1002F0008327C4FD638A07020325C4FDEFF0DFF7FF
:100300006F008002F32700C02320F4FE032704FEC1
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11
src/firmware/firmware1.hex Normal file
View file

@ -0,0 +1,11 @@
:0200000480007A
:10000000130101FE232E810013040102B7070081B2
:10001000938707002326F4FE6F0040028327C4FE67
:10002000138717002326E4FE83C70700A305F4FE09
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:0C0050000324C1011301010267800000BD
:02000004810079
:09000000626F6F74696E670A00FB
:040000058000000077
:00000001FF

3
src/firmware/hi.sh Executable file
View file

@ -0,0 +1,3 @@
/opt/riscv-nommu/bin/riscv32-unknown-linux-gnu-gcc -march=rv32i -mabi=ilp32 -Wl,-Bstatic,-T,linker.ld -ffreestanding -nostdlib firmware.c -o firmware.elf
/opt/riscv-nommu/bin/riscv32-unknown-linux-gnu-objdump -D firmware.elf > firmware.dump
/opt/riscv-nommu/bin/riscv32-unknown-linux-gnu-objcopy -O ihex firmware.elf firmware.hex

44
src/firmware/linker.ld Normal file
View file

@ -0,0 +1,44 @@
/* ---- Original Script: /opt/riscv32i/riscv32-unknown-elf/lib/ldscripts/elf32lriscv.x ---- */
/* Default linker script, for normal executables */
/* Copyright (C) 2014-2017 Free Software Foundation, Inc.
Copying and distribution of this script, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. */
OUTPUT_FORMAT("elf32-littleriscv", "elf32-littleriscv",
"elf32-littleriscv")
OUTPUT_ARCH(riscv)
ENTRY(main)
SECTIONS
{
. = 0x80000000;
.text :
{
*(.text)
*(.text.unlikely .text.*_unlikely .text.unlikely.*)
*(.text.exit .text.exit.*)
*(.text.startup .text.startup.*)
*(.text.hot .text.hot.*)
*(.stub .text.* .gnu.linkonce.t.*)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
}
.init :
{
KEEP (*(SORT_NONE(.init)))
}
.plt : { *(.plt) }
.iplt : { *(.iplt) }
.fini :
{
KEEP (*(SORT_NONE(.fini)))
}
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
. = 0x81000000;
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
. = 0x82000000;
.comment : { *(.comment) }
}

29
src/harptool.cpp
View file

@ -21,6 +21,7 @@
#include "include/args.h"
#include "include/help.h"
using namespace Harp;
using namespace HarpTools;
using namespace std;
@ -207,7 +208,7 @@ int disasm_main(int argc, char **argv) {
}
int emu_main(int argc, char **argv) {
string archString("8w32/32/8/8"), imgFileName("a.out.bin");
string archString("rv32i"), imgFileName("a.dsfsdout.bin");
bool showHelp, showStats, basicMachine, batch;
/* Read the command line arguments. */
@ -238,18 +239,28 @@ int emu_main(int argc, char **argv) {
return 1;
}
MemoryUnit mu(4096, arch.getWordSize(), basicMachine);
Core core(arch, *dec, mu/*, ID in multicore implementations*/);
// std::cout << "TESTING: " << tests[t] << "\n";
RamMemDevice mem(imgFileName.c_str(), arch.getWordSize());
ConsoleMemDevice console(arch.getWordSize(), cout, core, batch);
mu.attach(mem, 0);
mu.attach(console, 1ll<<(arch.getWordSize()*8 - 1));
MemoryUnit mu(4096, arch.getWordSize(), basicMachine);
Core core(arch, *dec, mu/*, ID in multicore implementations*/);
while (core.running()) { console.poll(); core.step(); }
// RamMemDevice mem(imgFileName.c_str(), arch.getWordSize());
RAM old_ram;
old_ram.loadHexImpl(imgFileName.c_str());
// old_ram.loadHexImpl(tests[t]);
if (showStats) core.printStats();
// MemDevice * memory = &old_ram;
ConsoleMemDevice console(arch.getWordSize(), cout, core, batch);
mu.attach(old_ram, 0);
mu.attach(console, 1ll<<(arch.getWordSize()*8 - 1));
while (core.running()) { console.poll(); core.step(); }
if (showStats) core.printStats();
std::cout << "\n";
return 0;
}

28
src/include/archdef.h
View file

@ -26,21 +26,21 @@ namespace Harp {
nThds = 1;
nWarps = 1;
extent = EXT_REGS;
if (!iss) { extent = EXT_NULL; return; }
iss >> encChar;
if (!iss) { extent = EXT_WORDSIZE; return; }
iss >> nRegs;
if (!iss) { extent = EXT_ENC; return; }
char sep;
iss >> sep >> nPRegs;
if (!iss || sep != '/') { extent = EXT_REGS; return; }
iss >> sep >> nThds;
if (!iss || sep != '/') { extent = EXT_PREGS; return; }
iss >> sep >> nWarps;
if (!iss || sep != '/') { extent = EXT_THDS; return; }
extent = EXT_WARPS;
// if (!iss) { extent = EXT_NULL; return; }
// iss >> encChar;
// if (!iss) { extent = EXT_WORDSIZE; return; }
// iss >> nRegs;
// if (!iss) { extent = EXT_ENC; return; }
// char sep;
// iss >> sep >> nPRegs;
// if (!iss || sep != '/') { extent = EXT_REGS; return; }
// iss >> sep >> nThds;
// if (!iss || sep != '/') { extent = EXT_PREGS; return; }
// iss >> sep >> nWarps;
// if (!iss || sep != '/') { extent = EXT_THDS; return; }
// extent = EXT_WARPS;
}
operator std::string () const {

3
src/include/core.h
View file

@ -27,7 +27,7 @@ namespace Harp {
Reg(): cpuId(0), regNum(0), val(0) {}
Reg(Word c, Word n): cpuId(c), regNum(n), val(0) {}
Reg &operator=(T r) { val = r; doWrite(); return *this; }
Reg &operator=(T r) { if (regNum) {val = r; doWrite();} return *this; }
operator T() const { doRead(); return val; }
@ -120,6 +120,7 @@ namespace Harp {
Size activeThreads, shadowActiveThreads;
std::vector<std::vector<Reg<Word> > > reg;
std::vector<std::vector<Reg<bool> > > pred;
std::vector<Reg<uint16_t> > csr;
std::vector<bool> tmask, shadowTmask;
std::stack<DomStackEntry> domStack;

2
src/include/debug.h
View file

@ -4,6 +4,8 @@
#ifndef __DEBUG_H
#define __DEBUG_H
// #define USE_DEBUG 9
#ifdef USE_DEBUG
#include <iostream>

87
src/include/instruction.h
View file

@ -13,6 +13,50 @@ namespace Harp {
class Warp;
class Ref;
enum Opcode
{
NOP = 0,
R_INST = 51,
L_INST = 3,
I_INST = 19,
S_INST = 35,
B_INST = 99,
LUI_INST = 55,
AUIPC_INST = 23,
JAL_INST = 111,
JALR_INST = 103,
SYS_INST = 115,
TRAP = 0x7f,
FENCE = 0x0f
};
enum InstType { N_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE};
// We build a table of instruction information out of this.
struct InstTableEntry_t {
const char *opString;
bool controlFlow, relAddress, allSrcArgs, privileged;
InstType iType;
};
static std::map<int, struct InstTableEntry_t> instTable =
{
{Opcode::NOP, {"nop" , false, false, false, false, InstType::N_TYPE }},
{Opcode::R_INST, {"r_type", false, false, false, false, InstType::R_TYPE }},
{Opcode::L_INST, {"load" , false, false, false, false, InstType::I_TYPE }},
{Opcode::I_INST, {"i_type", false, false, false, false, InstType::I_TYPE }},
{Opcode::S_INST, {"store" , false, false, false, false, InstType::I_TYPE }},
{Opcode::B_INST, {"branch", true , false, false, false, InstType::B_TYPE }},
{Opcode::LUI_INST, {"lui" , false, false, false, false, InstType::U_TYPE }},
{Opcode::AUIPC_INST, {"auipc" , false, false, false, false, InstType::U_TYPE }},
{Opcode::JAL_INST, {"jal" , true , false, false, false, InstType::J_TYPE }},
{Opcode::JALR_INST, {"jalr" , true , false, false, false, InstType::I_TYPE }},
{Opcode::SYS_INST, {"SYS" , true , false, false, false, InstType::I_TYPE }},
{Opcode::TRAP, {"TRAP" , true , false, false, false, InstType::I_TYPE }},
{Opcode::FENCE, {"fence" , true , false, false, false, InstType::I_TYPE }}
};
static const Size MAX_REG_SOURCES(3);
static const Size MAX_PRED_SOURCES(2);
@ -25,51 +69,10 @@ namespace Harp {
class Instruction {
public:
enum Opcode
{
NOP = 0,
R_INST = 51,
L_INST = 3,
I_INST = 19,
S_INST = 35,
B_INST = 99,
LUI_INST = 55,
AUIPC_INST = 23,
JAL_INST = 111,
JALR_INST = 103,
SYS_INST = 115
};
enum InstType { N_TYPE, R_TYPE, I_TYPE, S_TYPE, B_TYPE, U_TYPE, J_TYPE };
// We build a table of instruction information out of this.
struct InstTableEntry_t {
const char *opString;
bool controlFlow, relAddress, allSrcArgs, privileged;
InstType iType;
};
Instruction() :
predicated(false), nRsrc(0), nPsrc(0), immsrcPresent(false),
rdestPresent(false), pdestPresent(false), refLiteral(NULL)
{
instTable = std::map<int, struct InstTableEntry_t>
{
{Opcode::NOP, {"nop" , false, false, false, false, InstType::N_TYPE }},
{Opcode::R_INST, {"r_type", false, false, false, false, InstType::R_TYPE }},
{Opcode::L_INST, {"load" , false, false, false, false, InstType::I_TYPE }},
{Opcode::I_INST, {"i_type", false, false, false, false, InstType::I_TYPE }},
{Opcode::S_INST, {"store" , false, false, false, false, InstType::I_TYPE }},
{Opcode::B_INST, {"branch", true , false, false, false, InstType::B_TYPE }},
{Opcode::LUI_INST, {"lui" , false, false, false, false, InstType::U_TYPE }},
{Opcode::AUIPC_INST, {"auipc" , false, false, false, false, InstType::U_TYPE }},
{Opcode::JAL_INST, {"jal" , true , false, false, false, InstType::J_TYPE }},
{Opcode::JALR_INST, {"jalr" , true , false, false, false, InstType::I_TYPE }},
{Opcode::SYS_INST, {"SYS" , true , false, false, false, InstType::I_TYPE }}
};
}
void executeOn(Warp &warp);
@ -123,7 +126,7 @@ namespace Harp {
Ref *refLiteral;
public:
static std::map<int, struct InstTableEntry_t> instTable;
};
};

257
src/include/mem.h
View file

@ -124,7 +124,7 @@ namespace Harp {
Word read(Addr, bool sup); /* For data accesses. */
Word fetch(Addr, bool sup); /* For instruction accesses. */
Byte *getPtr(Addr, Size);
void write(Addr, Word, bool sup);
void write(Addr, Word, bool sup, Size);
void tlbAdd(Addr virt, Addr phys, Word flags);
void tlbRm(Addr va);
void tlbFlush() { tlb.clear(); }
@ -166,6 +166,261 @@ namespace Harp {
bool disableVm;
};
class RAM : public MemDevice {
public:
uint8_t* mem[1 << 12];
RAM(){
for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL;
}
~RAM(){
for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete [] mem[i];
}
void clear(){
for(uint32_t i = 0;i < (1 << 12);i++)
{
if(mem[i])
{
delete mem[i];
mem[i] = NULL;
}
}
}
uint8_t* get(uint32_t address){
if(mem[address >> 20] == NULL) {
uint8_t* ptr = new uint8_t[1024*1024];
for(uint32_t i = 0;i < 1024*1024;i+=4) {
ptr[i + 0] = 0xFF;
ptr[i + 1] = 0xFF;
ptr[i + 2] = 0xFF;
ptr[i + 3] = 0xFF;
}
mem[address >> 20] = ptr;
}
return &mem[address >> 20][address & 0xFFFFF];
}
void read(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
data[i] = (*this)[address + i];
}
}
void write(uint32_t address,uint32_t length, uint8_t *data){
for(unsigned i = 0;i < length;i++){
(*this)[address + i] = data[i];
}
}
virtual Size size() const { return (1<<31); };
void getBlock(uint32_t address, uint8_t *data)
{
uint32_t block_number = address & 0xffffff00; // To zero out block offset
uint32_t bytes_num = 256;
this->read(block_number, bytes_num, data);
}
void getWord(uint32_t address, uint32_t * data)
{
data[0] = 0;
uint8_t first = *get(address + 0);
uint8_t second = *get(address + 1);
uint8_t third = *get(address + 2);
uint8_t fourth = *get(address + 3);
// uint8_t hi = (uint8_t) *get(address + 0);
// std::cout << "RAM: READING ADDRESS " << address + 0 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 1);
// std::cout << "RAM: READING ADDRESS " << address + 1 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 2);
// std::cout << "RAM: READING ADDRESS " << address + 2 << " DATA: " << hi << "\n";
// hi = (uint8_t) *get(address + 3);
// std::cout << "RAM: READING ADDRESS " << address + 3 << " DATA: " << hi << "\n";
data[0] = (data[0] << 0) | fourth;
data[0] = (data[0] << 8) | third;
data[0] = (data[0] << 8) | second;
data[0] = (data[0] << 8) | first;
}
void writeWord(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 4; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeHalf(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
for (int i = 0; i < 2; i++)
{
// std::cout << "RAM: DATA TO WRITE " << data_to_write << "\n";
// std::cout << "RAM: DATA TO MASK " << byte_mask << "\n";
// std::cout << "RAM: WRITING ADDRESS " << address + i << " DATA: " << (data_to_write & byte_mask) << "\n";
(*this)[address + i] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
}
void writeByte(uint32_t address, uint32_t * data)
{
uint32_t data_to_write = *data;
uint32_t byte_mask = 0xFF;
(*this)[address] = data_to_write & byte_mask;
data_to_write = data_to_write >> 8;
}
uint8_t& operator [](uint32_t address) {
return *get(address);
}
virtual void write(Addr addr, Word w)
{
uint32_t word = (uint32_t) w;
writeWord(addr, &word);
}
virtual Word read(Addr addr)
{
uint32_t w;
getWord(addr, &w);
return (Word) w;
}
virtual Byte *base()
{
return (Byte *) this->get(0);
}
// MEMORY UTILS
uint32_t hti_old(char c) {
if (c >= 'A' && c <= 'F')
return c - 'A' + 10;
if (c >= 'a' && c <= 'f')
return c - 'a' + 10;
return c - '0';
}
uint32_t hToI_old(char *c, uint32_t size) {
uint32_t value = 0;
for (uint32_t i = 0; i < size; i++) {
value += hti_old(c[i]) << ((size - i - 1) * 4);
}
return value;
}
void loadHexImpl(std::string path) {
this->clear();
FILE *fp = fopen(&path[0], "r");
if(fp == 0){
std::cout << path << " not found" << std::endl;
}
//Preload 0x0 <-> 0x80000000 jumps
((uint32_t*)this->get(0))[0] = 0xf1401073;
((uint32_t*)this->get(0))[1] = 0xf1401073;
// ((uint32_t*)this->get(0))[1] = 0xf1401073;
((uint32_t*)this->get(0))[2] = 0x30101073;
((uint32_t*)this->get(0))[3] = 0x800000b7;
((uint32_t*)this->get(0))[4] = 0x000080e7;
((uint32_t*)this->get(0x80000000))[0] = 0x00000097;
((uint32_t*)this->get(0xb0000000))[0] = 0x01C02023;
// F00FFF10
((uint32_t*)this->get(0xf00fff10))[0] = 0x12345678;
fseek(fp, 0, SEEK_END);
uint32_t size = ftell(fp);
fseek(fp, 0, SEEK_SET);
char* content = new char[size];
int x = fread(content, 1, size, fp);
if (!x) { std::cout << "COULD NOT READ FILE\n"; exit(1);}
int offset = 0;
char* line = content;
// std::cout << "WHTA\n";
while (1) {
if (line[0] == ':') {
uint32_t byteCount = hToI_old(line + 1, 2);
uint32_t nextAddr = hToI_old(line + 3, 4) + offset;
uint32_t key = hToI_old(line + 7, 2);
switch (key) {
case 0:
for (uint32_t i = 0; i < byteCount; i++) {
unsigned add = nextAddr + i;
*(this->get(add)) = hToI_old(line + 9 + i * 2, 2);
// std::cout << "Address: " << std::hex <<(add) << "\tValue: " << std::hex << hToI_old(line + 9 + i * 2, 2) << std::endl;
}
break;
case 2:
// cout << offset << endl;
offset = hToI_old(line + 9, 4) << 4;
break;
case 4:
// cout << offset << endl;
offset = hToI_old(line + 9, 4) << 16;
break;
default:
// cout << "??? " << key << endl;
break;
}
}
while (*line != '\n' && size != 0) {
line++;
size--;
}
if (size <= 1)
break;
line++;
size--;
}
if (content) delete[] content;
}
};
};
#endif

58
src/include/obj.h
View file

@ -16,38 +16,38 @@
#include "enc.h"
#include "asm-tokens.h"
// namespace Harp {
// class Decoder;
// class Encoder;
namespace Harp {
class Decoder;
class Encoder;
// class Ref {
// public:
// std::string name;
// Ref(const std::string &n, bool r, Size ib = 0):
// name(n), bound(false), relative(r), ibase(ib) { }
// virtual ~Ref() { }
// virtual void bind(Addr addr, Addr base = 0) = 0;
// virtual Addr getAddr() const = 0;
class Ref {
public:
std::string name;
Ref(const std::string &n, bool r, Size ib = 0):
name(n), bound(false), relative(r), ibase(ib) { }
virtual ~Ref() { }
virtual void bind(Addr addr, Addr base = 0) = 0;
virtual Addr getAddr() const = 0;
// bool bound, relative;
// Size ibase;
// };
bool bound, relative;
Size ibase;
};
// /* Used in not-yet-encoded code objects, plain old data. */
// class SimpleRef : public Ref {
// public:
// SimpleRef(const std::string &name, Addr &addr, bool rel = false) :
// Ref(name, rel), addr(addr) { }
// virtual void bind(Addr addr, Addr base = 0) {
// std::cout << "Attempted to bind a SimpleRef.\n";
// exit(1);
// }
// virtual Addr getAddr() const { return this->addr; }
// Byte *getAddrPtr() { return (Byte*)&addr; }
/* Used in not-yet-encoded code objects, plain old data. */
class SimpleRef : public Ref {
public:
SimpleRef(const std::string &name, Addr &addr, bool rel = false) :
Ref(name, rel), addr(addr) { }
virtual void bind(Addr addr, Addr base = 0) {
std::cout << "Attempted to bind a SimpleRef.\n";
exit(1);
}
virtual Addr getAddr() const { return this->addr; }
Byte *getAddrPtr() { return (Byte*)&addr; }
// private:
// Addr &addr;
// };
private:
Addr &addr;
};
// /* Used in already-encoded code objects. */
// class OffsetRef : public Ref {
@ -205,6 +205,6 @@
// private:
// const ArchDef &arch;
// };
// };
};
#endif

468
src/instruction.cpp
View file

@ -41,7 +41,7 @@ ostream &Harp::operator<<(ostream& os, Instruction &inst) {
// else os << "#0x" << hex << inst.immsrc;
// }
os << inst.instTable[inst.op].opString;
os << instTable[inst.op].opString;
os << ';';
return os;
@ -80,6 +80,7 @@ void Instruction::executeOn(Warp &c) {
/* If I try to execute a privileged instruction in user mode, throw an
exception 3. */
if (instTable[op].privileged && !c.supervisorMode) {
std::cout << "INTERRUPT SUPERVISOR\n";
c.interrupt(3);
return;
}
@ -127,9 +128,12 @@ void Instruction::executeOn(Warp &c) {
// op != SPLIT && op != JOIN) continue;
++c.insts;
Word memAddr;
Word shift_by;
Word shamt;
Word temp;
int op1, op2;
switch (op) {
case NOP: break;
@ -153,7 +157,7 @@ void Instruction::executeOn(Warp &c) {
reg[rdest].trunc(wordSz);
break;
case 2:
if ( Word_s(reg[rsrc[0]]) < Word_s(reg[rsrc[1]]))
if ( int(reg[rsrc[0]]) < int(reg[rsrc[1]]))
{
reg[rdest] = 1;
}
@ -178,7 +182,7 @@ void Instruction::executeOn(Warp &c) {
case 5:
if (func7)
{
reg[rdest] = Word_s(reg[rsrc[0]]) >> Word_s(reg[rsrc[1]]);
reg[rdest] = int(reg[rsrc[0]]) >> int(reg[rsrc[1]]);
reg[rdest].trunc(wordSz);
}
else
@ -218,14 +222,15 @@ void Instruction::executeOn(Warp &c) {
reg[rdest] = signExt((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFFFF, 16, 0xFF);
break;
case 2:
reg[rdest] = Word_s(c.core->mem.read(memAddr, c.supervisorMode) & 0xFFFFFFFF);
reg[rdest] = int(c.core->mem.read(memAddr, c.supervisorMode) & 0xFFFFFFFF);
break;
case 4:
// LBU
reg[rdest] = Word_u((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFF);
break;
case 5:
reg[rdest] = Word_s((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFFFF);
reg[rdest] = int((c.core->mem.read(memAddr, c.supervisorMode) >> shift_by) & 0xFFFF);
break;
default:
cout << "ERROR: UNSUPPORTED L INST\n";
exit(1);
@ -233,231 +238,268 @@ void Instruction::executeOn(Warp &c) {
}
break;
case I_INST:
switch (func3)
{
case 0:
// ADDI
reg[rdest] = reg[rsrc[0]] + immsrc;
reg[rdest].trunc(wordSz);
break;
case 2:
// SLTI
if ( int(reg[rsrc[0]]) < int(immsrc))
{
reg[rdest] = 1;
}
else
{
reg[rdest] = 0;
}
break;
case 3:
// SLTIU
op1 = (unsigned) reg[rsrc[0]];
if ( unsigned(reg[rsrc[0]]) < unsigned(immsrc))
{
reg[rdest] = 1;
}
else
{
reg[rdest] = 0;
}
break;
case 4:
// XORI
reg[rdest] = reg[rsrc[0]] ^ immsrc;
break;
case 6:
// ORI;
reg[rdest] = reg[rsrc[0]] | immsrc;
break;
case 7:
// ANDI
reg[rdest] = reg[rsrc[0]] & immsrc;
break;
case 1:
// SLLI
reg[rdest] = reg[rsrc[0]] << immsrc;
reg[rdest].trunc(wordSz);
break;
case 5:
if (!func7)
{
// SRAI
op1 = reg[rsrc[0]];
op2 = immsrc;
reg[rdest] = op1 >> op2;
reg[rdest].trunc(wordSz);
}
else
{
// SRLI
reg[rdest] = Word_u(reg[rsrc[0]]) >> Word_u(immsrc);
reg[rdest].trunc(wordSz);
}
break;
default:
cout << "ERROR: UNSUPPORTED L INST\n";
exit(1);
}
break;
case S_INST:
++c.stores;
memAddr = reg[rsrc[1]] + immsrc;
switch (func3)
{
case 0:
c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode, 1);
break;
case 1:
c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode, 2);
break;
case 2:
c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode, 4);
break;
default:
cout << "ERROR: UNSUPPORTED S INST\n";
exit(1);
}
c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
#ifdef EMU_INSTRUMENTATION
Harp::OSDomain::osDomain->
do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
#endif
break;
case B_INST:
switch (func3)
{
case 0:
// BEQ
if (int(reg[rsrc[0]]) == int(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 1:
// BNE
// cout << "COMPARING: " << std::hex << int(reg[rsrc[0]]) << " and " << int(reg[rsrc[1]]) << "\n";
// cout << "COMPARING: " << std::hex << rsrc[0] << " and " << rsrc[1] << "\n";
if (int(reg[rsrc[0]]) != int(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 4:
// BLT
if (int(reg[rsrc[0]]) < int(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 5:
// BGE
if (int(reg[rsrc[0]]) >= int(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 6:
// BLTU
if (Word_u(reg[rsrc[0]]) < Word_u(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
case 7:
// BGEU
if (Word_u(reg[rsrc[0]]) >= Word_u(reg[rsrc[1]]))
{
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
pcSet = true;
}
break;
}
break;
case LUI_INST:
reg[rdest] = (immsrc << 12) & 0xfffff000;
break;
case AUIPC_INST:
reg[rdest] = ((immsrc << 12) & 0xfffff000) + (c.pc - 4);
break;
case JAL_INST:
if (!pcSet) nextPc = (c.pc - 4) + immsrc;
if (rdest != 0)
{
reg[rdest] = c.pc;
}
pcSet = true;
break;
case JALR_INST:
if (!pcSet) nextPc = reg[rsrc[0]] + immsrc;
if (rdest != 0)
{
reg[rdest] = c.pc;
}
// for (int z = 0; z < 32; z++) std::cout << "&&&&&&&& reg[" << z << "] = " << reg[z] << "\n";
// std::cout << "jumping to nextPc reg: " << rsrc[0] << " : " << reg[rsrc[0]] << " + " << immsrc << "\n";
pcSet = true;
break;
case SYS_INST:
temp = reg[rsrc[0]];
switch (func3)
{
case 1:
if (rdest != 0)
{
// std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF];
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
// std::cout << "\t and writing to csr: " << reg[rsrc[0]] << "\n";
c.csr[immsrc & 0x00000FFF] = temp;
break;
case 2:
if (rdest != 0)
{
// std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF];
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
// std::cout << "\t and writing to csr: " << (reg[rsrc[0]] | c.csr[immsrc & 0x00000FFF]) << "\n";
c.csr[immsrc & 0x00000FFF] = temp | c.csr[immsrc & 0x00000FFF];
break;
case 3:
if (rdest != 0)
{
//std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF];
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
//std::cout << "\t and writing to csr: " << (temp & (~c.csr[immsrc & 0x00000FFF])) << "\n";
c.csr[immsrc & 0x00000FFF] = temp & (~c.csr[immsrc & 0x00000FFF]);
break;
case 5:
if (rdest != 0)
{
//std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF];
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
//std::cout << "\t and writing to csr: " << (rsrc[0]) << "\n";
c.csr[immsrc & 0x00000FFF] = rsrc[0];
break;
case 6:
if (rdest != 0)
{
//std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF];
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
//std::cout << "\t and writing to csr: " << (rsrc[0] | c.csr[immsrc & 0x00000FFF]) << "\n";
c.csr[immsrc & 0x00000FFF] = rsrc[0] | c.csr[immsrc & 0x00000FFF];
break;
case 7:
if (rdest != 0)
{
//std::cout << "CSR: Writing to reg: " << rdest << " value: " << c.csr[immsrc & 0x00000FFF];
reg[rdest] = c.csr[immsrc & 0x00000FFF];
}
//std::cout << "\t and writing to csr: " << (rsrc[0] & (~c.csr[immsrc & 0x00000FFF])) << "\n";
c.csr[immsrc & 0x00000FFF] = rsrc[0] & (~c.csr[immsrc & 0x00000FFF]);
break;
case 0:
if (immsrc < 2)
{
std::cout << "INTERRUPT ECALL\n";
nextActiveThreads = 0;
c.interrupt(0);
}
break;
default:
break;
}
break;
case TRAP:
std::cout << "INTERRUPT TRAP\n";
nextActiveThreads = 0;
c.interrupt(0);
break;
case FENCE:
break;
default:
cout << "ERROR: Unsupported instruction: " << *this << "\n";
exit(1);
// case SHL:
// break;
// case SHR:
// break;
// case ADDI: reg[rdest] = reg[rsrc[0]] + immsrc;
// reg[rdest].trunc(wordSz);
// break;
// case SUBI: reg[rdest] = reg[rsrc[0]] - immsrc;
// reg[rdest].trunc(wordSz);
// break;
// case SHRI: reg[rdest] = Word_s(reg[rsrc[0]]) >> immsrc;
// break;
// case SHLI: reg[rdest] = reg[rsrc[0]] << immsrc;
// reg[rdest].trunc(wordSz);
// break;
// case ANDI: reg[rdest] = reg[rsrc[0]] & immsrc;
// break;
// case ORI: reg[rdest] = reg[rsrc[0]] | immsrc;
// break;
// case XORI: reg[rdest] = reg[rsrc[0]] ^ immsrc;
// break;
// case JMPI: if (!pcSet) nextPc = c.pc + immsrc;
// pcSet = true;
// break;
// case JALI: reg[rdest] = c.pc;
// if (!pcSet) nextPc = c.pc + immsrc;
// pcSet = true;
// break;
// case JALR: reg[rdest] = c.pc;
// if (!pcSet) nextPc = reg[rsrc[0]];
// pcSet = true;
// break;
// case JMPR: if (!pcSet) nextPc = reg[rsrc[0]];
// pcSet = true;
// break;
// case JALIS: nextActiveThreads = reg[rsrc[0]];
// reg[rdest] = c.pc;
// if (!pcSet) nextPc = c.pc + immsrc;
// pcSet = true;
// break;
// case JALRS: nextActiveThreads = reg[rsrc[0]];
// reg[rdest] = c.pc;
// if (!pcSet) nextPc = reg[rsrc[1]];
// pcSet = true;
// break;
// case JMPRT: nextActiveThreads = 1;
// if (!pcSet) nextPc = reg[rsrc[0]];
// pcSet = true;
// break;
// case LD: ++c.loads;
// memAddr = reg[rsrc[0]] + immsrc;
// #ifdef EMU_INSTRUMENTATION
// Harp::OSDomain::osDomain->
// do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
// #endif
// reg[rdest] = c.core->mem.read(memAddr, c.supervisorMode);
// c.memAccesses.push_back(Warp::MemAccess(false, memAddr));
// break;
// case ST: ++c.stores;
// memAddr = reg[rsrc[1]] + immsrc;
// c.core->mem.write(memAddr, reg[rsrc[0]], c.supervisorMode);
// c.memAccesses.push_back(Warp::MemAccess(true, memAddr));
// #ifdef EMU_INSTRUMENTATION
// Harp::OSDomain::osDomain->
// do_mem(0, memAddr, c.core->mem.virtToPhys(memAddr), 8, true);
// #endif
// break;
// case LDI: reg[rdest] = immsrc;
// reg[rdest].trunc(wordSz);
// break;
// case RTOP: pReg[pdest] = reg[rsrc[0]];
// break;
// case ISZERO: pReg[pdest] = !reg[rsrc[0]];
// break;
// case NOTP: pReg[pdest] = !(pReg[psrc[0]]);
// break;
// case ANDP: pReg[pdest] = pReg[psrc[0]] & pReg[psrc[1]];
// break;
// case ORP: pReg[pdest] = pReg[psrc[0]] | pReg[psrc[1]];
// break;
// case XORP: pReg[pdest] = pReg[psrc[0]] != pReg[psrc[1]];
// break;
// case ISNEG: pReg[pdest] = (1ll<<(wordSz*8 - 1))&reg[rsrc[0]];
// break;
// case HALT: c.activeThreads = 0;
// nextActiveThreads = 0;
// break;
// case TRAP: c.interrupt(0);
// break;
// case JMPRU: c.supervisorMode = false;
// if (!pcSet) nextPc = reg[rsrc[0]];
// pcSet = true;
// break;
// case SKEP: c.core->interruptEntry = reg[rsrc[0]];
// break;
// case RETI: if (t == 0) {
// c.tmask = c.shadowTmask;
// nextActiveThreads = c.shadowActiveThreads;
// c.interruptEnable = c.shadowInterruptEnable;
// c.supervisorMode = c.shadowSupervisorMode;
// for (unsigned i = 0; i < reg.size(); ++i)
// reg[i] = c.shadowReg[i];
// for (unsigned i = 0; i < pReg.size(); ++i)
// pReg[i] = c.shadowPReg[i];
// if (!pcSet) { nextPc = c.shadowPc; pcSet = true; }
// }
// break;
// case ITOF: reg[rdest] = Float(double(Word_s(reg[rsrc[0]])), wordSz);
// break;
// case FTOI: reg[rdest] = Word_s(double(Float(reg[rsrc[0]], wordSz)));
// reg[rdest].trunc(wordSz);
// break;
// case FNEG: reg[rdest] = Float(-double(Float(reg[rsrc[0]],wordSz)),wordSz);
// break;
// case FADD: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) +
// double(Float(reg[rsrc[1]], wordSz)),wordSz);
// break;
// case FSUB: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) -
// double(Float(reg[rsrc[1]], wordSz)),wordSz);
// break;
// case FMUL: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) *
// double(Float(reg[rsrc[1]], wordSz)),wordSz);
// break;
// case FDIV: reg[rdest] = Float(double(Float(reg[rsrc[0]], wordSz)) /
// double(Float(reg[rsrc[1]], wordSz)),wordSz);
// break;
// case SPLIT: if (sjOnce) {
// sjOnce = false;
// if (checkUnanimous(pred, c.pred, c.tmask)) {
// DomStackEntry e(c.tmask);
// e.uni = true;
// c.domStack.push(e);
// break;
// }
// DomStackEntry e(pred, c.pred, c.tmask, c.pc);
// c.domStack.push(c.tmask);
// c.domStack.push(e);
// for (unsigned i = 0; i < e.tmask.size(); ++i)
// c.tmask[i] = !e.tmask[i] && c.tmask[i];
// }
// break;
// case JOIN: if (sjOnce) {
// sjOnce = false;
// if (!c.domStack.empty() && c.domStack.top().uni) {
// D(2, "Uni branch at join");
// c.tmask = c.domStack.top().tmask;
// c.domStack.pop();
// break;
// }
// if (!c.domStack.top().fallThrough) {
// if (!pcSet) nextPc = c.domStack.top().pc;
// pcSet = true;
// }
// c.tmask = c.domStack.top().tmask;
// c.domStack.pop();
// }
// break;
// case WSPAWN: if (sjOnce) {
// sjOnce = false;
// D(0, "Spawning a new warp.");
// for (unsigned i = 0; i < c.core->w.size(); ++i) {
// Warp &newWarp(c.core->w[i]);
// if (newWarp.spawned == false) {
// newWarp.pc = reg[rsrc[0]];
// newWarp.reg[0][rdest] = reg[rsrc[1]];
// newWarp.activeThreads = 1;
// newWarp.supervisorMode = false;
// newWarp.spawned = true;
// break;
// }
// }
// }
// break;
// case BAR: if (sjOnce) {
// sjOnce = false;
// Word id(reg[rsrc[0]]), n(reg[rsrc[1]]);
// set<Warp*> &b(c.core->b[id]);
// // Add current warp to the barrier and halt.
// b.insert(&c);
// c.shadowActiveThreads = c.activeThreads;
// nextActiveThreads = 0;
// D(2, "Barrier " << id << ' ' << b.size() << " of " << n);
// // If the barrier's full, reactivate warps waiting at it
// if (b.size() == n) {
// set<Warp*>::iterator it;
// for (it = b.begin(); it != b.end(); ++it)
// (*it)->activeThreads = (*it)->shadowActiveThreads;
// c.core->b.erase(id);
// nextActiveThreads = c.shadowActiveThreads;
// }
// }
// break;
// default:
// cout << "ERROR: Unsupported instruction: " << *this << "\n";
// exit(1);
}
}

8
src/mem.cpp
View file

@ -152,7 +152,7 @@ Word MemoryUnit::fetch(Addr vAddr, bool sup) {
return ad.read(pAddr, sup, 8*addrBytes);
}
void MemoryUnit::write(Addr vAddr, Word w, bool sup) {
void MemoryUnit::write(Addr vAddr, Word w, bool sup, Size bytes) {
Addr pAddr;
if (disableVm) {
@ -162,7 +162,7 @@ void MemoryUnit::write(Addr vAddr, Word w, bool sup) {
TLBEntry t = tlbLookup(vAddr, flagMask);
pAddr = t.pfn*pageSize + vAddr%pageSize;
}
ad.write(pAddr, w, sup, 8*addrBytes);
ad.write(pAddr, w, sup, 8*bytes);
}
void MemoryUnit::tlbAdd(Addr virt, Addr phys, Word flags) {
@ -247,3 +247,7 @@ void DiskControllerMemDevice::write(Addr a, Word w) {
break;
}
}

419
src/results.txt Normal file
View file

@ -0,0 +1,419 @@
start
./riscv_tests/rv32ui-p-add.hex
INTERRUPT ECALL
Total steps: 453
Total insts: 453
=== Warp 0 ===
Steps : 453
Insts : 453
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-addi.hex
INTERRUPT ECALL
Total steps: 230
Total insts: 230
=== Warp 0 ===
Steps : 230
Insts : 230
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-and.hex
INTERRUPT ECALL
Total steps: 473
Total insts: 473
=== Warp 0 ===
Steps : 473
Insts : 473
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-andi.hex
INTERRUPT ECALL
Total steps: 186
Total insts: 186
=== Warp 0 ===
Steps : 186
Insts : 186
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-auipc.hex
INTERRUPT ECALL
Total steps: 47
Total insts: 47
=== Warp 0 ===
Steps : 47
Insts : 47
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-beq.hex
INTERRUPT ECALL
Total steps: 279
Total insts: 279
=== Warp 0 ===
Steps : 279
Insts : 279
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-bge.hex
INTERRUPT ECALL
Total steps: 297
Total insts: 297
=== Warp 0 ===
Steps : 297
Insts : 297
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-bgeu.hex
INTERRUPT ECALL
Total steps: 322
Total insts: 322
=== Warp 0 ===
Steps : 322
Insts : 322
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-blt.hex
INTERRUPT ECALL
Total steps: 279
Total insts: 279
=== Warp 0 ===
Steps : 279
Insts : 279
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-bltu.hex
INTERRUPT ECALL
Total steps: 304
Total insts: 304
=== Warp 0 ===
Steps : 304
Insts : 304
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-bne.hex
INTERRUPT ECALL
Total steps: 279
Total insts: 279
=== Warp 0 ===
Steps : 279
Insts : 279
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-jal.hex
INTERRUPT ECALL
Total steps: 43
Total insts: 43
=== Warp 0 ===
Steps : 43
Insts : 43
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-jalr.hex
INTERRUPT ECALL
Total steps: 96
Total insts: 96
=== Warp 0 ===
Steps : 96
Insts : 96
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-lb.hex
INTERRUPT ECALL
Total steps: 43
Total insts: 43
=== Warp 0 ===
Steps : 43
Insts : 43
Loads : 0
Stores: 0
GRADE: FAILED 3
./riscv_tests/rv32ui-p-lbu.hex
INTERRUPT ECALL
Total steps: 43
Total insts: 43
=== Warp 0 ===
Steps : 43
Insts : 43
Loads : 0
Stores: 0
GRADE: FAILED 3
./riscv_tests/rv32ui-p-lh.hex
INTERRUPT ECALL
Total steps: 43
Total insts: 43
=== Warp 0 ===
Steps : 43
Insts : 43
Loads : 0
Stores: 0
GRADE: FAILED 3
./riscv_tests/rv32ui-p-lhu.hex
INTERRUPT ECALL
Total steps: 44
Total insts: 44
=== Warp 0 ===
Steps : 44
Insts : 44
Loads : 0
Stores: 0
GRADE: FAILED 3
./riscv_tests/rv32ui-p-lui.hex
INTERRUPT ECALL
Total steps: 53
Total insts: 53
=== Warp 0 ===
Steps : 53
Insts : 53
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-lw.hex
INTERRUPT ECALL
Total steps: 45
Total insts: 45
=== Warp 0 ===
Steps : 45
Insts : 45
Loads : 0
Stores: 0
GRADE: FAILED 3
./riscv_tests/rv32ui-p-or.hex
INTERRUPT ECALL
Total steps: 476
Total insts: 476
=== Warp 0 ===
Steps : 476
Insts : 476
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-ori.hex
INTERRUPT ECALL
Total steps: 193
Total insts: 193
=== Warp 0 ===
Steps : 193
Insts : 193
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-sb.hex
INTERRUPT ECALL
Total steps: 39
Total insts: 39
=== Warp 0 ===
Steps : 39
Insts : 39
Loads : 0
Stores: 1
GRADE: FAILED 2
./riscv_tests/rv32ui-p-sh.hex
INTERRUPT ECALL
Total steps: 39
Total insts: 39
=== Warp 0 ===
Steps : 39
Insts : 39
Loads : 0
Stores: 1
GRADE: FAILED 2
./riscv_tests/rv32ui-p-simple.hex
INTERRUPT ECALL
Total steps: 29
Total insts: 29
=== Warp 0 ===
Steps : 29
Insts : 29
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-sll.hex
INTERRUPT ECALL
Total steps: 481
Total insts: 481
=== Warp 0 ===
Steps : 481
Insts : 481
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-slli.hex
INTERRUPT ECALL
Total steps: 229
Total insts: 229
=== Warp 0 ===
Steps : 229
Insts : 229
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-slt.hex
INTERRUPT ECALL
Total steps: 447
Total insts: 447
=== Warp 0 ===
Steps : 447
Insts : 447
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-slti.hex
INTERRUPT ECALL
Total steps: 225
Total insts: 225
=== Warp 0 ===
Steps : 225
Insts : 225
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-sltiu.hex
INTERRUPT ECALL
Total steps: 225
Total insts: 225
=== Warp 0 ===
Steps : 225
Insts : 225
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-sltu.hex
INTERRUPT ECALL
Total steps: 447
Total insts: 447
=== Warp 0 ===
Steps : 447
Insts : 447
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-sra.hex
INTERRUPT ECALL
Total steps: 500
Total insts: 500
=== Warp 0 ===
Steps : 500
Insts : 500
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-srai.hex
INTERRUPT ECALL
Total steps: 244
Total insts: 244
=== Warp 0 ===
Steps : 244
Insts : 244
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-srl.hex
INTERRUPT ECALL
Total steps: 494
Total insts: 494
=== Warp 0 ===
Steps : 494
Insts : 494
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-srli.hex
INTERRUPT ECALL
Total steps: 41
Total insts: 41
=== Warp 0 ===
Steps : 41
Insts : 41
Loads : 0
Stores: 0
GRADE: FAILED 3
./riscv_tests/rv32ui-p-sub.hex
INTERRUPT ECALL
Total steps: 445
Total insts: 445
=== Warp 0 ===
Steps : 445
Insts : 445
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-sw.hex
INTERRUPT ECALL
Total steps: 41
Total insts: 41
=== Warp 0 ===
Steps : 41
Insts : 41
Loads : 0
Stores: 1
GRADE: FAILED 2
./riscv_tests/rv32ui-p-xor.hex
INTERRUPT ECALL
Total steps: 475
Total insts: 475
=== Warp 0 ===
Steps : 475
Insts : 475
Loads : 0
Stores: 0
GRADE: PASSED
./riscv_tests/rv32ui-p-xori.hex
INTERRUPT ECALL
Total steps: 195
Total insts: 195
=== Warp 0 ===
Steps : 195
Insts : 195
Loads : 0
Stores: 0
GRADE: PASSED

50
src/riscv_tests/C.ADD.elf.hex Normal file
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@ -0,0 +1,50 @@
:0200000480007A
:1000000001000100010001000100010001000100E8
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:040000058000000077
:00000001FF

45
src/riscv_tests/C.ADDI.elf.hex Normal file
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@ -0,0 +1,45 @@
:0200000480007A
:1000000001000100010001000100010001000100E8
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:040000058000000077
:00000001FF

29
src/riscv_tests/C.ADDI16SP.elf.hex Normal file
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@ -0,0 +1,29 @@
:0200000480007A
:1000000001000100010001000100010001000100E8
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:0201700000008D
:10100000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF0
:10101000FFFFFFFF000000000000000000000000D4
:040000058000000077
:00000001FF

29
src/riscv_tests/C.ADDI4SPN.elf.hex Normal file
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@ -0,0 +1,29 @@
:0200000480007A
:1000000001000100010001000100010001000100E8
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:040000058000000077
:00000001FF

50
src/riscv_tests/C.AND.elf.hex Normal file
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@ -0,0 +1,50 @@
:0200000480007A
:1000000001000100010001000100010001000100E8
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:040000058000000077
:00000001FF

45
src/riscv_tests/C.ANDI.elf.hex Normal file
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@ -0,0 +1,45 @@
:0200000480007A
:1000000001000100010001000100010001000100E8
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