mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
opae build fix
This commit is contained in:
Blaise Tine
parent
f835fabbe3
commit
3cbecfcef0
7 changed files with 65 additions and 125 deletions
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@ -13,34 +13,6 @@ vortex_afu.json
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../rtl/VX_config.v
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../rtl/VX_define.v
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../rtl/cache/VX_cache_config.vh
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../rtl/Vortex_Socket.v
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../rtl/Vortex_Cluster.v
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../rtl/Vortex.v
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../rtl/VX_front_end.v
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../rtl/VX_back_end.v
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../rtl/VX_fetch.v
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../rtl/VX_scheduler.v
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../rtl/VX_execute_unit.v
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../rtl/VX_warp.v
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../rtl/VX_icache_stage.v
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../rtl/VX_gpr_wrapper.v
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../rtl/byte_enabled_simple_dual_port_ram.v
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../rtl/VX_gpgpu_inst.v
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../rtl/VX_writeback.v
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../rtl/VX_countones.v
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../rtl/VX_csr_handler.v
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../rtl/VX_csr_pipe.v
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../rtl/VX_warp_scheduler.v
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../rtl/VX_gpr.v
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../rtl/VX_gpr_stage.v
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../rtl/VX_dmem_controller.v
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../rtl/VX_alu.v
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../rtl/VX_csr_data.v
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../rtl/VX_lsu.v
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../rtl/VX_decode.v
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../rtl/VX_inst_multiplex.v
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../rtl/VX_csr_wrapper.v
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../rtl/VX_lsu_addr_gen.v
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../rtl/interfaces/VX_exec_unit_req_if.v
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../rtl/interfaces/VX_branch_response_if.v
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@ -74,6 +46,43 @@ vortex_afu.json
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../rtl/interfaces/VX_gpu_dcache_dram_rsp_if.v
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../rtl/interfaces/VX_inst_mem_wb_if.v
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../rtl/libs/VX_priority_encoder_w_mask.v
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../rtl/libs/VX_generic_register.v
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../rtl/libs/VX_mult.v
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../rtl/libs/VX_divide.v
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../rtl/libs/VX_generic_stack.v
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../rtl/libs/VX_generic_priority_encoder.v
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../rtl/libs/VX_priority_encoder.v
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../rtl/libs/VX_generic_queue.v
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../rtl/Vortex_Socket.v
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../rtl/Vortex_Cluster.v
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../rtl/Vortex.v
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../rtl/VX_front_end.v
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../rtl/VX_back_end.v
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../rtl/VX_fetch.v
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../rtl/VX_scheduler.v
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../rtl/VX_execute_unit.v
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../rtl/VX_warp.v
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../rtl/VX_icache_stage.v
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../rtl/VX_gpr_wrapper.v
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../rtl/byte_enabled_simple_dual_port_ram.v
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../rtl/VX_gpgpu_inst.v
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../rtl/VX_writeback.v
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../rtl/VX_countones.v
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../rtl/VX_csr_pipe.v
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../rtl/VX_warp_scheduler.v
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../rtl/VX_gpr.v
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../rtl/VX_gpr_stage.v
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../rtl/VX_dmem_controller.v
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../rtl/VX_alu.v
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../rtl/VX_csr_data.v
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../rtl/VX_lsu.v
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../rtl/VX_decode.v
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../rtl/VX_inst_multiplex.v
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../rtl/VX_csr_wrapper.v
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../rtl/VX_lsu_addr_gen.v
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../rtl/pipe_regs/VX_f_d_reg.v
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../rtl/pipe_regs/VX_i_d_reg.v
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../rtl/pipe_regs/VX_d_e_reg.v
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@ -94,15 +103,6 @@ vortex_afu.json
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../rtl/cache/VX_tag_data_structure.v
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../rtl/cache/VX_prefetcher.v
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../rtl/libs/VX_priority_encoder_w_mask.v
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../rtl/libs/VX_generic_register.v
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../rtl/libs/VX_mult.v
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../rtl/libs/VX_divide.v
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../rtl/libs/VX_generic_stack.v
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../rtl/libs/VX_generic_priority_encoder.v
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../rtl/libs/VX_priority_encoder.v
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../rtl/libs/VX_generic_queue.v
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ccip_interface_reg.sv
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ccip_std_afu.sv
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vortex_afu.sv
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@ -1,69 +0,0 @@
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module VX_csr_handler (
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input wire clk,
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input wire[`CSR_ADDR_SIZE-1:0] in_decode_csr_address, // done
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VX_csr_write_request_if csr_w_req_if,
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input wire in_wb_valid,
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output wire[31:0] out_decode_csr_data // done
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);
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wire in_mem_is_csr;
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wire[`CSR_ADDR_SIZE-1:0] in_mem_csr_address;
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wire[31:0] in_mem_csr_result;
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assign in_mem_is_csr = csr_w_req_if.is_csr;
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assign in_mem_csr_address = csr_w_req_if.csr_address;
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assign in_mem_csr_result = csr_w_req_if.csr_result;
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reg [`CSR_WIDTH-1:0] csr [`NUM_CSRS-1:0];
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reg [63:0] cycle;
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reg [63:0] instret;
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reg [`CSR_ADDR_SIZE-1:0] decode_csr_address;
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wire read_cycle;
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wire read_cycleh;
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wire read_instret;
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wire read_instreth;
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initial begin
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cycle = 0;
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instret = 0;
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decode_csr_address = 0;
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end
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always @(posedge clk) begin
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cycle <= cycle + 1;
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decode_csr_address <= in_decode_csr_address;
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if (in_wb_valid) begin
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instret <= instret + 1;
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end
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end
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reg[`CSR_WIDTH-1:0] data_read;
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always @(posedge clk) begin
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if (in_mem_is_csr) begin
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csr[in_mem_csr_address] <= in_mem_csr_result[11:0];
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end
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end
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assign data_read = csr[decode_csr_address];
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assign read_cycle = decode_csr_address == `CSR_CYCL_L;
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assign read_cycleh = decode_csr_address == `CSR_CYCL_H;
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assign read_instret = decode_csr_address == `CSR_INST_L;
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assign read_instreth = decode_csr_address == `CSR_INST_H;
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assign out_decode_csr_data = read_cycle ? cycle[31:0] :
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read_cycleh ? cycle[63:32] :
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read_instret ? instret[31:0] :
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read_instreth ? instret[63:32] :
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{{20{1'b0}}, data_read};
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endmodule // VX_csr_handler
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@ -4,29 +4,10 @@
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`include "./VX_config.v"
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// `define QUEUE_FORCE_MLAB 1
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// `define SYN 1
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// `define ASIC 1
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// `define SYN_FUNC 1
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`define DEBUG_BEGIN /* verilator lint_off UNUSED */
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`define DEBUG_END /* verilator lint_on UNUSED */
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`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \
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/* verilator lint_off PINCONNECTEMPTY */ \
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/* verilator lint_off DECLFILENAME */
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`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \
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/* verilator lint_on PINCONNECTEMPTY */ \
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/* verilator lint_on DECLFILENAME */
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`define STRINGIFY(x) `"x`"
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`define STATIC_ASSERT(cond, msg) \
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generate \
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if (!(cond)) $error(msg); \
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endgenerate
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`define LOG2UP(x) ((x > 1) ? $clog2(x) : 1)
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`define NUM_CORES_PER_CLUSTER (`NUM_CORES / `NUM_CLUSTERS)
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@ -196,5 +177,25 @@
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// Bank Number of words in a line
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`define L3BANK_LINE_WORDS (`L3BANK_LINE_SIZE_BYTES / `L3WORD_SIZE_BYTES)
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//=============================================================================
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`define DEBUG_BEGIN /* verilator lint_off UNUSED */
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`define DEBUG_END /* verilator lint_on UNUSED */
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`define IGNORE_WARNINGS_BEGIN /* verilator lint_off UNUSED */ \
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/* verilator lint_off PINCONNECTEMPTY */ \
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/* verilator lint_off DECLFILENAME */
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`define IGNORE_WARNINGS_END /* verilator lint_on UNUSED */ \
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/* verilator lint_on PINCONNECTEMPTY */ \
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/* verilator lint_on DECLFILENAME */
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`define STRINGIFY(x) `"x`"
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`define STATIC_ASSERT(cond, msg) \
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generate \
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if (!(cond)) $error(msg); \
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endgenerate
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// VX_DEFINE
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`endif
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@ -1,3 +1,5 @@
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`include "VX_define.v"
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module VX_divide #(
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parameter WIDTHN=1,
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parameter WIDTHD=1,
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@ -1,3 +1,5 @@
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`include "VX_define.v"
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module VX_generic_queue #(
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parameter DATAW,
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parameter SIZE = 16
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@ -1,3 +1,5 @@
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`include "VX_define.v"
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module VX_generic_register #(
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parameter N,
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parameter PassThru = 0
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@ -1,3 +1,5 @@
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`include "VX_define.v"
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module VX_mult #(
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parameter WIDTHA=1,
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parameter WIDTHB=1,
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