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lock CSR unit only for FPU CSRs

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This commit is contained in:
Blaise Tine 2024-05-10 03:45:24 -07:00
parent c1fa2bbc38
commit 3cceed1e0b
2 changed files with 10 additions and 7 deletions
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14
hw/rtl/core/VX_csr_unit.sv
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@ -51,20 +51,22 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
wire csr_wr_enable;
wire csr_req_ready;
wire [`VX_CSR_ADDR_BITS-1:0] csr_addr = execute_if.data.imm[`VX_CSR_ADDR_BITS-1:0];
wire [`NRI_BITS-1:0] csr_imm = execute_if.data.imm[`VX_CSR_ADDR_BITS +: `NRI_BITS];
wire is_fpu_csr = (csr_addr <= `VX_CSR_FCSR);
// wait for all pending instructions for current warp to complete
assign sched_csr_if.alm_empty_wid = execute_if.data.wid;
wire no_pending_instr = sched_csr_if.alm_empty;
wire no_pending_instr = sched_csr_if.alm_empty || ~is_fpu_csr;
wire csr_req_valid = execute_if.valid && no_pending_instr;
assign execute_if.ready = csr_req_ready && no_pending_instr;
wire [`VX_CSR_ADDR_BITS-1:0] csr_addr = execute_if.data.imm[`VX_CSR_ADDR_BITS-1:0];
wire [`NRI_BITS-1:0] csr_imm = execute_if.data.imm[`VX_CSR_ADDR_BITS +: `NRI_BITS];
wire [NUM_LANES-1:0][`XLEN-1:0] rs1_data;
`UNUSED_VAR (rs1_data)
for (genvar i = 0; i < NUM_LANES; ++i) begin
assign rs1_data[i] = execute_if.data.rs1_data[i][`XLEN-1:0];
assign rs1_data[i] = execute_if.data.rs1_data[i];
end
wire csr_write_enable = (execute_if.data.op_type == `INST_SFU_CSRRW);
@ -151,7 +153,7 @@ module VX_csr_unit import VX_gpu_pkg::*; #(
end
// unlock the warp
assign sched_csr_if.unlock_warp = csr_req_valid && csr_req_ready && execute_if.data.eop;
assign sched_csr_if.unlock_warp = csr_req_valid && csr_req_ready && execute_if.data.eop && is_fpu_csr;
assign sched_csr_if.unlock_wid = execute_if.data.wid;
VX_elastic_buffer #(

3
hw/rtl/core/VX_decode.sv
View file

@ -78,6 +78,7 @@ module VX_decode #(
`UNUSED_VAR (use_rs3)
wire is_itype_sh = func3[0] && ~func3[1];
wire is_fpu_csr = (u_12 <= `VX_CSR_FCSR);
wire [19:0] ui_imm = instr[31:12];
`ifdef XLEN_64
@ -280,7 +281,7 @@ module VX_decode #(
ex_type = `EX_SFU;
op_type = `INST_OP_BITS'(`INST_SFU_CSR(func3[1:0]));
use_rd = 1;
is_wstall = 1;
is_wstall = is_fpu_csr; // only stall for FPU CSRs
use_imm = func3[2];
imm[`VX_CSR_ADDR_BITS-1:0] = u_12; // addr
`USED_IREG (rd);