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Verilator crash workaround

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This commit is contained in:
Blaise Tine 2024-07-24 16:09:27 -07:00
parent 2773b87ae5
commit 3de14dd8bf
5 changed files with 81 additions and 79 deletions
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97
hw/unittest/cache/cachesim.cpp vendored
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -31,12 +31,12 @@ static bool trace_enabled = false;
static uint64_t trace_start_time = TRACE_START_TIME;
static uint64_t trace_stop_time = TRACE_STOP_TIME;
double sc_time_stamp() {
double sc_time_stamp() {
return timestamp;
}
bool sim_trace_enabled() {
if (timestamp >= trace_start_time
if (timestamp >= trace_start_time
&& timestamp < trace_stop_time)
return true;
return trace_enabled;
@ -47,21 +47,22 @@ void sim_trace_enable(bool enable) {
}
CacheSim::CacheSim() {
// force random values for uninitialized signals
Verilated::randReset(2);
ram_ = nullptr;
// create RTL module instance
cache_ = new VVX_cache_top();
mem_rsp_active_ = false;
snp_req_active_ = false;
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
trace_ = new VerilatedVcdC;
cache_->trace(trace_, 99);
trace_->open("trace.vcd");
#endif
// force random values for uninitialized signals
Verilated::randReset(2);
ram_ = nullptr;
mem_rsp_active_ = false;
snp_req_active_ = false;
}
CacheSim::~CacheSim() {
@ -89,7 +90,7 @@ void CacheSim::reset() {
mem_rsp_vec_.clear();
//clear req and rsp vecs
}
void CacheSim::step() {
@ -118,36 +119,36 @@ void CacheSim::eval() {
void CacheSim::run(){
//#ifndef NDEBUG
//#endif
this->step();
int valid = 300;
int stalls = 20 + 10;
int valid = 300;
int stalls = 20 + 10;
while (valid > -1) {
this->step();
display_miss();
display_miss();
if(cache_->core_rsp_valid){
get_core_rsp();
}
if(!cache_->core_req_valid && !cache_->core_rsp_valid){
valid--;
valid--;
}
stalls--;
stalls--;
if (stalls == 20){
//stall_mem();
//send_snoop_req();
stalls--;
//stall_mem();
//send_snoop_req();
stalls--;
}
}
}
void CacheSim::clear_req(){
cache_->core_req_valid = 0;
cache_->core_req_valid = 0;
}
void CacheSim::send_req(core_req_t *req){
@ -157,11 +158,11 @@ void CacheSim::send_req(core_req_t *req){
}
bool CacheSim::get_core_req_ready(){
return cache_->core_req_ready;
return cache_->core_req_ready;
}
bool CacheSim::get_core_rsp_ready(){
return cache_->core_rsp_ready;
return cache_->core_rsp_ready;
}
void CacheSim::eval_reqs(){
@ -170,7 +171,7 @@ void CacheSim::eval_reqs(){
core_req_t *req = core_req_vec_.front();
cache_->core_req_valid = req->valid;
cache_->core_req_rw = req->rw;
cache_->core_req_rw = req->rw;
cache_->core_req_byteen = req->byteen;
cache_->core_req_addr[0] = req->addr[0];
@ -183,10 +184,10 @@ void CacheSim::eval_reqs(){
cache_->core_req_data[2] = req->data[2];
cache_->core_req_data[3] = req->data[3];
cache_->core_req_tag = req->tag;
cache_->core_req_tag = req->tag;
core_req_vec_.pop();
} else {
clear_req();
}
@ -209,7 +210,7 @@ void CacheSim::stall_mem(){
void CacheSim::send_snoop_req(){
/*cache_->snp_req_valid = 1;
cache_->snp_req_addr = 0x12222222;
cache_->snp_req_invalidate = 1;
cache_->snp_req_invalidate = 1;
cache_->snp_req_tag = 0xff; */
}
@ -225,15 +226,15 @@ void CacheSim::eval_mem_bus() {
if (mem_rsp_vec_[i].cycles_left > 0) {
mem_rsp_vec_[i].cycles_left -= 1;
}
if ((dequeue_index == -1)
if ((dequeue_index == -1)
&& (mem_rsp_vec_[i].cycles_left == 0)) {
dequeue_index = i;
}
}
// send memory response
// send memory response
if (mem_rsp_active_
&& cache_->mem_rsp_valid
&& cache_->mem_rsp_valid
&& cache_->mem_rsp_ready) {
mem_rsp_active_ = false;
}
@ -244,7 +245,7 @@ void CacheSim::eval_mem_bus() {
//copy data from the rsp queue to the cache module
memcpy(cache_->mem_rsp_data.data(), mem_rsp_vec_[dequeue_index].data, MEM_BLOCK_SIZE);
cache_->mem_rsp_tag = mem_rsp_vec_[dequeue_index].tag;
cache_->mem_rsp_tag = mem_rsp_vec_[dequeue_index].tag;
free(mem_rsp_vec_[dequeue_index].data); //take data out of the queue
mem_rsp_vec_.erase(mem_rsp_vec_.begin() + dequeue_index);
mem_rsp_active_ = true;
@ -256,7 +257,7 @@ void CacheSim::eval_mem_bus() {
// handle memory stalls
bool mem_stalled = false;
#ifdef ENABLE_MEM_STALLS
if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) {
if (0 == ((timestamp/2) % MEM_STALLS_MODULO)) {
mem_stalled = true;
} else
if (mem_rsp_vec_.size() >= MEM_RQ_SIZE) {
@ -272,19 +273,19 @@ void CacheSim::eval_mem_bus() {
uint64_t base_addr = (cache_->mem_req_addr * MEM_BLOCK_SIZE);
uint8_t* data = reinterpret_cast<uint8_t*>(cache_->mem_req_data.data());
for (int i = 0; i < MEM_BLOCK_SIZE; i++) {
if ((byteen >> i) & 0x1) {
if ((byteen >> i) & 0x1) {
(*ram_)[base_addr + i] = data[i];
}
}
} else {
mem_req_t mem_req;
mem_req.cycles_left = MEM_LATENCY;
mem_req.cycles_left = MEM_LATENCY;
mem_req.data = (uint8_t*)malloc(MEM_BLOCK_SIZE);
mem_req.tag = cache_->mem_req_tag;
ram_->read(cache_->mem_req_addr * MEM_BLOCK_SIZE, MEM_BLOCK_SIZE, mem_req.data);
mem_rsp_vec_.push_back(mem_req);
}
}
}
}
}
cache_->mem_req_ready = ~mem_stalled;
@ -301,15 +302,15 @@ bool CacheSim::assert_equal(unsigned int* data, unsigned int tag){
}
}
return check;
return check;
}
//DEBUG
void CacheSim::display_miss(){
//int i = (unsigned int)cache_->miss_vec;
//std::bitset<8> x(i);
//int i = (unsigned int)cache_->miss_vec;
//std::bitset<8> x(i);
//if (i) std::cout << "Miss Vec " << x << std::endl;
//std::cout << "Miss Vec 0" << cache_->miss_vec[0] << std::endl;
}
@ -322,18 +323,18 @@ void CacheSim::get_core_req(unsigned int (&rsp)[4]){
//std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl;
//std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl;
//std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
//std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
}
void CacheSim::get_core_rsp(){
//std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl;
//std::cout << cache_->genblk5_BRA_0_KET_->bank->is_fill_in_pipe<< std::endl;
char check = cache_->core_rsp_valid;
std::cout << std::hex << "core_rsp_valid: " << (unsigned int) check << std::endl;
std::cout << std::hex << "core_rsp_data[0]: " << cache_->core_rsp_data[0] << std::endl;
std::cout << std::hex << "core_rsp_data[1]: " << cache_->core_rsp_data[1] << std::endl;
std::cout << std::hex << "core_rsp_data[2]: " << cache_->core_rsp_data[2] << std::endl;
std::cout << std::hex << "core_rsp_data[3]: " << cache_->core_rsp_data[3] << std::endl;
std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl;
}
void CacheSim::get_mem_req(){
@ -341,13 +342,13 @@ void CacheSim::get_mem_req(){
std::cout << std::hex << "mem_req_rw: " << cache_->mem_req_rw << std::endl;
std::cout << std::hex << "mem_req_byteen: " << cache_->mem_req_byteen << std::endl;
std::cout << std::hex << "mem_req_addr: " << cache_->mem_req_addr << std::endl;
std::cout << std::hex << "mem_req_data: " << cache_->mem_req_data << std::endl;
std::cout << std::hex << "mem_req_data: " << cache_->mem_req_data << std::endl;
std::cout << std::hex << "mem_req_tag: " << cache_->mem_req_tag << std::endl;
}
void CacheSim::get_mem_rsp(){
std::cout << std::hex << "mem_rsp_valid: " << cache_->mem_rsp_valid << std::endl;
std::cout << std::hex << "mem_rsp_data: " << cache_->mem_rsp_data << std::endl;
std::cout << std::hex << "mem_rsp_data: " << cache_->mem_rsp_data << std::endl;
std::cout << std::hex << "mem_rsp_tag: " << cache_->mem_rsp_tag << std::endl;
std::cout << std::hex << "mem_rsp_ready: " << cache_->mem_rsp_ready << std::endl;
}

17
hw/unittest/mem_streamer/memsim.cpp
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -28,12 +28,12 @@ static uint64_t trace_start_time = 0;
static uint64_t trace_stop_time = -1ull;
static uint64_t timestamp = 0;
double sc_time_stamp() {
double sc_time_stamp() {
return timestamp;
}
bool sim_trace_enabled() {
if (timestamp >= trace_start_time
if (timestamp >= trace_start_time
&& timestamp < trace_stop_time)
return true;
return trace_enabled;
@ -61,17 +61,18 @@ int generate_rand_mask (int mask) {
}
MemSim::MemSim() {
// create RTL module instance
msu_ = new VVX_mem_scheduler();
// Enable tracing
Verilated::traceEverOn(true);
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
trace_ = new VerilatedVcdC;
cache_->trace(trace_, 99);
race_->open("trace.vcd");
#endif
// force random values for uninitialized signals
Verilated::randReset(2);
}
MemSim::~MemSim() {
@ -158,7 +159,7 @@ int main (int argc, char** argv, char** env) {
Verilated::commandArgs(argc, argv);
MemSim memsim;
RAM ram;
RAM ram;
memsim.run(&ram);

16
sim/opaesim/opae_sim.cpp
View file

@ -136,16 +136,9 @@ public:
}
int init() {
// force random values for unitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);
// turn off assertion before reset
Verilated::assertOn(false);
// create RTL module instance
device_ = new Vvortex_afu_shim();
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
trace_ = new VerilatedVcdC();
@ -153,6 +146,13 @@ public:
trace_->open("trace.vcd");
#endif
// force random values for unitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);
// turn off assertion before reset
Verilated::assertOn(false);
ram_ = new RAM(0, RAM_PAGE_SIZE);
#ifndef NDEBUG

16
sim/rtlsim/processor.cpp
View file

@ -109,16 +109,9 @@ void sim_trace_enable(bool enable) {
class Processor::Impl {
public:
Impl() : dram_sim_(MEM_CLOCK_RATIO) {
// force random values for unitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);
// turn off assertion before reset
Verilated::assertOn(false);
// create RTL module instance
device_ = new Device();
#ifdef VCD_OUTPUT
Verilated::traceEverOn(true);
trace_ = new VerilatedVcdC();
@ -126,6 +119,13 @@ public:
trace_->open("trace.vcd");
#endif
// force random values for unitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);
// turn off assertion before reset
Verilated::assertOn(false);
ram_ = nullptr;
#ifndef NDEBUG

14
sim/xrtsim/xrt_sim.cpp
View file

@ -125,13 +125,6 @@ public:
}
int init() {
// force random values for unitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);
// turn off assertion before reset
Verilated::assertOn(false);
// create RTL module instance
device_ = new Vvortex_afu_shim();
@ -141,6 +134,13 @@ public:
device_->trace(trace_, 99);
trace_->open("trace.vcd");
#endif
// force random values for unitialized signals
Verilated::randReset(VERILATOR_RESET_VALUE);
Verilated::randSeed(50);
// turn off assertion before reset
Verilated::assertOn(false);
ram_ = new RAM(0, RAM_PAGE_SIZE);