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miss output vector added to cache.v and bank.v

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This commit is contained in:
trmontgomery 2020-11-02 12:02:54 -05:00
parent e6a8df7be1
commit 40a9fd3aaf
2 changed files with 21 additions and 3 deletions
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8
hw/rtl/cache/VX_bank.v vendored
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@ -98,7 +98,10 @@ module VX_bank #(
output wire snp_rsp_valid,
output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
input wire snp_rsp_ready
input wire snp_rsp_ready,
//Misses
output wire misses
);
`ifdef DBG_CORE_REQ_INFO
@ -444,6 +447,9 @@ module VX_bank #(
.mrvq_init_ready_state_st1(mrvq_init_ready_state_st1)
);
assign misses = miss_st1;
`ifdef DBG_CORE_REQ_INFO
if (WORD_SIZE != `GLOBAL_BLOCK_SIZE) begin
assign {debug_pc_st1, debug_rd_st1, debug_wid_st1, debug_tagid_st1, debug_rw_st1, debug_byteen_st1, debug_tid_st1} = inst_meta_st1;

16
hw/rtl/cache/VX_cache.v vendored
View file

@ -118,7 +118,9 @@ module VX_cache #(
input wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_valid,
input wire [NUM_SNP_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdin_tag,
`IGNORE_WARNINGS_END
output wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_ready
output wire [NUM_SNP_REQUESTS-1:0] snp_fwdin_ready,
output wire [NUM_BANKS-1:0] miss_vec
);
`ifdef DBG_CORE_REQ_INFO
@ -162,6 +164,9 @@ module VX_cache #(
wire [NUM_BANKS-1:0][SNP_REQ_TAG_WIDTH-1:0] per_bank_snp_rsp_tag;
wire [NUM_BANKS-1:0] per_bank_snp_rsp_ready;
wire [NUM_BANKS-1:0] per_bank_miss;
assign miss_vec = per_bank_miss;
`SCOPE_SIGNALS_CACHE_BANK_SELECT
wire snp_req_valid_qual;
@ -280,6 +285,7 @@ module VX_cache #(
wire curr_bank_snp_rsp_ready;
wire curr_bank_core_req_ready;
wire curr_bank_miss;
// Core Req
assign curr_bank_core_req_valid = (per_bank_valid[i] & {NUM_REQUESTS{core_req_ready}});
@ -344,6 +350,9 @@ module VX_cache #(
assign per_bank_snp_rsp_valid[i] = curr_bank_snp_rsp_valid;
assign per_bank_snp_rsp_tag[i] = curr_bank_snp_rsp_tag;
assign curr_bank_snp_rsp_ready = per_bank_snp_rsp_ready[i];
//Misses
assign per_bank_miss[i] = curr_bank_miss;
VX_bank #(
.BANK_ID (i),
@ -415,7 +424,10 @@ module VX_cache #(
// Snoop response
.snp_rsp_valid (curr_bank_snp_rsp_valid),
.snp_rsp_tag (curr_bank_snp_rsp_tag),
.snp_rsp_ready (curr_bank_snp_rsp_ready)
.snp_rsp_ready (curr_bank_snp_rsp_ready),
//Misses
.misses (curr_bank_miss)
);
end