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OUT_BUF / OUT_REG refactoring

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This commit is contained in:
Blaise Tine 2024-02-15 04:08:50 -08:00
parent bb4c150aaf
commit 413e933b8a
37 changed files with 164 additions and 164 deletions
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6
hw/rtl/VX_cluster.sv
View file

@ -63,7 +63,7 @@ module VX_cluster import VX_gpu_pkg::*; #(
VX_gbar_arb #(
.NUM_REQS (`NUM_SOCKETS),
.OUT_REG ((`NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure
.OUT_BUF ((`NUM_SOCKETS > 2) ? 1 : 0) // bgar_unit has no backpressure
) gbar_arb (
.clk (clk),
.reset (gbar_reset),
@ -103,8 +103,8 @@ module VX_cluster import VX_gpu_pkg::*; #(
.TAG_WIDTH (L2_TAG_WIDTH),
.WRITE_ENABLE (1),
.UUID_WIDTH (`UUID_WIDTH),
.CORE_OUT_REG (2),
.MEM_OUT_REG (2),
.CORE_OUT_BUF (2),
.MEM_OUT_BUF (2),
.NC_ENABLE (1),
.PASSTHRU (!`L2_ENABLED)
) l2cache (

4
hw/rtl/VX_platform.vh
View file

@ -227,10 +227,10 @@
`RESET_RELAY_EX (dst, src, 1, 0)
// size(x): 0 -> 0, 1 -> 1, 2 -> 2, 3 -> 2, 4-> 2
`define OUT_REG_TO_EB_SIZE(out_reg) `MIN(out_reg, 2)
`define TO_OUT_BUF_SIZE(out_reg) `MIN(out_reg, 2)
// reg(x): 0 -> 0, 1 -> 1, 2 -> 0, 3 -> 1, 4 -> 2
`define OUT_REG_TO_EB_REG(out_reg) ((out_reg & 1) + ((out_reg >> 2) << 1))
`define TO_OUT_BUF_REG(out_reg) ((out_reg & 1) + ((out_reg >> 2) << 1))
`define REPEAT(n,f,s) `_REPEAT_``n(f,s)
`define _REPEAT_0(f,s)

14
hw/rtl/VX_socket.sv
View file

@ -52,7 +52,7 @@ module VX_socket import VX_gpu_pkg::*; #(
VX_gbar_arb #(
.NUM_REQS (`SOCKET_SIZE),
.OUT_REG ((`SOCKET_SIZE > 1) ? 2 : 0)
.OUT_BUF ((`SOCKET_SIZE > 1) ? 2 : 0)
) gbar_arb (
.clk (clk),
.reset (gbar_arb_reset),
@ -104,8 +104,8 @@ module VX_socket import VX_gpu_pkg::*; #(
.UUID_WIDTH (`UUID_WIDTH),
.WRITE_ENABLE (0),
.NC_ENABLE (0),
.CORE_OUT_REG (2),
.MEM_OUT_REG (2)
.CORE_OUT_BUF (2),
.MEM_OUT_BUF (2)
) icache (
`ifdef PERF_ENABLE
.cache_perf (mem_perf_tmp_if.icache),
@ -149,8 +149,8 @@ module VX_socket import VX_gpu_pkg::*; #(
.UUID_WIDTH (`UUID_WIDTH),
.WRITE_ENABLE (1),
.NC_ENABLE (1),
.CORE_OUT_REG (`SM_ENABLED ? 2 : 1),
.MEM_OUT_REG (2)
.CORE_OUT_BUF (`SM_ENABLED ? 2 : 1),
.MEM_OUT_BUF (2)
) dcache (
`ifdef PERF_ENABLE
.cache_perf (mem_perf_tmp_if.dcache),
@ -184,8 +184,8 @@ module VX_socket import VX_gpu_pkg::*; #(
.TAG_WIDTH (L1_MEM_TAG_WIDTH),
.TAG_SEL_IDX (1), // Skip 0 for NC flag
.ARBITER ("R"),
.OUT_REG_REQ (2),
.OUT_REG_RSP (2)
.REQ_OUT_BUF (2),
.RSP_OUT_BUF (2)
) mem_arb (
.clk (clk),
.reset (mem_arb_reset),

4
hw/rtl/Vortex.sv
View file

@ -78,8 +78,8 @@ module Vortex import VX_gpu_pkg::*; (
.TAG_WIDTH (L2_MEM_TAG_WIDTH),
.WRITE_ENABLE (1),
.UUID_WIDTH (`UUID_WIDTH),
.CORE_OUT_REG (2),
.MEM_OUT_REG (2),
.CORE_OUT_BUF (2),
.MEM_OUT_BUF (2),
.NC_ENABLE (1),
.PASSTHRU (!`L3_ENABLED)
) l3cache (

2
hw/rtl/Vortex_axi.sv
View file

@ -124,7 +124,7 @@ module Vortex_axi import VX_gpu_pkg::*; #(
.ADDR_WIDTH (`XLEN),
.TAG_WIDTH (`VX_MEM_TAG_WIDTH),
.NUM_BANKS (AXI_NUM_BANKS),
.OUT_REG_RSP((AXI_NUM_BANKS > 1) ? 2 : 0)
.RSP_OUT_BUF((AXI_NUM_BANKS > 1) ? 2 : 0)
) axi_adapter (
.clk (clk),
.reset (reset),

16
hw/rtl/afu/opae/vortex_afu.sv
View file

@ -482,8 +482,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.DST_ADDR_WIDTH (LMEM_ADDR_WIDTH),
.SRC_TAG_WIDTH (CCI_ADDR_WIDTH),
.DST_TAG_WIDTH (AVS_REQ_TAGW),
.OUT_REG_REQ (0),
.OUT_REG_RSP (0)
.REQ_OUT_BUF (0),
.RSP_OUT_BUF (0)
) cci_mem_adapter (
.clk (clk),
.reset (reset),
@ -530,8 +530,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.DST_ADDR_WIDTH (LMEM_ADDR_WIDTH),
.SRC_TAG_WIDTH (`VX_MEM_TAG_WIDTH),
.DST_TAG_WIDTH (AVS_REQ_TAGW),
.OUT_REG_REQ (0),
.OUT_REG_RSP (2)
.REQ_OUT_BUF (0),
.RSP_OUT_BUF (2)
) vx_mem_adapter (
.clk (clk),
.reset (reset),
@ -578,8 +578,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.ADDR_WIDTH (LMEM_ADDR_WIDTH),
.TAG_WIDTH (AVS_REQ_TAGW),
.ARBITER ("P"),
.OUT_REG_REQ (0),
.OUT_REG_RSP (0)
.REQ_OUT_BUF (0),
.RSP_OUT_BUF (0)
) mem_arb (
.clk (clk),
.reset (mem_arb_reset),
@ -598,8 +598,8 @@ module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_
.NUM_BANKS (NUM_LOCAL_MEM_BANKS),
.TAG_WIDTH (AVS_REQ_TAGW + 1),
.RD_QUEUE_SIZE (AVS_RD_QUEUE_SIZE),
.OUT_REG_REQ (2),
.OUT_REG_RSP (0)
.REQ_OUT_BUF (2),
.RSP_OUT_BUF (0)
) avs_adapter (
.clk (clk),
.reset (avs_adapter_reset),

16
hw/rtl/cache/VX_cache.sv vendored
View file

@ -49,10 +49,10 @@ module VX_cache import VX_gpu_pkg::*; #(
parameter TAG_WIDTH = UUID_WIDTH + 1,
// Core response output register
parameter CORE_OUT_REG = 0,
parameter CORE_OUT_BUF = 0,
// Memory request output register
parameter MEM_OUT_REG = 0
parameter MEM_OUT_BUF = 0
) (
// PERF
`ifdef PERF_ENABLE
@ -123,8 +123,8 @@ module VX_cache import VX_gpu_pkg::*; #(
VX_elastic_buffer #(
.DATAW (`CS_WORD_WIDTH + TAG_WIDTH),
.SIZE (CORE_REQ_BUF_ENABLE ? `OUT_REG_TO_EB_SIZE(CORE_OUT_REG) : 0),
.OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG))
.SIZE (CORE_REQ_BUF_ENABLE ? `TO_OUT_BUF_SIZE(CORE_OUT_BUF) : 0),
.OUT_REG (`TO_OUT_BUF_REG(CORE_OUT_BUF))
) core_rsp_buf (
.clk (clk),
.reset (core_rsp_reset),
@ -152,8 +152,8 @@ module VX_cache import VX_gpu_pkg::*; #(
VX_elastic_buffer #(
.DATAW (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_WIDTH),
.SIZE (MEM_REQ_BUF_ENABLE ? `OUT_REG_TO_EB_SIZE(MEM_OUT_REG) : 0),
.OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG))
.SIZE (MEM_REQ_BUF_ENABLE ? `TO_OUT_BUF_SIZE(MEM_OUT_BUF) : 0),
.OUT_REG (`TO_OUT_BUF_REG(MEM_OUT_BUF))
) mem_req_buf (
.clk (clk),
.reset (mem_req_buf_reset),
@ -346,8 +346,8 @@ module VX_cache import VX_gpu_pkg::*; #(
.WRITE_ENABLE (WRITE_ENABLE),
.UUID_WIDTH (UUID_WIDTH),
.TAG_WIDTH (TAG_WIDTH),
.CORE_OUT_REG (CORE_REQ_BUF_ENABLE ? 0 : CORE_OUT_REG),
.MEM_OUT_REG (MEM_REQ_BUF_ENABLE ? 0 : MEM_OUT_REG)
.CORE_OUT_BUF (CORE_REQ_BUF_ENABLE ? 0 : CORE_OUT_BUF),
.MEM_OUT_BUF (MEM_REQ_BUF_ENABLE ? 0 : MEM_OUT_BUF)
) bank (
.clk (clk),
.reset (bank_reset),

12
hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -47,11 +47,11 @@ module VX_cache_bank #(
// core request tag size
parameter TAG_WIDTH = UUID_WIDTH + 1,
// Core response output register
parameter CORE_OUT_REG = 0,
// Core response output buffer
parameter CORE_OUT_BUF = 0,
// Memory request output register
parameter MEM_OUT_REG = 0,
// Memory request output buffer
parameter MEM_OUT_BUF = 0,
parameter MSHR_ADDR_WIDTH = `LOG2UP(MSHR_SIZE),
parameter REQ_SEL_WIDTH = `UP(`CS_REQ_SEL_BITS),
@ -444,7 +444,7 @@ module VX_cache_bank #(
VX_elastic_buffer #(
.DATAW (TAG_WIDTH + `CS_WORD_WIDTH + REQ_SEL_WIDTH),
.SIZE (CRSQ_SIZE),
.OUT_REG (CORE_OUT_REG)
.OUT_REG (`TO_OUT_BUF_REG(CORE_OUT_BUF))
) core_rsp_queue (
.clk (clk),
.reset (crsp_reset),
@ -486,7 +486,7 @@ module VX_cache_bank #(
.DATAW (1 + `CS_LINE_ADDR_WIDTH + MSHR_ADDR_WIDTH + WORD_SIZE + WORD_SEL_WIDTH + `CS_WORD_WIDTH),
.DEPTH (MREQ_SIZE),
.ALM_FULL (MREQ_SIZE-2),
.OUT_REG (MEM_OUT_REG)
.OUT_REG (`TO_OUT_BUF_REG(MEM_OUT_BUF))
) mem_req_queue (
.clk (clk),
.reset (mreq_reset),

12
hw/rtl/cache/VX_cache_bypass.sv vendored
View file

@ -33,8 +33,8 @@ module VX_cache_bypass #(
parameter UUID_WIDTH = 0,
parameter CORE_OUT_REG = 0,
parameter MEM_OUT_REG = 0,
parameter CORE_OUT_BUF = 0,
parameter MEM_OUT_BUF = 0,
parameter CORE_DATA_WIDTH = WORD_SIZE * 8,
parameter CORE_TAG_OUT_WIDTH = CORE_TAG_IN_WIDTH - NC_ENABLE
@ -233,8 +233,8 @@ module VX_cache_bypass #(
VX_elastic_buffer #(
.DATAW (1 + LINE_SIZE + `CS_MEM_ADDR_WIDTH + `CS_LINE_WIDTH + MEM_TAG_OUT_WIDTH),
.SIZE ((!DIRECT_PASSTHRU) ? `OUT_REG_TO_EB_SIZE(MEM_OUT_REG) : 0),
.OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG))
.SIZE ((!DIRECT_PASSTHRU) ? `TO_OUT_BUF_SIZE(MEM_OUT_BUF) : 0),
.OUT_REG (`TO_OUT_BUF_REG(MEM_OUT_BUF))
) mem_req_buf (
.clk (clk),
.reset (reset),
@ -326,8 +326,8 @@ module VX_cache_bypass #(
for (genvar i = 0; i < NUM_REQS; ++i) begin
VX_elastic_buffer #(
.DATAW (`CS_WORD_WIDTH + CORE_TAG_IN_WIDTH),
.SIZE ((!DIRECT_PASSTHRU) ? `OUT_REG_TO_EB_SIZE(CORE_OUT_REG) : 0),
.OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG))
.SIZE ((!DIRECT_PASSTHRU) ? `TO_OUT_BUF_SIZE(CORE_OUT_BUF) : 0),
.OUT_REG (`TO_OUT_BUF_REG(CORE_OUT_BUF))
) core_rsp_buf (
.clk (clk),
.reset (reset),

20
hw/rtl/cache/VX_cache_cluster.sv vendored
View file

@ -55,11 +55,11 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
// enable bypass for non-cacheable addresses
parameter NC_ENABLE = 0,
// Core response output register
parameter CORE_OUT_REG = 0,
// Core response output buffer
parameter CORE_OUT_BUF = 0,
// Memory request output register
parameter MEM_OUT_REG = 0
// Memory request output buffer
parameter MEM_OUT_BUF = 0
) (
input wire clk,
input wire reset,
@ -122,8 +122,8 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.TAG_WIDTH (TAG_WIDTH),
.TAG_SEL_IDX (TAG_SEL_IDX),
.ARBITER ("R"),
.OUT_REG_REQ ((NUM_INPUTS != NUM_CACHES) ? 2 : 0),
.OUT_REG_RSP ((NUM_INPUTS != NUM_CACHES) ? 2 : 0)
.REQ_OUT_BUF ((NUM_INPUTS != NUM_CACHES) ? 2 : 0),
.RSP_OUT_BUF ((NUM_INPUTS != NUM_CACHES) ? 2 : 0)
) cache_arb (
.clk (clk),
.reset (cache_arb_reset),
@ -155,8 +155,8 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.WRITE_ENABLE (WRITE_ENABLE),
.UUID_WIDTH (UUID_WIDTH),
.TAG_WIDTH (ARB_TAG_WIDTH),
.CORE_OUT_REG ((NUM_INPUTS != NUM_CACHES) ? 2 : CORE_OUT_REG),
.MEM_OUT_REG ((NUM_CACHES > 1) ? 2 : MEM_OUT_REG),
.CORE_OUT_BUF ((NUM_INPUTS != NUM_CACHES) ? 2 : CORE_OUT_BUF),
.MEM_OUT_BUF ((NUM_CACHES > 1) ? 2 : MEM_OUT_BUF),
.NC_ENABLE (NC_ENABLE),
.PASSTHRU (PASSTHRU)
) cache_wrap (
@ -183,8 +183,8 @@ module VX_cache_cluster import VX_gpu_pkg::*; #(
.TAG_WIDTH (MEM_TAG_WIDTH),
.TAG_SEL_IDX (1), // Skip 0 for NC flag
.ARBITER ("R"),
.OUT_REG_REQ ((NUM_CACHES > 1) ? 2 : 0),
.OUT_REG_RSP ((NUM_CACHES > 1) ? 2 : 0)
.REQ_OUT_BUF ((NUM_CACHES > 1) ? 2 : 0),
.RSP_OUT_BUF ((NUM_CACHES > 1) ? 2 : 0)
) mem_arb (
.clk (clk),
.reset (mem_arb_reset),

12
hw/rtl/cache/VX_cache_top.sv vendored
View file

@ -48,11 +48,11 @@ module VX_cache_top import VX_gpu_pkg::*; #(
// core request tag size
parameter TAG_WIDTH = 16,
// Core response output register
parameter CORE_OUT_REG = 2,
// Core response output buffer
parameter CORE_OUT_BUF = 2,
// Memory request output register
parameter MEM_OUT_REG = 2,
// Memory request output buffer
parameter MEM_OUT_BUF = 2,
parameter MEM_TAG_WIDTH = `CLOG2(MSHR_SIZE) + `CLOG2(NUM_BANKS)
) (
@ -153,8 +153,8 @@ module VX_cache_top import VX_gpu_pkg::*; #(
.TAG_WIDTH (TAG_WIDTH),
.UUID_WIDTH (UUID_WIDTH),
.WRITE_ENABLE (WRITE_ENABLE),
.CORE_OUT_REG (CORE_OUT_REG),
.MEM_OUT_REG (MEM_OUT_REG)
.CORE_OUT_BUF (CORE_OUT_BUF),
.MEM_OUT_BUF (MEM_OUT_BUF)
) cache (
`ifdef PERF_ENABLE
.cache_perf (cache_perf),

16
hw/rtl/cache/VX_cache_wrap.sv vendored
View file

@ -55,11 +55,11 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
// Force bypass for all requests
parameter PASSTHRU = 0,
// Core response output register
parameter CORE_OUT_REG = 0,
// Core response output buffer
parameter CORE_OUT_BUF = 0,
// Memory request output register
parameter MEM_OUT_REG = 0
// Memory request output buffer
parameter MEM_OUT_BUF = 0
) (
input wire clk,
@ -120,8 +120,8 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
.UUID_WIDTH (UUID_WIDTH),
.CORE_OUT_REG (CORE_OUT_REG),
.MEM_OUT_REG (MEM_OUT_REG)
.CORE_OUT_BUF (CORE_OUT_BUF),
.MEM_OUT_BUF (MEM_OUT_BUF)
) cache_bypass (
.clk (clk),
.reset (nc_bypass_reset),
@ -213,8 +213,8 @@ module VX_cache_wrap import VX_gpu_pkg::*; #(
.WRITE_ENABLE (WRITE_ENABLE),
.UUID_WIDTH (UUID_WIDTH),
.TAG_WIDTH (CORE_TAG_X_WIDTH),
.CORE_OUT_REG (NC_BYPASS ? 1 : CORE_OUT_REG),
.MEM_OUT_REG (NC_BYPASS ? 1 : MEM_OUT_REG)
.CORE_OUT_BUF (NC_BYPASS ? 1 : CORE_OUT_BUF),
.MEM_OUT_BUF (NC_BYPASS ? 1 : MEM_OUT_BUF)
) cache (
.clk (clk),
.reset (cache_reset),

6
hw/rtl/core/VX_alu_unit.sv
View file

@ -45,7 +45,7 @@ module VX_alu_unit #(
VX_dispatch_unit #(
.BLOCK_SIZE (BLOCK_SIZE),
.NUM_LANES (NUM_LANES),
.OUT_REG (PARTIAL_BW ? 1 : 0)
.OUT_BUF (PARTIAL_BW ? 1 : 0)
) dispatch_unit (
.clk (clk),
.reset (dispatch_reset),
@ -127,7 +127,7 @@ module VX_alu_unit #(
VX_stream_arb #(
.NUM_INPUTS (RSP_ARB_SIZE),
.DATAW (RSP_ARB_DATAW),
.OUT_REG (PARTIAL_BW ? 1 : 3)
.OUT_BUF (PARTIAL_BW ? 1 : 3)
) rsp_arb (
.clk (clk),
.reset (reset),
@ -161,7 +161,7 @@ module VX_alu_unit #(
VX_gather_unit #(
.BLOCK_SIZE (BLOCK_SIZE),
.NUM_LANES (NUM_LANES),
.OUT_REG (PARTIAL_BW ? 3 : 0)
.OUT_BUF (PARTIAL_BW ? 3 : 0)
) gather_unit (
.clk (clk),
.reset (commit_reset),

2
hw/rtl/core/VX_commit.sv
View file

@ -56,7 +56,7 @@ module VX_commit import VX_gpu_pkg::*; #(
.NUM_INPUTS (`NUM_EX_UNITS),
.DATAW (DATAW),
.ARBITER ("R"),
.OUT_REG (1)
.OUT_BUF (1)
) commit_arb (
.clk (clk),
.reset (arb_reset),

6
hw/rtl/core/VX_dispatch_unit.sv
View file

@ -16,7 +16,7 @@
module VX_dispatch_unit import VX_gpu_pkg::*; #(
parameter BLOCK_SIZE = 1,
parameter NUM_LANES = 1,
parameter OUT_REG = 0,
parameter OUT_BUF = 0,
parameter MAX_FANOUT = `MAX_FANOUT
) (
input wire clk,
@ -220,8 +220,8 @@ module VX_dispatch_unit import VX_gpu_pkg::*; #(
VX_elastic_buffer #(
.DATAW (OUT_DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) buf_out (
.clk (clk),
.reset (buf_out_reset),

10
hw/rtl/core/VX_fpu_unit.sv
View file

@ -42,7 +42,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
VX_dispatch_unit #(
.BLOCK_SIZE (BLOCK_SIZE),
.NUM_LANES (NUM_LANES),
.OUT_REG (PARTIAL_BW ? 1 : 0)
.OUT_BUF (PARTIAL_BW ? 1 : 0)
) dispatch_unit (
.clk (clk),
.reset (dispatch_reset),
@ -119,7 +119,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
VX_fpu_dpi #(
.NUM_LANES (NUM_LANES),
.TAGW (TAG_WIDTH),
.OUT_REG (PARTIAL_BW ? 1 : 3)
.OUT_BUF (PARTIAL_BW ? 1 : 3)
) fpu_dpi (
.clk (clk),
.reset (fpu_reset),
@ -148,7 +148,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
VX_fpu_fpnew #(
.NUM_LANES (NUM_LANES),
.TAGW (TAG_WIDTH),
.OUT_REG (PARTIAL_BW ? 1 : 3)
.OUT_BUF (PARTIAL_BW ? 1 : 3)
) fpu_fpnew (
.clk (clk),
.reset (fpu_reset),
@ -177,7 +177,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
VX_fpu_dsp #(
.NUM_LANES (NUM_LANES),
.TAGW (TAG_WIDTH),
.OUT_REG (PARTIAL_BW ? 1 : 3)
.OUT_BUF (PARTIAL_BW ? 1 : 3)
) fpu_dsp (
.clk (clk),
.reset (fpu_reset),
@ -248,7 +248,7 @@ module VX_fpu_unit import VX_fpu_pkg::*; #(
VX_gather_unit #(
.BLOCK_SIZE (BLOCK_SIZE),
.NUM_LANES (NUM_LANES),
.OUT_REG (PARTIAL_BW ? 3 : 0)
.OUT_BUF (PARTIAL_BW ? 3 : 0)
) gather_unit (
.clk (clk),
.reset (commit_reset),

6
hw/rtl/core/VX_gather_unit.sv
View file

@ -16,7 +16,7 @@
module VX_gather_unit import VX_gpu_pkg::*; #(
parameter BLOCK_SIZE = 1,
parameter NUM_LANES = 1,
parameter OUT_REG = 0
parameter OUT_BUF = 0
) (
input wire clk,
input wire reset,
@ -81,8 +81,8 @@ module VX_gather_unit import VX_gpu_pkg::*; #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (commit_out_reset),

8
hw/rtl/core/VX_lsu_unit.sv
View file

@ -50,7 +50,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
VX_dispatch_unit #(
.BLOCK_SIZE (BLOCK_SIZE),
.NUM_LANES (NUM_LANES),
.OUT_REG (1)
.OUT_BUF (1)
) dispatch_unit (
.clk (clk),
.reset (dispatch_reset),
@ -338,7 +338,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
.TAG_ID_WIDTH(TAG_ID_WIDTH),
.UUID_WIDTH (`UUID_WIDTH),
.RSP_PARTIAL (1),
.MEM_OUT_REG (2)
.MEM_OUT_BUF (2)
) mem_scheduler (
.clk (clk),
.reset (mem_scheduler_reset),
@ -558,7 +558,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
VX_stream_arb #(
.NUM_INPUTS (2),
.DATAW (RSP_ARB_DATAW),
.OUT_REG (3)
.OUT_BUF (3)
) rsp_arb (
.clk (clk),
.reset (commit_reset),
@ -574,7 +574,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
VX_gather_unit #(
.BLOCK_SIZE (BLOCK_SIZE),
.NUM_LANES (NUM_LANES),
.OUT_REG (3)
.OUT_BUF (3)
) gather_unit (
.clk (clk),
.reset (commit_reset),

2
hw/rtl/core/VX_muldiv_unit.sv
View file

@ -324,7 +324,7 @@ module VX_muldiv_unit #(
VX_stream_arb #(
.NUM_INPUTS (2),
.DATAW (TAGW + (NUM_LANES * `XLEN)),
.OUT_REG (1)
.OUT_BUF (1)
) rsp_buf (
.clk (clk),
.reset (reset),

2
hw/rtl/core/VX_scoreboard.sv
View file

@ -233,7 +233,7 @@ module VX_scoreboard import VX_gpu_pkg::*; #(
.NUM_INPUTS (ISSUE_RATIO),
.DATAW (DATAW),
.ARBITER ("F"),
.OUT_REG (2)
.OUT_BUF (2)
) out_arb (
.clk (clk),
.reset (arb_reset),

6
hw/rtl/core/VX_sfu_unit.sv
View file

@ -59,7 +59,7 @@ module VX_sfu_unit import VX_gpu_pkg::*; #(
VX_dispatch_unit #(
.BLOCK_SIZE (BLOCK_SIZE),
.NUM_LANES (NUM_LANES),
.OUT_REG (1)
.OUT_BUF (1)
) dispatch_unit (
.clk (clk),
.reset (dispatch_reset),
@ -166,7 +166,7 @@ module VX_sfu_unit import VX_gpu_pkg::*; #(
.NUM_INPUTS (RSP_ARB_SIZE),
.DATAW (RSP_ARB_DATAW),
.ARBITER ("R"),
.OUT_REG (3)
.OUT_BUF (3)
) rsp_arb (
.clk (clk),
.reset (commit_reset),
@ -182,7 +182,7 @@ module VX_sfu_unit import VX_gpu_pkg::*; #(
VX_gather_unit #(
.BLOCK_SIZE (BLOCK_SIZE),
.NUM_LANES (NUM_LANES),
.OUT_REG (1)
.OUT_BUF (1)
) gather_unit (
.clk (clk),
.reset (commit_reset),

4
hw/rtl/core/VX_smem_unit.sv
View file

@ -106,8 +106,8 @@ module VX_smem_unit import VX_gpu_pkg::*; #(
.TAG_WIDTH (DCACHE_TAG_WIDTH),
.TAG_SEL_IDX (0),
.ARBITER ("P"),
.OUT_REG_REQ (2),
.OUT_REG_RSP (2)
.REQ_OUT_BUF (2),
.RSP_OUT_BUF (2)
) smem_switch (
.clk (clk),
.reset (switch_reset),

6
hw/rtl/fpu/VX_fpu_dpi.sv
View file

@ -18,7 +18,7 @@
module VX_fpu_dpi import VX_fpu_pkg::*; #(
parameter NUM_LANES = 1,
parameter TAGW = 1,
parameter OUT_REG = 0
parameter OUT_BUF = 0
) (
input wire clk,
input wire reset,
@ -445,7 +445,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
.NUM_INPUTS (2),
.DATAW (RSP_DATAW),
.ARBITER ("R"),
.OUT_REG (0)
.OUT_BUF (0)
) div_sqrt_arb (
.clk (clk),
.reset (reset),
@ -471,7 +471,7 @@ module VX_fpu_dpi import VX_fpu_pkg::*; #(
.NUM_INPUTS (NUM_FPC),
.DATAW (RSP_DATAW),
.ARBITER ("R"),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) rsp_arb (
.clk (clk),
.reset (reset),

6
hw/rtl/fpu/VX_fpu_dsp.sv
View file

@ -18,7 +18,7 @@
module VX_fpu_dsp import VX_fpu_pkg::*; #(
parameter NUM_LANES = 4,
parameter TAGW = 4,
parameter OUT_REG = 0
parameter OUT_BUF = 0
) (
input wire clk,
input wire reset,
@ -251,7 +251,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
.NUM_INPUTS (2),
.DATAW (RSP_DATAW),
.ARBITER ("R"),
.OUT_REG (0)
.OUT_BUF (0)
) div_sqrt_arb (
.clk (clk),
.reset (reset),
@ -285,7 +285,7 @@ module VX_fpu_dsp import VX_fpu_pkg::*; #(
.NUM_INPUTS (NUM_FPC),
.DATAW (RSP_DATAW + 2),
.ARBITER ("R"),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) rsp_arb (
.clk (clk),
.reset (reset),

4
hw/rtl/fpu/VX_fpu_fpnew.sv
View file

@ -269,8 +269,8 @@ module VX_fpu_fpnew
VX_elastic_buffer #(
.DATAW (RSP_DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_REG)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_REG))
) rsp_buf (
.clk (clk),
.reset (reset),

10
hw/rtl/libs/VX_avs_adapter.sv
View file

@ -21,8 +21,8 @@ module VX_avs_adapter #(
parameter NUM_BANKS = 1,
parameter TAG_WIDTH = 1,
parameter RD_QUEUE_SIZE = 1,
parameter OUT_REG_REQ = 0,
parameter OUT_REG_RSP = 0
parameter REQ_OUT_BUF = 0,
parameter RSP_OUT_BUF = 0
) (
input wire clk,
input wire reset,
@ -126,8 +126,8 @@ module VX_avs_adapter #(
VX_elastic_buffer #(
.DATAW (1 + DATA_SIZE + BANK_OFFSETW + DATA_WIDTH),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG_REQ)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG_REQ))
.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(REQ_OUT_BUF))
) req_out_buf (
.clk (clk),
.reset (reset),
@ -194,7 +194,7 @@ module VX_avs_adapter #(
.NUM_INPUTS (NUM_BANKS),
.DATAW (DATA_WIDTH + TAG_WIDTH),
.ARBITER ("R"),
.OUT_REG (OUT_REG_RSP)
.OUT_BUF (RSP_OUT_BUF)
) rsp_arb (
.clk (clk),
.reset (reset),

4
hw/rtl/libs/VX_axi_adapter.sv
View file

@ -20,7 +20,7 @@ module VX_axi_adapter #(
parameter TAG_WIDTH = 8,
parameter NUM_BANKS = 1,
parameter AVS_ADDR_WIDTH = (ADDR_WIDTH - `CLOG2(DATA_WIDTH/8)),
parameter OUT_REG_RSP = 0
parameter RSP_OUT_BUF = 0
) (
input wire clk,
input wire reset,
@ -208,7 +208,7 @@ module VX_axi_adapter #(
.NUM_INPUTS (NUM_BANKS),
.DATAW (DATA_WIDTH + TAG_WIDTH),
.ARBITER ("R"),
.OUT_REG (OUT_REG_RSP)
.OUT_BUF (RSP_OUT_BUF)
) rsp_arb (
.clk (clk),
.reset (reset),

12
hw/rtl/libs/VX_mem_adapter.sv
View file

@ -21,8 +21,8 @@ module VX_mem_adapter #(
parameter DST_ADDR_WIDTH = 1,
parameter SRC_TAG_WIDTH = 1,
parameter DST_TAG_WIDTH = 1,
parameter OUT_REG_REQ = 0,
parameter OUT_REG_RSP = 0
parameter REQ_OUT_BUF = 0,
parameter RSP_OUT_BUF = 0
) (
input wire clk,
input wire reset,
@ -208,8 +208,8 @@ module VX_mem_adapter #(
VX_elastic_buffer #(
.DATAW (1 + DST_DATA_SIZE + DST_ADDR_WIDTH + DST_DATA_WIDTH + DST_TAG_WIDTH),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG_REQ)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG_REQ))
.SIZE (`TO_OUT_BUF_SIZE(REQ_OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(REQ_OUT_BUF))
) req_out_buf (
.clk (clk),
.reset (reset),
@ -223,8 +223,8 @@ module VX_mem_adapter #(
VX_elastic_buffer #(
.DATAW (SRC_DATA_WIDTH + SRC_TAG_WIDTH),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG_RSP)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG_RSP))
.SIZE (`TO_OUT_BUF_SIZE(RSP_OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(RSP_OUT_BUF))
) rsp_in_buf (
.clk (clk),
.reset (reset),

6
hw/rtl/libs/VX_mem_rsp_sel.sv
View file

@ -19,7 +19,7 @@ module VX_mem_rsp_sel #(
parameter DATA_WIDTH = 1,
parameter TAG_WIDTH = 1,
parameter TAG_SEL_BITS = 0,
parameter OUT_REG = 0
parameter OUT_BUF = 0
) (
input wire clk,
input wire reset,
@ -84,8 +84,8 @@ module VX_mem_rsp_sel #(
VX_elastic_buffer #(
.DATAW (NUM_REQS + TAG_WIDTH + (NUM_REQS * DATA_WIDTH)),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (reset),

14
hw/rtl/libs/VX_mem_scheduler.sv
View file

@ -26,8 +26,8 @@ module VX_mem_scheduler #(
parameter UUID_WIDTH = 0, // upper section of the request tag contains the UUID
parameter QUEUE_SIZE = 8,
parameter RSP_PARTIAL = 0,
parameter CORE_OUT_REG = 0,
parameter MEM_OUT_REG = 0,
parameter CORE_OUT_BUF = 0,
parameter MEM_OUT_BUF = 0,
parameter WORD_WIDTH = WORD_SIZE * 8,
parameter LINE_WIDTH = LINE_SIZE * 8,
@ -310,8 +310,8 @@ module VX_mem_scheduler #(
for (genvar i = 0; i < MEM_CHANNELS; ++i) begin
VX_elastic_buffer #(
.DATAW (1 + LINE_SIZE + ADDR_WIDTH + LINE_WIDTH + MEM_TAGW),
.SIZE (`OUT_REG_TO_EB_SIZE(MEM_OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(MEM_OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(MEM_OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(MEM_OUT_BUF))
) mem_req_buf (
.clk (clk),
.reset (reset),
@ -336,7 +336,7 @@ module VX_mem_scheduler #(
.DATA_WIDTH (LINE_WIDTH),
.TAG_WIDTH (MEM_TAGW),
.TAG_SEL_BITS (MEM_TAGW - MEM_TAG_ID),
.OUT_REG (2)
.OUT_BUF (2)
) mem_rsp_sel (
.clk (clk),
.reset (reset),
@ -453,8 +453,8 @@ module VX_mem_scheduler #(
VX_elastic_buffer #(
.DATAW (CORE_REQS + 1 + 1 + (CORE_REQS * WORD_WIDTH) + TAG_WIDTH),
.SIZE (`OUT_REG_TO_EB_SIZE(CORE_OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(CORE_OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(CORE_OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(CORE_OUT_BUF))
) rsp_buf (
.clk (clk),
.reset (reset),

26
hw/rtl/libs/VX_stream_arb.sv
View file

@ -20,7 +20,7 @@ module VX_stream_arb #(
parameter DATAW = 1,
parameter `STRING ARBITER = "P",
parameter MAX_FANOUT = `MAX_FANOUT,
parameter OUT_REG = 0 ,
parameter OUT_BUF = 0 ,
parameter NUM_REQS = (NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS,
parameter LOG_NUM_REQS = `CLOG2(NUM_REQS),
parameter NUM_REQS_W = `UP(LOG_NUM_REQS)
@ -57,7 +57,7 @@ module VX_stream_arb #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) arb_slice (
.clk (clk),
.reset (slice_reset),
@ -101,7 +101,7 @@ module VX_stream_arb #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) fanout_slice_arb (
.clk (clk),
.reset (slice_reset),
@ -127,7 +127,7 @@ module VX_stream_arb #(
.DATAW (DATAW + LOG_NUM_REQS2),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) fanout_join_arb (
.clk (clk),
.reset (reset),
@ -180,8 +180,8 @@ module VX_stream_arb #(
VX_elastic_buffer #(
.DATAW (LOG_NUM_REQS + DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (reset),
@ -214,7 +214,7 @@ module VX_stream_arb #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) arb_slice (
.clk (clk),
.reset (slice_reset),
@ -248,7 +248,7 @@ module VX_stream_arb #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) fanout_fork_arb (
.clk (clk),
.reset (reset),
@ -275,7 +275,7 @@ module VX_stream_arb #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) fanout_slice_arb (
.clk (clk),
.reset (slice_reset),
@ -321,8 +321,8 @@ module VX_stream_arb #(
for (genvar i = 0; i < NUM_OUTPUTS; ++i) begin
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (reset),
@ -348,8 +348,8 @@ module VX_stream_arb #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset),

14
hw/rtl/libs/VX_stream_switch.sv
View file

@ -18,7 +18,7 @@ module VX_stream_switch #(
parameter NUM_INPUTS = 1,
parameter NUM_OUTPUTS = 1,
parameter DATAW = 1,
parameter OUT_REG = 0,
parameter OUT_BUF = 0,
parameter NUM_REQS = (NUM_INPUTS > NUM_OUTPUTS) ? ((NUM_INPUTS + NUM_OUTPUTS - 1) / NUM_OUTPUTS) : ((NUM_OUTPUTS + NUM_INPUTS - 1) / NUM_INPUTS),
parameter SEL_COUNT = `MIN(NUM_INPUTS, NUM_OUTPUTS),
parameter LOG_NUM_REQS = `CLOG2(NUM_REQS)
@ -78,8 +78,8 @@ module VX_stream_switch #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset),
@ -113,8 +113,8 @@ module VX_stream_switch #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset),
@ -144,8 +144,8 @@ module VX_stream_switch #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset),

14
hw/rtl/libs/VX_stream_xbar.sv
View file

@ -21,7 +21,7 @@ module VX_stream_xbar #(
parameter IN_WIDTH = `LOG2UP(NUM_INPUTS),
parameter OUT_WIDTH = `LOG2UP(NUM_OUTPUTS),
parameter ARBITER = "P",
parameter OUT_REG = 0,
parameter OUT_BUF = 0,
parameter MAX_FANOUT = `MAX_FANOUT,
parameter PERF_CTR_BITS = `CLOG2(NUM_INPUTS+1)
) (
@ -66,7 +66,7 @@ module VX_stream_xbar #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) xbar_arb (
.clk (clk),
.reset (slice_reset),
@ -94,7 +94,7 @@ module VX_stream_xbar #(
.DATAW (DATAW),
.ARBITER (ARBITER),
.MAX_FANOUT (MAX_FANOUT),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) xbar_arb (
.clk (clk),
.reset (reset),
@ -129,8 +129,8 @@ module VX_stream_xbar #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (out_buf_reset),
@ -151,8 +151,8 @@ module VX_stream_xbar #(
VX_elastic_buffer #(
.DATAW (DATAW),
.SIZE (`OUT_REG_TO_EB_SIZE(OUT_REG)),
.OUT_REG (`OUT_REG_TO_EB_REG(OUT_REG))
.SIZE (`TO_OUT_BUF_SIZE(OUT_BUF)),
.OUT_REG (`TO_OUT_BUF_REG(OUT_BUF))
) out_buf (
.clk (clk),
.reset (reset),

4
hw/rtl/mem/VX_gbar_arb.sv
View file

@ -15,7 +15,7 @@
module VX_gbar_arb #(
parameter NUM_REQS = 1,
parameter OUT_REG = 0,
parameter OUT_BUF = 0,
parameter `STRING ARBITER = "R"
) (
input wire clk,
@ -44,7 +44,7 @@ module VX_gbar_arb #(
.NUM_OUTPUTS (1),
.DATAW (REQ_DATAW),
.ARBITER (ARBITER),
.OUT_REG (OUT_REG)
.OUT_BUF (OUT_BUF)
) req_arb (
.clk (clk),
.reset (reset),

10
hw/rtl/mem/VX_mem_arb.sv
View file

@ -21,8 +21,8 @@ module VX_mem_arb #(
parameter ADDR_WIDTH = (MEM_ADDR_WIDTH-`CLOG2(DATA_SIZE)),
parameter TAG_WIDTH = 1,
parameter TAG_SEL_IDX = 0,
parameter OUT_REG_REQ = 0,
parameter OUT_REG_RSP = 0,
parameter REQ_OUT_BUF = 0,
parameter RSP_OUT_BUF = 0,
parameter `STRING ARBITER = "R"
) (
input wire clk,
@ -58,7 +58,7 @@ module VX_mem_arb #(
.NUM_OUTPUTS (NUM_OUTPUTS),
.DATAW (REQ_DATAW),
.ARBITER (ARBITER),
.OUT_REG (OUT_REG_REQ)
.OUT_BUF (REQ_OUT_BUF)
) req_arb (
.clk (clk),
.reset (reset),
@ -127,7 +127,7 @@ module VX_mem_arb #(
.NUM_INPUTS (NUM_OUTPUTS),
.NUM_OUTPUTS (NUM_INPUTS),
.DATAW (RSP_DATAW),
.OUT_REG (OUT_REG_RSP)
.OUT_BUF (RSP_OUT_BUF)
) rsp_switch (
.clk (clk),
.reset (reset),
@ -153,7 +153,7 @@ module VX_mem_arb #(
.NUM_OUTPUTS (NUM_INPUTS),
.DATAW (RSP_DATAW),
.ARBITER (ARBITER),
.OUT_REG (OUT_REG_RSP)
.OUT_BUF (RSP_OUT_BUF)
) req_arb (
.clk (clk),
.reset (reset),

4
hw/rtl/mem/VX_shared_mem.sv
View file

@ -124,7 +124,7 @@ module VX_shared_mem import VX_gpu_pkg::*; #(
.NUM_OUTPUTS (NUM_BANKS),
.DATAW (REQ_DATAW),
.PERF_CTR_BITS (`PERF_CTR_BITS),
.OUT_REG (3) // output should be registered for the data_store addressing
.OUT_BUF (3) // output should be registered for the data_store addressing
) req_xbar (
.clk (clk),
.reset (reset),
@ -208,7 +208,7 @@ module VX_shared_mem import VX_gpu_pkg::*; #(
.NUM_INPUTS (NUM_BANKS),
.NUM_OUTPUTS (NUM_REQS),
.DATAW (RSP_DATAW),
.OUT_REG (2)
.OUT_BUF (2)
) rsp_xbar (
.clk (clk),
.reset (reset),

8
hw/rtl/mem/VX_smem_switch.sv
View file

@ -19,8 +19,8 @@ module VX_smem_switch #(
parameter TAG_WIDTH = 1,
parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH,
parameter TAG_SEL_IDX = 0,
parameter OUT_REG_REQ = 0,
parameter OUT_REG_RSP = 0,
parameter REQ_OUT_BUF = 0,
parameter RSP_OUT_BUF = 0,
parameter `STRING ARBITER = "R"
) (
input wire clk,
@ -64,7 +64,7 @@ module VX_smem_switch #(
VX_stream_switch #(
.NUM_OUTPUTS (NUM_REQS),
.DATAW (REQ_DATAW),
.OUT_REG (OUT_REG_REQ)
.OUT_BUF (REQ_OUT_BUF)
) req_switch (
.clk (clk),
.reset (reset),
@ -102,7 +102,7 @@ module VX_smem_switch #(
.NUM_INPUTS (NUM_REQS),
.DATAW (RSP_DATAW),
.ARBITER (ARBITER),
.OUT_REG (OUT_REG_RSP)
.OUT_BUF (RSP_OUT_BUF)
) rsp_arb (
.clk (clk),
.reset (reset),