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master merge fixes

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This commit is contained in:
Blaise Tine 2021-05-27 14:59:03 -07:00
parent d42171d2ed
commit 432d694455
4 changed files with 6 additions and 6 deletions
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4
hw/rtl/VX_define.vh
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@ -298,8 +298,8 @@
`define DCORE_TAG_WIDTH (`DBG_CACHE_REQ_MDATAW + `LSUQ_ADDR_BITS)
`endif
// DRAM request data bits
`define DDRAM_LINE_WIDTH (`DCACHE_LINE_SIZE * 8)
// Memory request data bits
`define DMEM_LINE_WIDTH (`DCACHE_LINE_SIZE * 8)
// Memory request address bits
`define DMEM_ADDR_WIDTH (32 - `CLOG2(`DCACHE_LINE_SIZE))

4
hw/rtl/VX_lsu_unit.v
View file

@ -132,8 +132,8 @@ module VX_lsu_unit #(
wire is_req_start = (0 == req_sent_mask);
// need to hold the acquired tag index until the full request is submitted
reg [`DCORE_TAG_ID_BITS-1:0] req_tag_hold;
wire [`DCORE_TAG_ID_BITS-1:0] req_tag = is_req_start ? mbuf_waddr : req_tag_hold;
reg [`LSUQ_ADDR_BITS-1:0] req_tag_hold;
wire [`LSUQ_ADDR_BITS-1:0] req_tag = is_req_start ? mbuf_waddr : req_tag_hold;
always @(posedge clk) begin
if (mbuf_push) begin
req_tag_hold <= mbuf_waddr;

2
hw/rtl/interfaces/VX_cache_mem_req_if.v
View file

@ -1,7 +1,7 @@
`ifndef VX_CACHE_MEM_REQ_IF
`define VX_CACHE_MEM_REQ_IF
`include "../cache/VX_cache_config.vh"
`include "../cache/VX_cache_define.vh"
interface VX_cache_mem_req_if #(
parameter MEM_LINE_WIDTH = 1,

2
hw/rtl/interfaces/VX_cache_mem_rsp_if.v
View file

@ -1,7 +1,7 @@
`ifndef VX_CACHE_MEM_RSP_IF
`define VX_CACHE_MEM_RSP_IF
`include "../cache/VX_cache_config.vh"
`include "../cache/VX_cache_define.vh"
interface VX_cache_mem_rsp_if #(
parameter MEM_LINE_WIDTH = 1,