mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
removed dup address detection, replaced with coalescing
This commit is contained in:
Blaise Tine
parent
4766787478
commit
454b9e7444
2 changed files with 33 additions and 62 deletions
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@ -275,13 +275,6 @@
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`define LSU_LINE_SIZE `MIN(`NUM_LSU_LANES * (`XLEN / 8), `L1_LINE_SIZE)
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`endif
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// LSU Duplicate Address Check
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`ifdef LSU_DUP_ENABLE
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`define LSU_DUP_ENABLED 1
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`else
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`define LSU_DUP_ENABLED 0
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`endif
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// Size of LSU Core Request Queue
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`ifndef LSUQ_IN_SIZE
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`define LSUQ_IN_SIZE (2 * (`NUM_THREADS / `NUM_LSU_LANES))
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@ -38,8 +38,8 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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localparam LSUQ_SIZEW = `LOG2UP(`LSUQ_IN_SIZE);
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localparam REQ_ASHIFT = `CLOG2(WORD_SIZE);
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// tag_id = wid + PC + tmask + rd + op_type + align + is_dup + pid + pkt_addr
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localparam TAG_ID_WIDTH = `NW_WIDTH + `XLEN + NUM_LANES + `NR_BITS + `INST_LSU_BITS + (NUM_LANES * (REQ_ASHIFT)) + `LSU_DUP_ENABLED + PID_WIDTH + LSUQ_SIZEW;
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// tag_id = wid + PC + rd + op_type + align + pid + pkt_addr
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localparam TAG_ID_WIDTH = `NW_WIDTH + `XLEN + `NR_BITS + `INST_LSU_BITS + (NUM_LANES * (REQ_ASHIFT)) + PID_WIDTH + LSUQ_SIZEW;
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// tag = uuid + tag_id
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localparam TAG_WIDTH = `UUID_WIDTH + TAG_ID_WIDTH;
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@ -88,23 +88,6 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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assign full_addr[i] = execute_if[block_idx].data.rs1_data[i][`XLEN-1:0] + execute_if[block_idx].data.imm;
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end
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// detect duplicate addresses
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wire lsu_is_dup;
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`ifdef LSU_DUP_ENABLE
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if (NUM_LANES > 1) begin
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wire [NUM_LANES-2:0] addr_matches;
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for (genvar i = 0; i < (NUM_LANES-1); ++i) begin
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assign addr_matches[i] = (execute_if[block_idx].data.rs1_data[i+1] == execute_if[block_idx].data.rs1_data[0]) || ~execute_if[block_idx].data.tmask[i+1];
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end
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assign lsu_is_dup = execute_if[block_idx].data.tmask[0] && (& addr_matches);
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end else begin
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assign lsu_is_dup = 0;
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end
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`else
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assign lsu_is_dup = 0;
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`endif
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wire mem_req_empty;
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wire st_rsp_ready;
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wire lsu_valid, lsu_ready;
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@ -139,10 +122,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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assign lsu_ready = mem_req_ready
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&& (~mem_req_rw || st_rsp_ready); // writes commit directly
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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assign mem_req_mask[i] = execute_if[block_idx].data.tmask[i] && (~lsu_is_dup || (i == 0));
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end
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assign mem_req_mask = execute_if[block_idx].data.tmask;
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assign mem_req_rw = ~execute_if[block_idx].data.wb;
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wire mem_req_fire = mem_req_valid && mem_req_ready;
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@ -282,11 +262,15 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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`UNUSED_VAR (pkt_raddr)
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end
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// pack memory request tag
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assign mem_req_tag = {
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execute_if[block_idx].data.uuid, execute_if[block_idx].data.wid, execute_if[block_idx].data.tmask, execute_if[block_idx].data.PC, execute_if[block_idx].data.rd, execute_if[block_idx].data.op_type, req_align, execute_if[block_idx].data.pid, pkt_waddr
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`ifdef LSU_DUP_ENABLE
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, lsu_is_dup
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`endif
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execute_if[block_idx].data.uuid,
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execute_if[block_idx].data.wid,
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execute_if[block_idx].data.PC,
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execute_if[block_idx].data.rd,
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execute_if[block_idx].data.op_type,
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req_align, execute_if[block_idx].data.pid,
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pkt_waddr
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};
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wire [DCACHE_CHANNELS-1:0] cache_req_valid;
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@ -304,7 +288,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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`RESET_RELAY (mem_scheduler_reset, reset);
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VX_mem_scheduler #(
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.INSTANCE_ID ($sformatf("core%0d-lsu-memsched", CORE_ID)),
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.INSTANCE_ID ($sformatf("core%0d-lsu-memsched%0d", CORE_ID, block_idx)),
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.CORE_REQS (`NUM_LSU_LANES),
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.MEM_CHANNELS(DCACHE_CHANNELS),
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.WORD_SIZE (WORD_SIZE),
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@ -374,30 +358,27 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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wire [`UUID_WIDTH-1:0] rsp_uuid;
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wire [`NW_WIDTH-1:0] rsp_wid;
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wire [NUM_LANES-1:0] rsp_tmask_uq;
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wire [`XLEN-1:0] rsp_pc;
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wire [`NR_BITS-1:0] rsp_rd;
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wire [`INST_LSU_BITS-1:0] rsp_op_type;
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wire [NUM_LANES-1:0][REQ_ASHIFT-1:0] rsp_align;
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wire [PID_WIDTH-1:0] rsp_pid;
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wire rsp_is_dup;
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`ifndef LSU_DUP_ENABLE
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assign rsp_is_dup = 0;
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`endif
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assign {
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rsp_uuid, rsp_wid, rsp_tmask_uq, rsp_pc, rsp_rd, rsp_op_type, rsp_align, rsp_pid, pkt_raddr
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`ifdef LSU_DUP_ENABLE
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, rsp_is_dup
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`endif
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} = mem_rsp_tag;
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`UNUSED_VAR (rsp_op_type)
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// unpack memory response tag
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assign {
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rsp_uuid,
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rsp_wid,
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rsp_pc, rsp_rd,
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rsp_op_type,
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rsp_align,
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rsp_pid,
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pkt_raddr
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} = mem_rsp_tag;
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// load response formatting
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reg [NUM_LANES-1:0][`XLEN-1:0] rsp_data;
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wire [NUM_LANES-1:0] rsp_tmask;
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`ifdef XLEN_64
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`ifdef EXT_F_ENABLE
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@ -410,11 +391,10 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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for (genvar i = 0; i < NUM_LANES; i++) begin
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`ifdef XLEN_64
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wire [63:0] rsp_data64 = (i == 0 || rsp_is_dup) ? mem_rsp_data[0] : mem_rsp_data[i];
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wire [31:0] rsp_data32 = (i == 0 || rsp_is_dup) ? (rsp_align[0][2] ? mem_rsp_data[0][63:32] : mem_rsp_data[0][31:0]) :
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(rsp_align[i][2] ? mem_rsp_data[i][63:32] : mem_rsp_data[i][31:0]);
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wire [63:0] rsp_data64 = mem_rsp_data[i];
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wire [31:0] rsp_data32 = (rsp_align[i][2] ? mem_rsp_data[i][63:32] : mem_rsp_data[i][31:0]);
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`else
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wire [31:0] rsp_data32 = (i == 0 || rsp_is_dup) ? mem_rsp_data[0] : mem_rsp_data[i];
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wire [31:0] rsp_data32 = mem_rsp_data[i];
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`endif
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wire [15:0] rsp_data16 = rsp_align[i][1] ? rsp_data32[31:16] : rsp_data32[15:0];
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wire [7:0] rsp_data8 = rsp_align[i][0] ? rsp_data16[15:8] : rsp_data16[7:0];
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@ -435,9 +415,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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default: rsp_data[i] = 'x;
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endcase
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end
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end
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assign rsp_tmask = rsp_is_dup ? rsp_tmask_uq : mem_rsp_mask;
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end
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// load commit
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@ -449,7 +427,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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.reset (reset),
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.valid_in (mem_rsp_valid),
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.ready_in (mem_rsp_ready),
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.data_in ({rsp_uuid, rsp_wid, rsp_tmask, rsp_pc, rsp_rd, rsp_data, rsp_pid, mem_rsp_sop_pkt, mem_rsp_eop_pkt}),
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.data_in ({rsp_uuid, rsp_wid, mem_rsp_mask, rsp_pc, rsp_rd, rsp_data, rsp_pid, mem_rsp_sop_pkt, mem_rsp_eop_pkt}),
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.data_out ({commit_ld_if.data.uuid, commit_ld_if.data.wid, commit_ld_if.data.tmask, commit_ld_if.data.PC, commit_ld_if.data.rd, commit_ld_if.data.data, commit_ld_if.data.pid, commit_ld_if.data.sop, commit_ld_if.data.eop}),
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.valid_out (commit_ld_if.valid),
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.ready_out (commit_ld_if.ready)
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@ -507,24 +485,24 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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`TRACE_ARRAY1D(1, "0x%h", full_addr, NUM_LANES);
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`TRACE(1, (", tag=0x%0h, byteen=0x%0h, data=", mem_req_tag, mem_req_byteen));
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`TRACE_ARRAY1D(1, "0x%0h", mem_req_data, NUM_LANES);
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`TRACE(1, (", is_dup=%b (#%0d)\n", lsu_is_dup, execute_if[block_idx].data.uuid));
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`TRACE(1, (" (#%0d)\n", execute_if[block_idx].data.uuid));
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end else begin
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`TRACE(1, ("%d: D$%0d Rd Req: wid=%0d, PC=0x%0h, tmask=%b, addr=", $time, CORE_ID, execute_if[block_idx].data.wid, execute_if[block_idx].data.PC, mem_req_mask));
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`TRACE_ARRAY1D(1, "0x%h", full_addr, NUM_LANES);
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`TRACE(1, (", tag=0x%0h, byteen=0x%0h, rd=%0d, is_dup=%b (#%0d)\n", mem_req_tag, mem_req_byteen, execute_if[block_idx].data.rd, lsu_is_dup, execute_if[block_idx].data.uuid));
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`TRACE(1, (", tag=0x%0h, byteen=0x%0h, rd=%0d (#%0d)\n", mem_req_tag, mem_req_byteen, execute_if[block_idx].data.rd, execute_if[block_idx].data.uuid));
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end
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end
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if (mem_rsp_fire) begin
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`TRACE(1, ("%d: D$%0d Rsp: wid=%0d, PC=0x%0h, tmask=%b, tag=0x%0h, rd=%0d, sop=%b, eop=%b, data=",
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$time, CORE_ID, rsp_wid, rsp_pc, mem_rsp_mask, mem_rsp_tag, rsp_rd, mem_rsp_sop, mem_rsp_eop));
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`TRACE_ARRAY1D(1, "0x%0h", mem_rsp_data, NUM_LANES);
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`TRACE(1, (", is_dup=%b (#%0d)\n", rsp_is_dup, rsp_uuid));
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`TRACE(1, (" (#%0d)\n", rsp_uuid));
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end
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end
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`endif
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`ifdef DBG_SCOPE_LSU
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if (CORE_ID == 0) begin
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if (CORE_ID == 0 && block_idx == 0) begin
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`ifdef SCOPE
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VX_scope_tap #(
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.SCOPE_ID (3),
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@ -548,7 +526,7 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
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ila_lsu ila_lsu_inst (
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.clk (clk),
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.probe0 ({mem_req_data_0, execute_if[0].data.uuid, execute_if[0].data.wid, execute_if[0].data.PC, mem_req_mask, full_addr_0, mem_req_byteen, mem_req_rw, mem_req_ready, mem_req_valid}),
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.probe1 ({rsp_data_0, rsp_uuid, mem_rsp_eop, rsp_pc, rsp_rd, rsp_tmask, rsp_wid, mem_rsp_ready, mem_rsp_valid}),
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.probe1 ({rsp_data_0, rsp_uuid, mem_rsp_eop, rsp_pc, rsp_rd, mem_rsp_mask, rsp_wid, mem_rsp_ready, mem_rsp_valid}),
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.probe2 ({cache_bus_if.req_data.data, cache_bus_if.req_data.tag, cache_bus_if.req_data.byteen, cache_bus_if.req_data.addr, cache_bus_if.req_data.rw, cache_bus_if.req_ready, cache_bus_if.req_valid}),
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.probe3 ({cache_bus_if.rsp_data.data, cache_bus_if.rsp_data.tag, cache_bus_if.rsp_ready, cache_bus_if.rsp_valid})
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);
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