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refactoring priority encoder

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This commit is contained in:
Blaise Tine 2024-08-09 13:58:19 -07:00
parent ab21f76aed
commit 455fc8389c
3 changed files with 40 additions and 36 deletions
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14
hw/rtl/libs/VX_mem_coalescer.sv
View file

@ -125,16 +125,20 @@ module VX_mem_coalescer #(
end
for (genvar i = 0; i < OUT_REQS; ++i) begin
wire [DATA_RATIO-1:0] batch_mask = in_req_mask[i * DATA_RATIO +: DATA_RATIO] & ~processed_mask_r[i * DATA_RATIO +: DATA_RATIO];
wire [DATA_RATIO-1:0] batch_mask;
wire [DATA_RATIO_W-1:0] batch_idx;
assign batch_mask = in_req_mask[i * DATA_RATIO +: DATA_RATIO] & ~processed_mask_r[i * DATA_RATIO +: DATA_RATIO];
VX_priority_encoder #(
.N (DATA_RATIO)
) priority_encoder (
.data_in (batch_mask),
.index (batch_idx),
`UNUSED_PIN (onehot),
.valid_out (batch_valid_n[i])
.data_in (batch_mask),
.index_out (batch_idx),
`UNUSED_PIN (onehot_out),
.valid_out (batch_valid_n[i])
);
if (OUT_REQS > 1) begin
assign seed_idx[i] = {(NUM_REQS_W-DATA_RATIO_W)'(i), batch_idx};
end else begin

8
hw/rtl/libs/VX_priority_arbiter.sv
View file

@ -34,10 +34,10 @@ module VX_priority_arbiter #(
VX_priority_encoder #(
.N (NUM_REQS)
) priority_encoder (
.data_in (requests),
.index (grant_index),
.onehot (grant_onehot),
.valid_out (grant_valid)
.data_in (requests),
.index_out (grant_index),
.onehot_out (grant_onehot),
.valid_out (grant_valid)
);
end

54
hw/rtl/libs/VX_priority_encoder.sv
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -14,38 +14,38 @@
`include "VX_platform.vh"
`TRACING_OFF
module VX_priority_encoder #(
parameter N = 1,
module VX_priority_encoder #(
parameter N = 1,
parameter REVERSE = 0,
parameter MODEL = 1,
parameter LN = `LOG2UP(N)
) (
input wire [N-1:0] data_in,
output wire [N-1:0] onehot,
output wire [LN-1:0] index,
input wire [N-1:0] data_in,
output wire [N-1:0] onehot_out,
output wire [LN-1:0] index_out,
output wire valid_out
);
wire [N-1:0] reversed;
wire [N-1:0] reversed;
if (REVERSE != 0) begin
for (genvar i = 0; i < N; ++i) begin
assign reversed[N-i-1] = data_in[i];
end
end
end else begin
assign reversed = data_in;
end
if (N == 1) begin
assign onehot = reversed;
assign index = '0;
assign valid_out = reversed;
assign onehot_out = reversed;
assign index_out = '0;
assign valid_out = reversed;
end else if (N == 2) begin
assign onehot = {~reversed[0], reversed[0]};
assign index = ~reversed[0];
assign valid_out = (| reversed);
assign onehot_out = {~reversed[0], reversed[0]};
assign index_out = ~reversed[0];
assign valid_out = (| reversed);
end else if (MODEL == 1) begin
@ -64,12 +64,12 @@ module VX_priority_encoder #(
.REVERSE (1)
) lzc (
.data_in (reversed),
.data_out (index),
.data_out (index_out),
`UNUSED_PIN (valid_out)
);
assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
assign valid_out = scan_lo[N-1];
assign onehot_out = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
assign valid_out = scan_lo[N-1];
end else if (MODEL == 2) begin
@ -78,27 +78,27 @@ module VX_priority_encoder #(
`IGNORE_WARNINGS_END
assign higher_pri_regs[N-1:1] = higher_pri_regs[N-2:0] | reversed[N-2:0];
assign higher_pri_regs[0] = 1'b0;
assign onehot[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
assign onehot_out[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
VX_lzc #(
.N (N),
.REVERSE (1)
) lzc (
.data_in (reversed),
.data_out (index),
.data_out (index_out),
.valid_out (valid_out)
);
end else if (MODEL == 3) begin
assign onehot = reversed & -reversed;
assign onehot_out = reversed & -reversed;
VX_lzc #(
.N (N),
.REVERSE (1)
) lzc (
.data_in (reversed),
.data_out (index),
.data_out (index_out),
.valid_out (valid_out)
);
@ -117,13 +117,13 @@ module VX_priority_encoder #(
onehot_r[i] = 1'b1;
end
end
end
end
assign index = index_r;
assign onehot = onehot_r;
assign valid_out = (| reversed);
assign index_out = index_r;
assign onehot_out = onehot_r;
assign valid_out = (| reversed);
end
end
endmodule
`TRACING_ON