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scope fixes

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This commit is contained in:
Blaise Tine 2020-06-09 07:03:52 -07:00
parent 9575fe9a51
commit 457783322b
16 changed files with 349 additions and 155 deletions
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93
driver/opae/vortex.cpp
View file

@ -67,12 +67,19 @@ inline bool is_aligned(size_t addr, size_t alignment) {
///////////////////////////////////////////////////////////////////////////////
static int vx_scope_trace(vx_device_h hdevice) {
static int vx_scope_start(vx_device_h hdevice) {
if (nullptr == hdevice)
return -1;
vx_device_t *device = ((vx_device_t*)hdevice);
// set start delay
uint64_t delay = ((0 << 3) | 4);
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, delay));
// start execution
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN));
std::ofstream ofs("vx_scope.vcd");
ofs << "$timescale 1 ns $end" << std::endl;
@ -99,30 +106,24 @@ static int vx_scope_trace(vx_device_h hdevice) {
fwidth += 19;
ofs << "$var reg 2 14 icache_req_tag $end" << std::endl;
ofs << "$var reg 2 15 icache_rsp_tag $end" << std::endl;
ofs << "$var reg 2 16 dcache_req_tag $end" << std::endl;
ofs << "$var reg 2 17 dcache_rsp_tag $end" << std::endl;
ofs << "$var reg 29 18 dram_req_tag $end" << std::endl;
ofs << "$var reg 29 19 dram_rsp_tag $end" << std::endl;
ofs << "$var reg 32 14 icache_req_addr $end" << std::endl;
ofs << "$var reg 2 15 icache_req_tag $end" << std::endl;
ofs << "$var reg 32 16 icache_rsp_data $end" << std::endl;
ofs << "$var reg 2 17 icache_rsp_tag $end" << std::endl;
ofs << "$var reg 2 18 dcache_req_tag $end" << std::endl;
ofs << "$var reg 2 19 dcache_rsp_tag $end" << std::endl;
ofs << "$var reg 29 20 dram_req_tag $end" << std::endl;
ofs << "$var reg 29 21 dram_rsp_tag $end" << std::endl;
fwidth += 66;
fwidth += 128;
const int num_signals = 20;
#define IS_PC_SID(x) (x == 14)
ofs << "enddefinitions $end" << std::endl;
const int num_signals = 22;
uint64_t frame_width, max_frames, data_valid;
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 2));
CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &frame_width));
std::cout << "scope::frame_width=" << frame_width << std::endl;
assert((fwidth-1)== (int)frame_width);
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 3));
CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &max_frames));
std::cout << "scope::max_frames=" << max_frames << std::endl;
ofs << "enddefinitions $end" << std::endl;
do {
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 0));
@ -132,7 +133,17 @@ static int vx_scope_trace(vx_device_h hdevice) {
std::this_thread::sleep_for(std::chrono::milliseconds(1));
} while (true);
std::cout << "scope trace dump begin..." << std::endl;
std::cout << "scope trace dump begin..." << std::endl;
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 2));
CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &frame_width));
std::cout << "scope::frame_width=" << frame_width << std::endl;
assert((fwidth-1)== (int)frame_width);
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 3));
CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_DATA, &max_frames));
std::cout << "scope::max_frames=" << max_frames << std::endl;
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_SCOPE_CMD, 1));
@ -175,7 +186,12 @@ static int vx_scope_trace(vx_device_h hdevice) {
if (signal_offset == signal_width) {
signa_data[signal_width] = 0; // string null termination
ofs << 'b' << signa_data.data() << ' ' << (num_signals - signal_id) << std::endl;
int sid = (num_signals - signal_id);
if (IS_PC_SID(sid)) {
ofs << 'b' << signa_data.data() << "00 " << sid << std::endl;
} else {
ofs << 'b' << signa_data.data() << ' ' << sid << std::endl;
}
signal_offset = 0;
++signal_id;
}
@ -207,22 +223,28 @@ static int vx_scope_trace(vx_device_h hdevice) {
do {
switch (num_signals - signal_id) {
case 14:
default:
print_signal(word, 1);
break;
case 15:
case 16:
case 17:
case 18:
case 19:
print_signal(word, 2);
break;
case 5:
case 7:
print_signal(word, 4);
break;
case 18:
case 19:
case 20:
case 21:
print_signal(word, 29);
break;
default:
print_signal(word, 1);
case 14:
print_signal(word, 30);
break;
case 16:
print_signal(word, 32);
break;
}
} while ((frame_offset % 64) != 0);
@ -561,19 +583,20 @@ extern int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size) {
extern int vx_start(vx_device_h hdevice) {
if (nullptr == hdevice)
return -1;
vx_device_t *device = ((vx_device_t*)hdevice);
return -1;
// Ensure ready for new command
if (vx_ready_wait(hdevice, -1) != 0)
return -1;
// start execution
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN));
#ifdef SCOPE
vx_scope_trace(hdevice);
int ret = vx_scope_start(hdevice);
if (ret != 0)
return ret;
#else
// start execution
vx_device_t *device = ((vx_device_t*)hdevice);
CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN));
#endif
return 0;

2
driver/rtlsim/Makefile
View file

@ -19,7 +19,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \
#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2
#DEBUG=1
AFU=1
#AFU=1
CFLAGS += -fPIC

2
driver/tests/basic/common.h
View file

@ -3,6 +3,6 @@
#define DEV_MEM_SRC_ADDR 0x10000040
#define DEV_MEM_DST_ADDR 0x20000080
#define NUM_BLOCKS 64
#define NUM_BLOCKS 1
#endif

BIN
driver/tests/basic/kernel.bin
View file

Binary file not shown.

19
hw/opae/sources.txt
View file

@ -1,18 +1,17 @@
vortex_afu.json
+define+NDEBUG
+define+DBG_PRINT_CORE_ICACHE
+define+DBG_PRINT_CORE_DCACHE
+define+DBG_PRINT_CACHE_BANK
+define+DBG_PRINT_CACHE_SNP
+define+DBG_PRINT_CACHE_MSRQ
+define+DBG_PRINT_DRAM
+define+DBG_PRINT_OPAE
+define+DBG_PRINT_SCOPE
+define+SCOPE
#+define+DBG_PRINT_CORE_ICACHE
#+define+DBG_PRINT_CORE_DCACHE
#+define+DBG_PRINT_CACHE_BANK
#+define+DBG_PRINT_CACHE_SNP
#+define+DBG_PRINT_CACHE_MSRQ
#+define+DBG_PRINT_DRAM
#+define+DBG_PRINT_OPAE
#+define+DBG_PRINT_SCOPE
+incdir+.
+incdir+../rtl
+incdir+../rtl/interfaces

16
hw/opae/vortex_afu.sv
View file

@ -797,17 +797,25 @@ end
`SCOPE_SIGNALS_DECL
`STATIC_ASSERT($bits({`SCOPE_SIGNALS_LIST}) == 85, "oops!")
`SCOPE_ASSIGN(scope_dram_req_valid, vx_dram_req_valid);
`SCOPE_ASSIGN(scope_dram_req_tag, vx_dram_req_tag);
`SCOPE_ASSIGN(scope_dram_req_ready, vx_dram_req_ready);
`SCOPE_ASSIGN(scope_dram_rsp_valid, vx_dram_rsp_valid);
`SCOPE_ASSIGN(scope_dram_rsp_tag, vx_dram_rsp_tag);
`SCOPE_ASSIGN(scope_dram_rsp_ready, vx_dram_rsp_ready);
`STATIC_ASSERT($bits({`SCOPE_SIGNALS_LIST}) == 147, "oops!")
VX_scope #(
.DATAW ($bits({`SCOPE_SIGNALS_LIST})),
.BUSW (64),
.SIZE (256),
.SIZE (8192),
.IDW (19)
) scope (
.clk (clk),
.reset (SoftReset),
.start (vx_reset),
.stop (cmd_run_done),
.data_in ({`SCOPE_SIGNALS_LIST}),
.bus_in (csr_scope_cmd),
.bus_out (csr_scope_data),
@ -822,7 +830,9 @@ VX_scope #(
assign cmd_run_done = !vx_busy;
Vortex_Socket #() vx_socket (
`SCOPE_SIGNALS_ATTACH
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
.clk (clk),
.reset (vx_reset),

52
hw/rtl/VX_define.vh
View file

@ -297,7 +297,9 @@
scope_dram_rsp_valid, \
scope_dram_rsp_ready, \
scope_schedule_delay, \
scope_icache_req_addr, \
scope_icache_req_tag, \
scope_icache_rsp_data, \
scope_icache_rsp_tag, \
scope_dcache_req_tag, \
scope_dcache_rsp_tag, \
@ -306,16 +308,18 @@
`define SCOPE_SIGNALS_DECL \
wire scope_icache_req_valid; \
wire [`DCORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
wire [29:0] scope_icache_req_addr; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag; \
wire scope_icache_req_ready; \
wire scope_icache_rsp_valid; \
wire [`DCORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
wire [31:0] scope_icache_rsp_data; \
wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag; \
wire scope_icache_rsp_ready; \
wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid; \
wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag; \
wire scope_dcache_req_ready; \
wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid; \
wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag; \
wire scope_dcache_rsp_ready; \
wire scope_dram_req_valid; \
wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag; \
@ -325,48 +329,70 @@
wire scope_dram_rsp_ready; \
wire scope_schedule_delay;
`define SCOPE_SIGNALS_IO \
`define SCOPE_SIGNALS_ICACHE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_icache_req_valid, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
output wire [29:0] scope_icache_req_addr, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_req_tag, \
output wire scope_icache_req_ready, \
output wire scope_icache_rsp_valid, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \
output wire [31:0] scope_icache_rsp_data, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_icache_rsp_tag, \
output wire scope_icache_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_DCACHE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire [`DNUM_REQUESTS-1:0] scope_dcache_req_valid, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_req_tag, \
output wire scope_dcache_req_ready, \
output wire [`DNUM_REQUESTS-1:0] scope_dcache_rsp_valid, \
output wire [`ICORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
output wire [`DCORE_TAG_WIDTH-1:0] scope_dcache_rsp_tag, \
output wire scope_dcache_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_DRAM_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_dram_req_valid, \
output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_req_tag, \
output wire scope_dram_req_ready, \
output wire scope_dram_rsp_valid, \
output wire [`VX_DRAM_TAG_WIDTH-1:0] scope_dram_rsp_tag, \
output wire scope_dram_rsp_ready, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_CORE_IO \
/* verilator lint_off UNDRIVEN */ \
output wire scope_schedule_delay, \
/* verilator lint_on UNDRIVEN */
`define SCOPE_SIGNALS_ATTACH \
`define SCOPE_SIGNALS_ICACHE_ATTACH \
.scope_icache_req_valid (scope_icache_req_valid), \
.scope_icache_req_addr (scope_icache_req_addr), \
.scope_icache_req_tag (scope_icache_req_tag), \
.scope_icache_req_ready (scope_icache_req_ready), \
.scope_icache_rsp_valid (scope_icache_rsp_valid), \
.scope_icache_rsp_data (scope_icache_rsp_data), \
.scope_icache_rsp_tag (scope_icache_rsp_tag), \
.scope_icache_rsp_ready (scope_icache_rsp_ready), \
.scope_icache_rsp_ready (scope_icache_rsp_ready),
`define SCOPE_SIGNALS_DCACHE_ATTACH \
.scope_dcache_req_valid (scope_dcache_req_valid), \
.scope_dcache_req_tag (scope_dcache_req_tag), \
.scope_dcache_req_ready (scope_dcache_req_ready), \
.scope_dcache_rsp_valid (scope_dcache_rsp_valid), \
.scope_dcache_rsp_tag (scope_dcache_rsp_tag), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready), \
.scope_dcache_rsp_ready (scope_dcache_rsp_ready),
`define SCOPE_SIGNALS_DRAM_ATTACH \
.scope_dram_req_valid (scope_dram_req_valid), \
.scope_dram_req_tag (scope_dram_req_tag), \
.scope_dram_req_ready (scope_dram_req_ready), \
.scope_dram_rsp_valid (scope_dram_rsp_valid), \
.scope_dram_rsp_tag (scope_dram_rsp_tag), \
.scope_dram_rsp_ready (scope_dram_rsp_ready), \
.scope_dram_rsp_ready (scope_dram_rsp_ready),
`define SCOPE_SIGNALS_CORE_ATTACH \
.scope_schedule_delay (scope_schedule_delay),
`define SCOPE_ASSIGN(d,s) assign d = s

68
hw/rtl/VX_dram_arb.v
View file

@ -13,34 +13,34 @@ module VX_dram_arb #(
input wire reset,
// Core request
input wire [NUM_REQUESTS-1:0] core_req_valid,
input wire [NUM_REQUESTS-1:0] core_req_rw,
input wire [NUM_REQUESTS-1:0][DRAM_LINE_SIZE-1:0] core_req_byteen,
input wire [NUM_REQUESTS-1:0][DRAM_ADDR_WIDTH-1:0] core_req_addr,
input wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] core_req_data,
input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_req_tag,
output wire [NUM_REQUESTS-1:0] core_req_ready,
input wire [NUM_REQUESTS-1:0] in_dram_req_valid,
input wire [NUM_REQUESTS-1:0] in_dram_req_rw,
input wire [NUM_REQUESTS-1:0][DRAM_LINE_SIZE-1:0] in_dram_req_byteen,
input wire [NUM_REQUESTS-1:0][DRAM_ADDR_WIDTH-1:0] in_dram_req_addr,
input wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] in_dram_req_data,
input wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] in_dram_req_tag,
output wire [NUM_REQUESTS-1:0] in_dram_req_ready,
// Core response
output wire [NUM_REQUESTS-1:0] core_rsp_valid,
output wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] core_rsp_data,
output wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag,
input wire [NUM_REQUESTS-1:0] core_rsp_ready,
output wire [NUM_REQUESTS-1:0] in_dram_rsp_valid,
output wire [NUM_REQUESTS-1:0][DRAM_LINE_WIDTH-1:0] in_dram_rsp_data,
output wire [NUM_REQUESTS-1:0][CORE_TAG_WIDTH-1:0] in_dram_rsp_tag,
input wire [NUM_REQUESTS-1:0] in_dram_rsp_ready,
// DRAM request
output wire dram_req_valid,
output wire dram_req_rw,
output wire [DRAM_LINE_SIZE-1:0] dram_req_byteen,
output wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr,
output wire [DRAM_LINE_WIDTH-1:0] dram_req_data,
output wire [DRAM_TAG_WIDTH-1:0] dram_req_tag,
input wire dram_req_ready,
output wire out_dram_req_valid,
output wire out_dram_req_rw,
output wire [DRAM_LINE_SIZE-1:0] out_dram_req_byteen,
output wire [DRAM_ADDR_WIDTH-1:0] out_dram_req_addr,
output wire [DRAM_LINE_WIDTH-1:0] out_dram_req_data,
output wire [DRAM_TAG_WIDTH-1:0] out_dram_req_tag,
input wire out_dram_req_ready,
// DRAM response
input wire dram_rsp_valid,
input wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data,
input wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag,
output wire dram_rsp_ready
input wire out_dram_rsp_valid,
input wire [DRAM_LINE_WIDTH-1:0] out_dram_rsp_data,
input wire [DRAM_TAG_WIDTH-1:0] out_dram_rsp_tag,
output wire out_dram_rsp_ready
);
reg [`REQS_BITS-1:0] bus_req_sel;
@ -52,26 +52,26 @@ module VX_dram_arb #(
end
end
assign dram_req_valid = core_req_valid [bus_req_sel];
assign dram_req_rw = core_req_rw [bus_req_sel];
assign dram_req_byteen= core_req_byteen [bus_req_sel];
assign dram_req_addr = core_req_addr [bus_req_sel];
assign dram_req_data = core_req_data [bus_req_sel];
assign dram_req_tag = {core_req_tag [bus_req_sel], (`REQS_BITS)'(bus_req_sel)};
assign out_dram_req_valid = in_dram_req_valid [bus_req_sel];
assign out_dram_req_rw = in_dram_req_rw [bus_req_sel];
assign out_dram_req_byteen= in_dram_req_byteen [bus_req_sel];
assign out_dram_req_addr = in_dram_req_addr [bus_req_sel];
assign out_dram_req_data = in_dram_req_data [bus_req_sel];
assign out_dram_req_tag = {in_dram_req_tag [bus_req_sel], (`REQS_BITS)'(bus_req_sel)};
genvar i;
for (i = 0; i < NUM_REQUESTS; i++) begin
assign core_req_ready[i] = dram_req_ready && (bus_req_sel == `REQS_BITS'(i));
assign in_dram_req_ready[i] = out_dram_req_ready && (bus_req_sel == `REQS_BITS'(i));
end
wire [`REQS_BITS-1:0] bus_rsp_sel = dram_rsp_tag[`REQS_BITS-1:0];
wire [`REQS_BITS-1:0] bus_rsp_sel = out_dram_rsp_tag[`REQS_BITS-1:0];
for (i = 0; i < NUM_REQUESTS; i++) begin
assign core_rsp_valid[i] = dram_rsp_valid && (bus_rsp_sel == `REQS_BITS'(i));
assign core_rsp_data[i] = dram_rsp_data;
assign core_rsp_tag[i] = dram_rsp_tag[`REQS_BITS +: CORE_TAG_WIDTH];
assign in_dram_rsp_valid[i] = out_dram_rsp_valid && (bus_rsp_sel == `REQS_BITS'(i));
assign in_dram_rsp_data[i] = out_dram_rsp_data;
assign in_dram_rsp_tag[i] = out_dram_rsp_tag[`REQS_BITS +: CORE_TAG_WIDTH];
end
assign dram_rsp_ready = core_rsp_ready[bus_rsp_sel];
assign out_dram_rsp_ready = in_dram_rsp_ready[bus_rsp_sel];
endmodule

22
hw/rtl/VX_pipeline.v
View file

@ -3,7 +3,9 @@
module VX_pipeline #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_IO
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO
// Clock
input wire clk,
@ -53,21 +55,23 @@ module VX_pipeline #(
wire gpr_stage_delay;
wire schedule_delay;
`SCOPE_ASSIGN(scope_schedule_delay, schedule_delay);
`SCOPE_ASSIGN(scope_icache_req_valid, icache_req_valid);
`SCOPE_ASSIGN(scope_icache_req_addr, icache_req_addr);
`SCOPE_ASSIGN(scope_icache_req_tag, icache_req_tag);
`SCOPE_ASSIGN(scope_icache_req_ready, icache_req_ready);
`SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_valid);
`SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_data);
`SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_tag);
`SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_ready);
`SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_valid);
`SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_valid);
`SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_tag);
`SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_ready);
`SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_valid);
`SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_tag);
`SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_ready);
`SCOPE_ASSIGN(scope_icache_req_valid, icache_req_valid);
`SCOPE_ASSIGN(scope_icache_req_tag, icache_req_tag);
`SCOPE_ASSIGN(scope_icache_req_ready, icache_req_ready);
`SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_valid);
`SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_tag);
`SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_ready);
`SCOPE_ASSIGN(scope_schedule_delay, schedule_delay);
// Dcache
VX_cache_core_req_if #(

8
hw/rtl/Vortex.v
View file

@ -3,7 +3,9 @@
module Vortex #(
parameter CORE_ID = 0
) (
`SCOPE_SIGNALS_IO
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO
// Clock
input wire clk,
@ -165,7 +167,9 @@ module Vortex #(
VX_pipeline #(
.CORE_ID(CORE_ID)
) pipeline (
`SCOPE_SIGNALS_ATTACH
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
.clk(clk),
.reset(reset),

56
hw/rtl/Vortex_Cluster.v
View file

@ -3,7 +3,9 @@
module Vortex_Cluster #(
parameter CLUSTER_ID = 0
) (
`SCOPE_SIGNALS_IO
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO
// Clock
input wire clk,
@ -108,7 +110,9 @@ module Vortex_Cluster #(
Vortex #(
.CORE_ID(i + (CLUSTER_ID * `NUM_CORES))
) vortex_core (
`SCOPE_SIGNALS_ATTACH
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
.clk (clk),
.reset (reset),
@ -443,38 +447,38 @@ module Vortex_Cluster #(
.CORE_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.DRAM_TAG_WIDTH (`L2DRAM_TAG_WIDTH)
) dram_arb (
.clk (clk),
.reset (reset),
.clk (clk),
.reset (reset),
// Core request
.core_req_valid (arb_core_req_valid),
.core_req_rw (arb_core_req_rw),
.core_req_byteen (arb_core_req_byteen),
.core_req_addr (arb_core_req_addr),
.core_req_data (arb_core_req_data),
.core_req_tag (arb_core_req_tag),
.core_req_ready (arb_core_req_ready),
.in_dram_req_valid (arb_core_req_valid),
.in_dram_req_rw (arb_core_req_rw),
.in_dram_req_byteen (arb_core_req_byteen),
.in_dram_req_addr (arb_core_req_addr),
.in_dram_req_data (arb_core_req_data),
.in_dram_req_tag (arb_core_req_tag),
.in_dram_req_ready (arb_core_req_ready),
// Core response
.core_rsp_valid (arb_core_rsp_valid),
.core_rsp_data (arb_core_rsp_data),
.core_rsp_tag (arb_core_rsp_tag),
.core_rsp_ready (arb_core_rsp_ready),
.in_dram_rsp_valid (arb_core_rsp_valid),
.in_dram_rsp_data (arb_core_rsp_data),
.in_dram_rsp_tag (arb_core_rsp_tag),
.in_dram_rsp_ready (arb_core_rsp_ready),
// DRAM request
.dram_req_valid (dram_req_valid),
.dram_req_rw (dram_req_rw),
.dram_req_byteen (dram_req_byteen),
.dram_req_addr (dram_req_addr),
.dram_req_data (dram_req_data),
.dram_req_tag (dram_req_tag),
.dram_req_ready (dram_req_ready),
.out_dram_req_valid (dram_req_valid),
.out_dram_req_rw (dram_req_rw),
.out_dram_req_byteen (dram_req_byteen),
.out_dram_req_addr (dram_req_addr),
.out_dram_req_data (dram_req_data),
.out_dram_req_tag (dram_req_tag),
.out_dram_req_ready (dram_req_ready),
// DRAM response
.dram_rsp_valid (dram_rsp_valid),
.dram_rsp_tag (dram_rsp_tag),
.dram_rsp_data (dram_rsp_data),
.dram_rsp_ready (dram_rsp_ready)
.out_dram_rsp_valid (dram_rsp_valid),
.out_dram_rsp_tag (dram_rsp_tag),
.out_dram_rsp_data (dram_rsp_data),
.out_dram_rsp_ready (dram_rsp_ready)
);
end

19
hw/rtl/Vortex_Socket.v
View file

@ -1,7 +1,9 @@
`include "VX_define.vh"
module Vortex_Socket (
`SCOPE_SIGNALS_IO
`SCOPE_SIGNALS_ICACHE_IO
`SCOPE_SIGNALS_DCACHE_IO
`SCOPE_SIGNALS_CORE_IO
// Clock
input wire clk,
@ -52,19 +54,14 @@ module Vortex_Socket (
output wire busy,
output wire ebreak
);
`SCOPE_ASSIGN(scope_dram_req_valid, dram_req_valid);
`SCOPE_ASSIGN(scope_dram_req_tag, dram_req_tag);
`SCOPE_ASSIGN(scope_dram_req_ready, dram_req_ready);
`SCOPE_ASSIGN(scope_dram_rsp_valid, dram_rsp_valid);
`SCOPE_ASSIGN(scope_dram_rsp_tag, dram_req_tag);
`SCOPE_ASSIGN(scope_dram_rsp_ready, dram_rsp_ready);
if (`NUM_CLUSTERS == 1) begin
Vortex_Cluster #(
.CLUSTER_ID(`L3CACHE_ID)
) Vortex_Cluster (
`SCOPE_SIGNALS_ATTACH
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
.clk (clk),
.reset (reset),
@ -151,7 +148,9 @@ module Vortex_Socket (
Vortex_Cluster #(
.CLUSTER_ID(i)
) Vortex_Cluster (
`SCOPE_SIGNALS_ATTACH
`SCOPE_SIGNALS_ICACHE_ATTACH
`SCOPE_SIGNALS_DCACHE_ATTACH
`SCOPE_SIGNALS_CORE_ATTACH
.clk (clk),
.reset (reset),

27
hw/rtl/libs/VX_scope.v
View file

@ -9,6 +9,7 @@ module VX_scope #(
input wire clk,
input wire reset,
input wire start,
input wire stop,
input wire [DATAW-1:0] data_in,
input wire [BUSW-1:0] bus_in,
output reg [BUSW-1:0] bus_out,
@ -21,7 +22,7 @@ module VX_scope #(
CMD_GET_VALID,
CMD_GET_DATA,
CMD_GET_WIDTH,
CMD_GET_DEPTH,
CMD_GET_COUNT,
CMD_SET_DELAY,
CMD_SET_DURATION,
CMD_SET_RESERVED1,
@ -32,7 +33,7 @@ module VX_scope #(
GET_VALID,
GET_DATA,
GET_WIDTH,
GET_DEPTH
GET_COUNT
} cmd_get_t;
reg [DATAW-1:0] data_store [SIZE-1:0];
@ -78,7 +79,7 @@ module VX_scope #(
CMD_GET_VALID,
CMD_GET_DATA,
CMD_GET_WIDTH,
CMD_GET_DEPTH: out_cmd <= $bits(out_cmd)'(cmd_type);
CMD_GET_COUNT: out_cmd <= $bits(out_cmd)'(cmd_type);
CMD_SET_DELAY: delay_val <= $bits(delay_val)'(cmd_data);
CMD_SET_DURATION: waddr_end <= $bits(waddr)'(cmd_data);
default:;
@ -101,7 +102,8 @@ module VX_scope #(
if (start_wait) begin
delay_cntr <= delay_cntr - 1;
if (1 == delay_cntr) begin
if (1 == delay_cntr) begin
$display("%t: scope-state: recording", $time);
start_wait <= 0;
recording <= 1;
delta <= 0;
@ -125,10 +127,13 @@ module VX_scope #(
waddr <= waddr + 1;
end
if (waddr == waddr_end) begin
if (stop
|| (waddr == waddr_end)) begin
$display("%t: scope-state: data_valid, waddr=%0d", $time, waddr);
waddr <= waddr; // keep last written address
recording <= 0;
data_valid <= 1;
read_delta <= DELTA_ENABLE;
read_delta <= DELTA_ENABLE;
end
end
@ -145,14 +150,14 @@ module VX_scope #(
raddr <= raddr + 1;
read_offset <= 0;
read_delta <= DELTA_ENABLE;
if (raddr == waddr_end) begin
if (raddr == waddr) begin
data_valid <= 0;
end
end
end else begin
raddr <= raddr + 1;
read_delta <= DELTA_ENABLE;
if (raddr == waddr_end) begin
if (raddr == waddr) begin
data_valid <= 0;
end
end
@ -165,7 +170,7 @@ module VX_scope #(
case (out_cmd)
GET_VALID : bus_out = BUSW'(data_valid);
GET_WIDTH : bus_out = BUSW'(DATAW);
GET_DEPTH : bus_out = BUSW'(waddr_end) + BUSW'(1);
GET_COUNT : bus_out = BUSW'(waddr) + BUSW'(1);
default : bus_out = read_delta ? (BUSW)'(delta_store[raddr]) : (BUSW)'(data_store[raddr] >> read_offset);
endcase
end
@ -175,8 +180,8 @@ module VX_scope #(
if (bus_read) begin
$display("%t: scope-read: cmd=%0d, out=0x%0h, addr=%0d, off=%0d", $time, out_cmd, bus_out, raddr, read_offset);
end
if (DELTA_ENABLE && recording && (trigger_id != prev_id) && (delta != 0)) begin
$display("%t: scope-write: waddr=%0d, delta=%0d", $time, waddr, delta);
if (bus_write) begin
$display("%t: scope-write: cmd=%0d, value=%0d", $time, cmd_type, cmd_data);
end
end
`endif

70
hw/syn/quartus/pipeline/Makefile Normal file
View file

@ -0,0 +1,70 @@
PROJECT = VX_pipeline
TOP_LEVEL_ENTITY = VX_pipeline
SRC_FILE = VX_pipeline.v
PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
# Part, Family
FAMILY = "Arria 10"
DEVICE = 10AX115N3F40E2SG
# Executable Configuration
SYN_ARGS = --parallel --read_settings_files=on
FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
ASM_ARGS =
STA_ARGS = --do_report_timing
# Build targets
all: $(PROJECT).sta.rpt
syn: $(PROJECT).syn.rpt
fit: $(PROJECT).fit.rpt
asm: $(PROJECT).asm.rpt
sta: $(PROJECT).sta.rpt
smart: smart.log
# Target implementations
STAMP = echo done >
$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES)
quartus_syn $(PROJECT) $(SYN_ARGS)
$(STAMP) fit.chg
$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
quartus_fit $(PROJECT) $(FIT_ARGS)
$(STAMP) asm.chg
$(STAMP) sta.chg
$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
quartus_asm $(PROJECT) $(ASM_ARGS)
$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
quartus_sta $(PROJECT) $(STA_ARGS)
smart.log: $(PROJECT_FILES)
quartus_sh --determine_smart_action $(PROJECT) > smart.log
# Project initialization
$(PROJECT_FILES):
quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
syn.chg:
$(STAMP) syn.chg
fit.chg:
$(STAMP) fit.chg
sta.chg:
$(STAMP) sta.chg
asm.chg:
$(STAMP) asm.chg
program: $(PROJECT).sof
quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
clean:
rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

9
hw/syn/quartus/pipeline/project.sdc Normal file
View file

@ -0,0 +1,9 @@
set_time_format -unit ns -decimal_places 3
create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty

41
hw/syn/quartus/pipeline/project.tcl Normal file
View file

@ -0,0 +1,41 @@
load_package flow
package require cmdline
set options { \
{ "project.arg" "" "Project name" } \
{ "family.arg" "" "Device family name" } \
{ "device.arg" "" "Device name" } \
{ "top.arg" "" "Top level module" } \
{ "sdc.arg" "" "Timing Design Constraints file" } \
{ "src.arg" "" "Verilog source file" } \
{ "inc.arg" "." "Include path" } \
}
array set opts [::cmdline::getoptions quartus(args) $options]
project_new $opts(project) -overwrite
set_global_assignment -name FAMILY $opts(family)
set_global_assignment -name DEVICE $opts(device)
set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
set_global_assignment -name VERILOG_FILE $opts(src)
set_global_assignment -name SEARCH_PATH $opts(inc)
set_global_assignment -name SDC_FILE $opts(sdc)
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
proc make_all_pins_virtual {} {
execute_module -tool map
set name_ids [get_names -filter * -node_type pin]
foreach_in_collection name_id $name_ids {
set pin_name [get_name_info -info full_path $name_id]
post_message "Making VIRTUAL_PIN assignment to $pin_name"
set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
}
export_assignments
}
make_all_pins_virtual
project_close