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refactor interfaces

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This commit is contained in:
Blaise Tine 2020-04-16 10:40:40 -04:00
parent 31f906f9fd
commit 460aabf6b1
33 changed files with 146 additions and 240 deletions
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8
hw/rtl/interfaces/VX_branch_response_inter.v
View file

@ -1,18 +1,14 @@
`ifndef VX_BRANCH_RSP
`define VX_BRANCH_RSP
`include "../VX_define.vh"
`ifndef VX_BRANCH_RSP
`define VX_BRANCH_RSP
interface VX_branch_response_inter ();
wire valid_branch;
wire branch_dir;
wire[31:0] branch_dest;
wire[`NW_BITS-1:0] branch_warp_num;
endinterface
`endif

8
hw/rtl/interfaces/VX_csr_req_inter.v
View file

@ -1,10 +1,8 @@
`ifndef VX_CSR_REQ
`define VX_CSR_REQ
`include "../VX_define.vh"
`ifndef VX_CSR_REQ
`define VX_CSR_REQ
interface VX_csr_req_inter ();
wire[`NUM_THREADS-1:0] valid;
@ -17,8 +15,6 @@ interface VX_csr_req_inter ();
wire csr_immed;
wire[31:0] csr_mask;
endinterface
`endif

6
hw/rtl/interfaces/VX_csr_wb_inter.v
View file

@ -1,10 +1,8 @@
`ifndef VX_CSR_WB_REQ
`define VX_CSR_WB_REQ
`include "../VX_define.vh"
`ifndef VX_CSR_WB_REQ
`define VX_CSR_WB_REQ
interface VX_csr_wb_inter ();
wire[`NUM_THREADS-1:0] valid;

7
hw/rtl/interfaces/VX_dcache_request_inter.v
View file

@ -1,10 +1,8 @@
`ifndef VX_DCACHE_REQ
`define VX_DCACHE_REQ
`include "../VX_define.vh"
`ifndef VX_DCACHE_REQ
`define VX_DCACHE_REQ
interface VX_dcache_request_inter ();
wire[`NUM_THREADS-1:0][31:0] out_cache_driver_in_address;
@ -15,5 +13,4 @@ interface VX_dcache_request_inter ();
endinterface
`endif

9
hw/rtl/interfaces/VX_dcache_response_inter.v
View file

@ -1,16 +1,13 @@
`ifndef VX_DCACHE_RSP
`define VX_DCACHE_RSP
`include "../VX_define.vh"
`ifndef VX_DCACHE_RSP
`define VX_DCACHE_RSP
interface VX_dcache_response_inter ();
wire[`NUM_THREADS-1:0][31:0] in_cache_driver_out_data;
wire delay;
wire delay;
endinterface
`endif

7
hw/rtl/interfaces/VX_dram_req_rsp_inter.v
View file

@ -1,10 +1,9 @@
`include "../VX_define.vh"
`ifndef VX_DRAM_REQ_RSP_INTER
`define VX_DRAM_REQ_RSP_INTER
`include "../VX_define.vh"
interface VX_dram_req_rsp_inter #(
parameter NUM_BANKS = 8,
parameter NUM_WORDS_PER_BLOCK = 4) ();
@ -20,8 +19,6 @@ interface VX_dram_req_rsp_inter #(
wire[NUM_BANKS - 1:0][NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
wire i_m_ready;
endinterface
`endif

16
hw/rtl/interfaces/VX_exec_unit_req_inter.v
View file

@ -1,17 +1,15 @@
`ifndef VX_EXE_UNIT_REQ_INTER
`define VX_EXE_UNIT_REQ_INTER
`include "../VX_define.vh"
`ifndef VX_EXE_UNIT_REQ_INTER
`define VX_EXE_UNIT_REQ_INTER
interface VX_exec_unit_req_inter ();
// Meta
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[31:0] curr_PC;
wire[31:0] PC_next;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[31:0] curr_PC;
wire[31:0] PC_next;
// Write Back Info
wire[4:0] rd;
@ -45,7 +43,7 @@ interface VX_exec_unit_req_inter ();
wire[11:0] csr_address;
wire csr_immed;
wire[31:0] csr_mask;
endinterface
`endif

10
hw/rtl/interfaces/VX_frE_to_bckE_req_inter.v
View file

@ -1,10 +1,8 @@
`ifndef VX_FrE_to_BE_INTER
`define VX_FrE_to_BE_INTER
`include "VX_define.vh"
`ifndef VX_FrE_to_BE_INTER
`define VX_FrE_to_BE_INTER
interface VX_frE_to_bckE_req_inter ();
wire[11:0] csr_address;
@ -30,7 +28,7 @@ interface VX_frE_to_bckE_req_inter ();
wire jal;
wire[31:0] jal_offset;
wire[31:0] PC_next;
wire[`NUM_THREADS-1:0] valid;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
// GPGPU stuff
@ -39,8 +37,6 @@ interface VX_frE_to_bckE_req_inter ();
wire is_split;
wire is_barrier;
endinterface
`endif

20
hw/rtl/interfaces/VX_gpr_clone_inter.v
View file

@ -1,18 +1,16 @@
`ifndef VX_GPR_CLONE_INTER
`define VX_GPR_CLONE_INTER
`include "../VX_define.vh"
`ifndef VX_GPR_CLONE_INTER
`define VX_GPR_CLONE_INTER
interface VX_gpr_clone_inter ();
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
/* verilator lint_off UNUSED */
wire is_clone;
wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface
`endif

10
hw/rtl/interfaces/VX_gpr_data_inter.v
View file

@ -1,14 +1,14 @@
`ifndef VX_gpr_data_INTER
`define VX_gpr_data_INTER
`include "../VX_define.vh"
`ifndef VX_gpr_data_INTER
`define VX_gpr_data_INTER
interface VX_gpr_data_inter ();
wire[`NUM_THREADS-1:0][31:0] a_reg_data;
wire[`NUM_THREADS-1:0][31:0] b_reg_data;
endinterface
`endif

7
hw/rtl/interfaces/VX_gpr_jal_inter.v
View file

@ -1,14 +1,13 @@
`include "../VX_define.vh"
`ifndef VX_GPR_JAL_INTER
`define VX_GPR_JAL_INTER
`include "../VX_define.vh"
interface VX_gpr_jal_inter ();
wire is_jal;
wire[31:0] curr_PC;
endinterface
`endif

11
hw/rtl/interfaces/VX_gpr_read_inter.v
View file

@ -1,17 +1,14 @@
`include "../VX_define.vh"
`ifndef VX_GPR_READ
`define VX_GPR_READ
`include "../VX_define.vh"
interface VX_gpr_read_inter ();
wire[4:0] rs1;
wire[4:0] rs2;
wire[`NW_BITS-1:0] warp_num;
wire[4:0] rs1;
wire[4:0] rs2;
wire[`NW_BITS-1:0] warp_num;
endinterface
`endif

9
hw/rtl/interfaces/VX_gpr_wspawn_inter.v
View file

@ -1,18 +1,15 @@
`include "../VX_define.vh"
`ifndef VX_GPR_WSPAWN_INTER
`define VX_GPR_WSPAWN_INTER
`include "../VX_define.vh"
interface VX_gpr_wspawn_inter ();
/* verilator lint_off UNUSED */
wire is_wspawn;
wire[`NW_BITS-1:0] which_wspawn;
wire is_wspawn;
wire[`NW_BITS-1:0] which_wspawn;
// wire[`NW_BITS-1:0] warp_num;
/* verilator lint_on UNUSED */
endinterface
`endif

7
hw/rtl/interfaces/VX_gpu_dcache_dram_req_inter.v
View file

@ -1,11 +1,10 @@
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_DRAM_DCACHE_REQ
`define VX_GPU_DRAM_DCACHE_REQ
`include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_dcache_dram_req_inter
#(
parameter BANK_LINE_WORDS = 2
@ -27,11 +26,9 @@ interface VX_gpu_dcache_dram_req_inter
// DRAM Cache can't accept response
wire dram_fill_accept;
// DRAM Cache can't accept request
wire dram_req_delay;
endinterface
`endif

9
hw/rtl/interfaces/VX_gpu_dcache_dram_res_inter.v
View file

@ -1,12 +1,8 @@
`ifndef VX_GPU_DRAM_DCACHE_RES
`define VX_GPU_DRAM_DCACHE_RES
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_DRAM_DCACHE_RES
`define VX_GPU_DRAM_DCACHE_RES
interface VX_gpu_dcache_dram_res_inter
#(
parameter BANK_LINE_WORDS = 2
@ -19,5 +15,4 @@ interface VX_gpu_dcache_dram_res_inter
endinterface
`endif

9
hw/rtl/interfaces/VX_gpu_dcache_req_inter.v
View file

@ -1,14 +1,13 @@
`ifndef VX_GPU_DCACHE_REQ
`define VX_GPU_DCACHE_REQ
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_DCACHE_REQ
`define VX_GPU_DCACHE_REQ
interface VX_gpu_dcache_req_inter
#(
parameter NUM_REQUESTS = 32
parameter NUM_REQUESTS = 32
)
();

11
hw/rtl/interfaces/VX_gpu_dcache_res_inter.v
View file

@ -1,16 +1,12 @@
`ifndef VX_GPU_DCACHE_RES
`define VX_GPU_DCACHE_RES
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_DCACHE_RES
`define VX_GPU_DCACHE_RES
interface VX_gpu_dcache_res_inter
#(
parameter NUM_REQUESTS = 32
)
();
) ();
// Cache WB
wire [NUM_REQUESTS-1:0] core_wb_valid;
@ -25,5 +21,4 @@ interface VX_gpu_dcache_res_inter
endinterface
`endif

13
hw/rtl/interfaces/VX_gpu_dcache_snp_req_inter.v
View file

@ -1,18 +1,13 @@
`ifndef VX_GPU_SNP_REQ
`define VX_GPU_SNP_REQ
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_SNP_REQ
`define VX_GPU_SNP_REQ
interface VX_gpu_dcache_snp_req_inter ();
// Snoop Req
wire snp_req;
wire [31:0] snp_req_addr;
wire snp_req;
wire [31:0] snp_req_addr;
endinterface
`endif

24
hw/rtl/interfaces/VX_gpu_inst_req_inter.v
View file

@ -1,27 +1,23 @@
`include "../VX_define.vh"
`ifndef VX_GPU_INST_REQ_IN
`define VX_GPU_INST_REQ_IN
`include "../VX_define.vh"
interface VX_gpu_inst_req_inter();
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire is_wspawn;
wire is_tmc;
wire is_split;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire is_wspawn;
wire is_tmc;
wire is_split;
wire is_barrier;
wire is_barrier;
wire[31:0] pc_next;
wire[31:0] pc_next;
wire[`NUM_THREADS-1:0][31:0] a_reg_data;
wire[31:0] rd2;
wire[31:0] rd2;
endinterface
`endif

9
hw/rtl/interfaces/VX_gpu_snp_req_rsp.v
View file

@ -1,11 +1,9 @@
`include "../generic_cache/VX_cache_config.vh"
`ifndef VX_GPU_SNP_REQ_RSP
`define VX_GPU_SNP_REQ_RSP
interface VX_gpu_snp_req_rsp
();
`include "../generic_cache/VX_cache_config.vh"
interface VX_gpu_snp_req_rsp ();
// Snoop request
wire snp_req;
@ -16,5 +14,4 @@ interface VX_gpu_snp_req_rsp
endinterface
`endif

6
hw/rtl/interfaces/VX_icache_request_inter.v
View file

@ -1,10 +1,9 @@
`include "../VX_define.vh"
`ifndef VX_ICACHE_REQ
`define VX_ICACHE_REQ
`include "../VX_define.vh"
interface VX_icache_request_inter ();
wire[31:0] pc_address;
@ -15,5 +14,4 @@ interface VX_icache_request_inter ();
endinterface
`endif

7
hw/rtl/interfaces/VX_icache_response_inter.v
View file

@ -1,9 +1,8 @@
`include "../VX_define.vh"
`ifndef VX_ICACHE_RSP
`define VX_ICACHE_RSP
`include "../VX_define.vh"
interface VX_icache_response_inter ();
// wire ready;
@ -11,8 +10,6 @@ interface VX_icache_response_inter ();
wire[31:0] instruction;
wire delay;
endinterface
`endif

21
hw/rtl/interfaces/VX_inst_exec_wb_inter.v
View file

@ -1,21 +1,18 @@
`ifndef VX_EXEC_UNIT_WB_INST_INTER
`define VX_EXEC_UNIT_WB_INST_INTER
`include "../VX_define.vh"
`ifndef VX_EXEC_UNIT_WB_INST_INTER
`define VX_EXEC_UNIT_WB_INST_INTER
interface VX_inst_exec_wb_inter ();
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[31:0] exec_wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[31:0] exec_wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
endinterface
`endif

21
hw/rtl/interfaces/VX_inst_mem_wb_inter.v
View file

@ -1,21 +1,18 @@
`ifndef VX_MEM_WB_INST_INTER
`define VX_MEM_WB_INST_INTER
`include "../VX_define.vh"
`ifndef VX_MEM_WB_INST_INTER
`define VX_MEM_WB_INST_INTER
interface VX_inst_mem_wb_inter ();
wire[`NUM_THREADS-1:0][31:0] loaded_data;
wire[31:0] mem_wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
wire[`NUM_THREADS-1:0][31:0] loaded_data;
wire[31:0] mem_wb_pc;
wire[4:0] rd;
wire[1:0] wb;
wire[`NUM_THREADS-1:0] wb_valid;
wire[`NW_BITS-1:0] wb_warp_num;
endinterface
`endif

15
hw/rtl/interfaces/VX_inst_meta_inter.v
View file

@ -1,16 +1,15 @@
`include "../VX_define.vh"
`ifndef VX_F_D_INTER
`define VX_F_D_INTER
`include "../VX_define.vh"
interface VX_inst_meta_inter ();
wire[31:0] instruction;
wire[31:0] inst_pc;
wire[`NW_BITS-1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
wire[31:0] instruction;
wire[31:0] inst_pc;
wire[`NW_BITS-1:0] warp_num;
wire[`NUM_THREADS-1:0] valid;
endinterface
`endif

14
hw/rtl/interfaces/VX_jal_response_inter.v
View file

@ -1,17 +1,15 @@
`ifndef VX_JAL_RSP
`define VX_JAL_RSP
`include "../VX_define.vh"
`ifndef VX_JAL_RSP
`define VX_JAL_RSP
interface VX_jal_response_inter ();
wire jal;
wire[31:0] jal_dest;
wire[`NW_BITS-1:0] jal_warp_num;
wire jal;
wire[31:0] jal_dest;
wire[`NW_BITS-1:0] jal_warp_num;
endinterface
`endif

7
hw/rtl/interfaces/VX_join_inter.v
View file

@ -1,17 +1,14 @@
`include "../VX_define.vh"
`ifndef VX_JOIN_INTER
`define VX_JOIN_INTER
`include "../VX_define.vh"
interface VX_join_inter ();
wire is_join;
wire[`NW_BITS-1:0] join_warp_num;
endinterface
`endif

10
hw/rtl/interfaces/VX_lsu_req_inter.v
View file

@ -1,15 +1,14 @@
`include "../VX_define.vh"
`ifndef VX_LSU_REQ_INTER
`define VX_LSU_REQ_INTER
`include "../VX_define.vh"
interface VX_lsu_req_inter ();
wire[`NUM_THREADS-1:0] valid;
wire[31:0] lsu_pc;
wire[`NW_BITS-1:0] warp_num;
wire[31:0] lsu_pc;
wire[`NW_BITS-1:0] warp_num;
wire[`NUM_THREADS-1:0][31:0] store_data;
wire[`NUM_THREADS-1:0][31:0] base_address; // A reg data
wire[31:0] offset; // itype_immed
@ -20,5 +19,4 @@ interface VX_lsu_req_inter ();
endinterface
`endif

31
hw/rtl/interfaces/VX_mem_req_inter.v
View file

@ -1,28 +1,25 @@
`include "../VX_define.vh"
`ifndef VX_MEM_REQ_IN
`define VX_MEM_REQ_IN
`include "../VX_define.vh"
interface VX_mem_req_inter ();
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[2:0] mem_read;
wire[2:0] mem_write;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] rs1;
wire[4:0] rs2;
wire[2:0] mem_read;
wire[2:0] mem_write;
wire[4:0] rd;
wire[1:0] wb;
wire[4:0] rs1;
wire[4:0] rs2;
wire[`NUM_THREADS-1:0][31:0] rd2;
wire[31:0] PC_next;
wire[31:0] curr_PC;
wire[31:0] branch_offset;
wire[2:0] branch_type;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
wire[31:0] PC_next;
wire[31:0] curr_PC;
wire[31:0] branch_offset;
wire[2:0] branch_type;
wire[`NUM_THREADS-1:0] valid;
wire[`NW_BITS-1:0] warp_num;
endinterface
`endif

23
hw/rtl/interfaces/VX_mw_wb_inter.v
View file

@ -1,22 +1,19 @@
`ifndef VX_MW_WB_INTER
`define VX_MW_WB_INTER
`include "../VX_define.vh"
`ifndef VX_MW_WB_INTER
`define VX_MW_WB_INTER
interface VX_mw_wb_inter ();
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[`NUM_THREADS-1:0][31:0] mem_result;
wire[4:0] rd;
wire[1:0] wb;
wire[31:0] PC_next;
wire[`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
wire[`NUM_THREADS-1:0][31:0] alu_result;
wire[`NUM_THREADS-1:0][31:0] mem_result;
wire[4:0] rd;
wire[1:0] wb;
wire[31:0] PC_next;
wire[`NUM_THREADS-1:0] valid;
wire [`NW_BITS-1:0] warp_num;
endinterface
`endif

7
hw/rtl/interfaces/VX_warp_ctl_inter.v
View file

@ -1,10 +1,9 @@
`include "../VX_define.vh"
`ifndef VX_WARP_CTL_INTER
`define VX_WARP_CTL_INTER
`include "../VX_define.vh"
interface VX_warp_ctl_inter ();
wire[`NW_BITS-1:0] warp_num;
@ -29,8 +28,6 @@ interface VX_warp_ctl_inter ();
wire[`NUM_THREADS-1:0] split_later_mask;
wire[31:0] split_save_pc;
endinterface
`endif

6
hw/rtl/interfaces/VX_wb_inter.v
View file

@ -1,9 +1,7 @@
`include "../VX_define.vh"
`ifndef VX_WB_INTER
`define VX_WB_INTER
`include "../VX_define.vh"
interface VX_wb_inter ();
@ -16,6 +14,4 @@ interface VX_wb_inter ();
endinterface
`endif

8
hw/rtl/interfaces/VX_wstall_inter.v
View file

@ -1,15 +1,13 @@
`include "../VX_define.vh"
`ifndef VX_WSTALL_INTER
`define VX_WSTALL_INTER
`include "../VX_define.vh"
interface VX_wstall_inter();
wire wstall;
wire[`NW_BITS-1:0] warp_num;
endinterface
`endif