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https://github.com/vortexgpgpu/vortex.git
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code refactoring
This commit is contained in:
Blaise Tine
parent
4e6de0dc38
commit
4626389ee2
4 changed files with 44 additions and 64 deletions
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@ -85,4 +85,4 @@ runRel: wRel
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(cd obj_dir && ./VVortex)
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clean:
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rm obj_dir/*
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rm -rf obj_dir
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@ -127,8 +127,10 @@
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`define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
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`define SINGLE_CORE_BENCH 1
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//`define SINGLE_CORE_BENCH
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`define GLOBAL_BLOCK_SIZE_BYTES 16
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// ========================================= Dcache Configurable Knobs =========================================
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// General Cache Knobs
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@ -6,7 +6,6 @@ module Vortex
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parameter CORE_ID = 0
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)
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(
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`ifdef SINGLE_CORE_BENCH
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input wire clk,
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input wire reset,
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@ -53,10 +52,10 @@ module Vortex
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input wire [31:0] I_snp_req_addr,
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output wire I_snp_req_delay,
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output wire out_ebreak
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`else
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input wire clk,
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input wire reset,
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// IO
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@ -3,40 +3,40 @@
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module Vortex_SOC (
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input wire clk,
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input wire reset,
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// IO
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output wire io_valid[`NUMBER_CORES-1:0],
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output wire[31:0] io_data [`NUMBER_CORES-1:0],
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// System Clock
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input wire clk,
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input wire reset,
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output wire[31:0] number_cores,
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// IO
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output wire io_valid[`NUMBER_CORES-1:0],
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output wire[31:0] io_data [`NUMBER_CORES-1:0],
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output wire[31:0] number_cores,
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// DRAM Dcache Req
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output wire out_dram_req,
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output wire out_dram_req_write,
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output wire out_dram_req_read,
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output wire [31:0] out_dram_req_addr,
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output wire [31:0] out_dram_req_size,
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output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG],
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output wire [31:0] out_dram_expected_lat,
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output wire out_dram_req,
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output wire out_dram_req_write,
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output wire out_dram_req_read,
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output wire [31:0] out_dram_req_addr,
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output wire [31:0] out_dram_req_size,
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output wire [31:0] out_dram_req_data[`DBANK_LINE_SIZE_RNG],
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output wire [31:0] out_dram_expected_lat,
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// DRAM Dcache Res
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output wire out_dram_fill_accept,
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input wire out_dram_fill_rsp,
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input wire [31:0] out_dram_fill_rsp_addr,
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input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
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output wire out_dram_fill_accept,
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input wire out_dram_fill_rsp,
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input wire [31:0] out_dram_fill_rsp_addr,
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input wire [31:0] out_dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
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input wire l3c_snp_req,
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input wire l3c_snp_req_addr,
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output wire l3c_snp_req_delay,
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input wire llc_snp_req,
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input wire llc_snp_req_addr,
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output wire llc_snp_req_delay,
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output wire out_ebreak
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);
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output wire out_ebreak
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);
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`ifdef L3C
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// DRAM Dcache Req
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wire [`NUMBER_CLUSTERS-1:0] dram_req;
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wire [`NUMBER_CLUSTERS-1:0] dram_req_write;
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@ -54,11 +54,7 @@ module Vortex_SOC (
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assign number_cores = `NUMBER_CORES;
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// IO
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// wire per_core_io_valid[`NUMBER_CORES-1:0];
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// wire[31:0] per_core_io_data[`NUMBER_CORES-1:0];
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// Out ebreak
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// Out ebreak
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wire[`NUMBER_CORES-1:0] per_core_out_ebreak;
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assign out_ebreak = (&per_core_out_ebreak);
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@ -71,18 +67,17 @@ module Vortex_SOC (
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wire l3c_core_accept;
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wire l3c_snp_fwd;
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wire[31:0] l3c_snp_fwd_addr;
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wire[`L3NUMBER_REQUESTS-1:0] l3c_snp_fwd_delay_temp;
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wire l3c_snp_fwd_delay;
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wire l3c_snp_fwd;
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wire[31:0] l3c_snp_fwd_addr;
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wire[`L3NUMBER_REQUESTS-1:0] l3c_snp_fwd_delay_temp;
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wire l3c_snp_fwd_delay;
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assign l3c_snp_fwd_delay = (|l3c_snp_fwd_delay_temp);
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wire[`L3NUMBER_REQUESTS-1:0] l3c_wb;
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wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr;
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wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data;
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wire[`L3NUMBER_REQUESTS-1:0] l3c_wb;
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wire[`L3NUMBER_REQUESTS-1:0] [31:0] l3c_wb_addr;
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wire[`L3NUMBER_REQUESTS-1:0][`IBANK_LINE_SIZE_RNG][31:0] l3c_wb_data;
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wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_req_data;
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wire[`IBANK_LINE_SIZE_RNG][31:0] l3c_dram_fill_rsp_data;
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@ -95,9 +90,6 @@ module Vortex_SOC (
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end
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endgenerate
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//
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genvar l3c_curr_core;
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generate
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@ -203,9 +195,9 @@ module Vortex_SOC (
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.dram_snp_full (dram_snp_full),
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// Snoop Request
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.snp_req (l3c_snp_req),
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.snp_req_addr (l3c_snp_req_addr),
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.snp_req_delay (l3c_snp_req_delay),
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.snp_req (llc_snp_req),
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.snp_req_addr (llc_snp_req_addr),
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.snp_req_delay (llc_snp_req_delay),
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.snp_fwd (l3c_snp_fwd),
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.snp_fwd_addr (l3c_snp_fwd_addr),
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@ -227,8 +219,6 @@ module Vortex_SOC (
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for (curr_cluster = 0; curr_cluster < `NUMBER_CLUSTERS; curr_cluster=curr_cluster+1) begin
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////////////////////// BEGIN CLUSTER /////////////////
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// DRAM Dcache Req
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wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req;
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wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dram_req_write;
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@ -260,8 +250,6 @@ module Vortex_SOC (
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wire[`NUMBER_CORES_PER_CLUSTER-1:0] [31:0] per_core_I_dram_fill_rsp_addr;
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wire[`NUMBER_CORES_PER_CLUSTER-1:0][`IBANK_LINE_SIZE_RNG][31:0] per_core_I_dram_fill_rsp_data;
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// Snoop Requests
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wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_dcache_snp_req;
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wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_dcache_snp_req_addr;
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@ -271,7 +259,6 @@ module Vortex_SOC (
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wire[`NUMBER_CORES_PER_CLUSTER-1:0][31:0] per_core_icache_snp_req_addr;
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wire[`NUMBER_CORES_PER_CLUSTER-1:0] per_core_icache_snp_req_delay;
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// generate
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for (curr_core = 0; curr_core < `NUMBER_CORES_PER_CLUSTER; curr_core=curr_core+1) begin
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@ -346,8 +333,6 @@ module Vortex_SOC (
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// endgenerate
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//
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// generate
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for (l2c_curr_core = 0; l2c_curr_core < `LLNUMBER_REQUESTS; l2c_curr_core=l2c_curr_core+2) begin
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// Core Request
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@ -492,7 +477,6 @@ module Vortex_SOC (
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`else
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assign number_cores = `NUMBER_CORES;
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// IO
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@ -545,6 +529,7 @@ module Vortex_SOC (
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assign io_valid[curr_core] = per_core_io_valid[curr_core];
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assign io_data [curr_core] = per_core_io_data [curr_core];
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Vortex #(.CORE_ID(curr_core)) vortex_core(
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.clk (clk),
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.reset (reset),
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@ -735,16 +720,10 @@ module Vortex_SOC (
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.dram_snp_full (dram_snp_full),
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// Snoop Request
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.snp_req (l3c_snp_req),
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.snp_req_addr (l3c_snp_req_addr)
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.snp_req (llc_snp_req),
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.snp_req_addr (llc_snp_req_addr)
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);
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//////////////////// L2 Cache ////////////////////
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`endif
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