minor update

hw/rtl/VX_commit.v

@@ -60,8 +60,17 @@ module VX_commit #(
         .count (commit_size)
     );
 
-    assign cmt_to_csr_if.valid       = commit_fire;
-    assign cmt_to_csr_if.commit_size = commit_size;
+    VX_generic_register #(
+        .N(1 + CMTW),
+        .R(1)
+    ) pipe_reg (
+        .clk   (clk),
+        .reset (reset),
+        .stall (1'b0),
+        .flush (1'b0),
+        .in    ({commit_fire,         commit_size}),
+        .out   ({cmt_to_csr_if.valid, cmt_to_csr_if.commit_size})
+    );
 
     // Writeback
 

hw/rtl/VX_config.vh

@@ -194,7 +194,7 @@
 
 // Number of banks
 `ifndef DNUM_BANKS
-`define DNUM_BANKS `MIN(`NUM_THREADS, 4)
+`define DNUM_BANKS `NUM_THREADS
 `endif
 
 // Core Request Queue Size

hw/rtl/libs/VX_countones.v

@@ -8,7 +8,7 @@ module VX_countones #(
     input wire [N-1:0]       valids,
     output wire [N_BITS-1:0] count    
 );
-    reg [N_BITS-1:0] count_r;
+    /*reg [N_BITS-1:0] count_r;
 
     always @(*) begin
         count_r = 0;
@@ -19,6 +19,8 @@ module VX_countones #(
         end
     end
 
-    assign count = count_r;
+    assign count = count_r;*/
+
+    assign count = $countones(valids);
 
 endmodule