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https://github.com/vortexgpgpu/vortex.git
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minor update
This commit is contained in:
Blaise Tine
parent
34023ab814
commit
47c33cca66
3 changed files with 52 additions and 44 deletions
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@ -123,7 +123,7 @@ module VX_operands import VX_gpu_pkg::*; #(
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has_collision_n |= src_valid[i]
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&& src_valid[j+i]
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&& (req_bank_idx[i] == req_bank_idx[j+i])
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&& (src_regs[i] != src_regs[j+i]);
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&& (src_regs[i][`NR_BITS-1:BANK_SEL_BITS] != src_regs[j+i][`NR_BITS-1:BANK_SEL_BITS]);
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end
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end
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end
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@ -185,7 +185,7 @@ module VX_operands import VX_gpu_pkg::*; #(
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is_dup_rs1_rs2 <= (scoreboard_if.data.rs1 == scoreboard_if.data.rs2);
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is_dup_rs1_rs3 <= (scoreboard_if.data.rs1 == scoreboard_if.data.rs3);
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is_dup_rs2_rs3 <= (scoreboard_if.data.rs2 == scoreboard_if.data.rs3);
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gpr_rd_addr <= gpr_rd_addr_n;
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gpr_rd_addr <= gpr_rd_addr_n;
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gpr_rd_req_idx <= gpr_rd_req_idx_n;
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end
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end
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@ -228,11 +228,18 @@ module VX_operands import VX_gpu_pkg::*; #(
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.ready_out (operands_if.ready)
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);
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wire [RAM_ADDRW-1:0] gpr_wr_addr;
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wire [PER_BANK_ADDRW-1:0] gpr_wr_addr;
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if (ISSUE_WIS != 0) begin
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assign gpr_wr_addr = {writeback_if.data.wis, writeback_if.data.rd};
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assign gpr_wr_addr = {writeback_if.data.wis, writeback_if.data.rd[`NR_BITS-1:BANK_SEL_BITS]};
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end else begin
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assign gpr_wr_addr = writeback_if.data.rd;
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assign gpr_wr_addr = writeback_if.data.rd[`NR_BITS-1:BANK_SEL_BITS];
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end
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wire [BANK_SEL_WIDTH-1:0] gpr_wr_bank_idx;
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if (NUM_BANKS != 1) begin
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assign gpr_wr_bank_idx = writeback_if.data.rd[BANK_SEL_BITS-1:0];
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end else begin
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assign gpr_wr_bank_idx = '0;
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end
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`ifdef GPR_RESET
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@ -251,15 +258,13 @@ module VX_operands import VX_gpu_pkg::*; #(
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if (BANK_SEL_BITS != 0) begin
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assign gpr_wr_enabled = wr_enabled
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&& writeback_if.valid
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&& (gpr_wr_addr[BANK_SEL_BITS-1:0] == BANK_SEL_BITS'(b));
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&& (gpr_wr_bank_idx == BANK_SEL_BITS'(b));
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end else begin
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assign gpr_wr_enabled = wr_enabled && writeback_if.valid;
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end
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wire [PER_BANK_ADDRW-1:0] gpr_wr_addr_b = gpr_wr_addr[BANK_SEL_BITS +: PER_BANK_ADDRW];
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// prevent degenerate writes to R0
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wire gpr_wr_enabled_qual = gpr_wr_enabled && (| gpr_wr_addr);
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wire gpr_wr_enabled_qual = gpr_wr_enabled && (writeback_if.data.rd != 0);
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wire [BYTEENW-1:0] wren;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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@ -278,7 +283,7 @@ module VX_operands import VX_gpu_pkg::*; #(
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.read (1'b1),
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.wren (wren),
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.write (gpr_wr_enabled_qual),
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.waddr (gpr_wr_addr_b),
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.waddr (gpr_wr_addr),
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.wdata (writeback_if.data.data),
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.raddr (gpr_rd_addr[b]),
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.rdata (gpr_rd_data[b])
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -17,20 +17,21 @@
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module VX_dp_ram #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter ADDR_MIN = 0,
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parameter WRENW = 1,
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parameter OUT_REG = 0,
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parameter NO_RWCHECK = 0,
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parameter LUTRAM = 0,
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parameter LUTRAM = 0,
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parameter INIT_ENABLE = 0,
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parameter INIT_FILE = "",
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parameter [DATAW-1:0] INIT_VALUE = 0,
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parameter ADDRW = `LOG2UP(SIZE)
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) (
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) (
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input wire clk,
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input wire read,
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input wire write,
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input wire [WRENW-1:0] wren,
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input wire [ADDRW-1:0] waddr,
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input wire [ADDRW-1:0] waddr,
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input wire [DATAW-1:0] wdata,
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input wire [ADDRW-1:0] raddr,
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output wire [DATAW-1:0] rdata
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@ -48,16 +49,16 @@ module VX_dp_ram #(
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ram[i] = INIT_VALUE; \
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end \
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end
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`UNUSED_VAR (read)
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`ifdef SYNTHESIS
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if (WRENW > 1) begin
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`ifdef QUARTUS
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if (LUTRAM != 0) begin
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if (OUT_REG != 0) begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -72,7 +73,7 @@ module VX_dp_ram #(
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end
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assign rdata = rdata_r;
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end else begin
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`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -87,7 +88,7 @@ module VX_dp_ram #(
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end else begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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reg [WRENW-1:0][WSELW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -103,7 +104,7 @@ module VX_dp_ram #(
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assign rdata = rdata_r;
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end else begin
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if (NO_RWCHECK != 0) begin
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`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -115,7 +116,7 @@ module VX_dp_ram #(
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end
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assign rdata = ram[raddr];
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end else begin
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reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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reg [WRENW-1:0][WSELW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -132,9 +133,9 @@ module VX_dp_ram #(
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`else
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// default synthesis
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if (LUTRAM != 0) begin
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`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
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`USE_FAST_BRAM reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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if (OUT_REG != 0) begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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always @(posedge clk) begin
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if (write) begin
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@ -161,7 +162,7 @@ module VX_dp_ram #(
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end
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end else begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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reg [DATAW-1:0] rdata_r;
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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@ -178,7 +179,7 @@ module VX_dp_ram #(
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assign rdata = rdata_r;
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end else begin
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if (NO_RWCHECK != 0) begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -190,7 +191,7 @@ module VX_dp_ram #(
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end
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assign rdata = ram[raddr];
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -208,9 +209,9 @@ module VX_dp_ram #(
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end else begin
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// (WRENW == 1)
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if (LUTRAM != 0) begin
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`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
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`USE_FAST_BRAM reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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if (OUT_REG != 0) begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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always @(posedge clk) begin
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if (write) begin
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@ -231,7 +232,7 @@ module VX_dp_ram #(
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end
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end else begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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reg [DATAW-1:0] rdata_r;
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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@ -245,7 +246,7 @@ module VX_dp_ram #(
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assign rdata = rdata_r;
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end else begin
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if (NO_RWCHECK != 0) begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -254,7 +255,7 @@ module VX_dp_ram #(
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end
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assign rdata = ram[raddr];
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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@ -265,10 +266,10 @@ module VX_dp_ram #(
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end
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end
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end
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end
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end
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`else
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// RAM emulation
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reg [DATAW-1:0] ram [SIZE-1:0];
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reg [DATAW-1:0] ram [ADDR_MIN:SIZE-1];
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`RAM_INITIALIZATION
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wire [DATAW-1:0] ram_n;
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@ -276,8 +277,8 @@ module VX_dp_ram #(
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assign ram_n[i * WSELW +: WSELW] = ((WRENW == 1) | wren[i]) ? wdata[i * WSELW +: WSELW] : ram[waddr][i * WSELW +: WSELW];
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end
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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always @(posedge clk) begin
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if (write) begin
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ram[waddr] <= ram_n;
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@ -287,7 +288,7 @@ module VX_dp_ram #(
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end
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end
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assign rdata = rdata_r;
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end else begin
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end else begin
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reg [DATAW-1:0] prev_data;
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reg [ADDRW-1:0] prev_waddr;
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reg prev_write;
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@ -298,7 +299,7 @@ module VX_dp_ram #(
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prev_write <= (| wren);
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prev_data <= ram[waddr];
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prev_waddr <= waddr;
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end
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end
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if (LUTRAM || !NO_RWCHECK) begin
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`UNUSED_VAR (prev_write)
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`UNUSED_VAR (prev_data)
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@ -1,10 +1,10 @@
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// Copyright © 2019-2023
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//
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@ -17,17 +17,18 @@
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module VX_sp_ram #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter ADDR_MIN = 0,
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parameter WRENW = 1,
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parameter OUT_REG = 0,
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parameter NO_RWCHECK = 0,
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parameter LUTRAM = 0,
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parameter LUTRAM = 0,
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parameter INIT_ENABLE = 0,
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parameter INIT_FILE = "",
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parameter [DATAW-1:0] INIT_VALUE = 0,
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parameter ADDRW = `LOG2UP(SIZE)
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) (
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input wire clk,
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input wire read,
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) (
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input wire clk,
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input wire read,
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input wire write,
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input wire [WRENW-1:0] wren,
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input wire [ADDRW-1:0] addr,
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@ -37,6 +38,7 @@ module VX_sp_ram #(
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VX_dp_ram #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.ADDR_MIN (ADDR_MIN),
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.WRENW (WRENW),
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.OUT_REG (OUT_REG),
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.NO_RWCHECK (NO_RWCHECK),
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