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changed mem_req_arb in VX_cache_l3.sv to accept data_out

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sij814 2024-09-18 22:05:40 -07:00
parent 992f8d97d3
commit 48f86a48f6
1 changed files with 13 additions and 1 deletions
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14
hw/rtl/cache/VX_cache_l3.sv vendored
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@ -495,6 +495,7 @@ module VX_cache_l3 import VX_gpu_pkg::*; #(
// Memory request arbitration
wire [NUM_BANKS-1:0][(`CS_MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + LINE_SIZE + `CS_LINE_WIDTH + 1)-1:0] data_in;
wire [NUM_MEM_PORTS-1:0][(`CS_MEM_ADDR_WIDTH + MSHR_ADDR_WIDTH + 1 + LINE_SIZE + `CS_LINE_WIDTH + 1)-1:0] data_out;
for (genvar i = 0; i < NUM_BANKS; ++i) begin
assign data_in[i] = {
@ -518,12 +519,23 @@ module VX_cache_l3 import VX_gpu_pkg::*; #(
.valid_in (per_bank_mem_req_valid),
.ready_in (per_bank_mem_req_ready),
.data_in (data_in),
.data_out ({mem_req_addr_p, mem_req_rw_p, mem_req_byteen_p, mem_req_data_p, mem_req_id_p, mem_req_flush_p}),
.data_out (data_out),
.valid_out (mem_req_valid_p),
.ready_out (mem_req_ready_p),
`UNUSED_PIN (sel_out)
);
for (genvar i = 0; i < NUM_MEM_PORTS; ++i) begin
assign {
mem_req_addr_p[i],
mem_req_rw_p[i],
mem_req_byteen_p[i],
mem_req_data_p[i],
mem_req_id_p[i],
mem_req_flush_p[i]
} = data_out[i];
end
if (NUM_BANKS > 1) begin
for (genvar i = 0; i < NUM_MEM_PORTS; ++i) begin
wire [`CS_BANK_SEL_BITS-1:0] mem_req_bank_id = `CS_MEM_ADDR_TO_BANK_ID(mem_req_addr_p[i]);