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Simulate debug

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This commit is contained in:
felsabbagh3 2019-10-29 14:28:20 -04:00
parent 557c987bb0
commit 4aa04e76e6
12 changed files with 242 additions and 33 deletions
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6
kernel/vortex_test.dump
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@ -5,8 +5,8 @@ vortex_test.elf: file format elf32-littleriscv
Disassembly of section .text:
80000000 <_start>:
80000000: 7ffff137 lui sp,0x7ffff
80000004: 041010ef jal ra,80001844 <main>
80000000: 00400593 li a1,4
80000004: 00b58633 add a2,a1,a1
80000008: 00000513 li a0,0
8000000c: 0005006b 0x5006b
@ -23,7 +23,7 @@ Disassembly of section .text:
80000024: 00755c63 bge a0,t2,8000003c <loop_done>
80000028 <loop_body>:
80000028: 80010113 addi sp,sp,-2048 # 7fffe800 <SIZE+0x7fffe7ce>
80000028: 80010113 addi sp,sp,-2048
8000002c: 00050313 mv t1,a0
80000030: 0003506b 0x3506b

BIN
kernel/vortex_test.elf
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2
kernel/vortex_test.hex
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@ -1,5 +1,5 @@
:0200000480007A
:1000000037F1FF7FEF101004130500006B000500AF
:10000000930540003386B500130500006B00050022
:10001000938B0600130D0700130F010093030500D7
:1000200013051000635C75001301018013030500C4
:100030006B500300130515006FF0DFFE1300000086

15
kernel/vx_os/vx_back/vx_back.s
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@ -6,6 +6,11 @@
.type _start, @function
.global _start
_start:
li a1, 4
add a2, a1, a1
li a0, 0
.word 0x0005006b # tmc a0
###########################
# la a0, 0x10000000
# li a1, 7
# sw a1, 0(a0)
@ -67,11 +72,11 @@ _start:
# .word 0x0000306b #join
# ecall
############################
lui sp, 0x7ffff
# jal vx_before_main
jal main
li a0, 0
.word 0x0005006b # tmc a0
# lui sp, 0x7ffff
# # jal vx_before_main
# jal main
# li a0, 0
# .word 0x0005006b # tmc a0
# Hi:
# li a2, 7

2
models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v
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@ -47,6 +47,8 @@
//
// Known Work Arounds: N/A
//
`define ARM_UD_MODEL
`timescale 1 ns/1 ps
`define ARM_MEM_PROP 1.000
`define ARM_MEM_RETAIN 1.000

36
models/memory/cln28hpm/rf2_32x128_wm1/vsim/Makefile Normal file
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@ -0,0 +1,36 @@
ALL:sim
#TOOL INPUT
SRC = \
rf2_32x128_wm1_tb.v \
../rf2_32x128_wm1.v
CMD= \
-do "vcd file rf2_32x128_wm1_tb.vcd; \
vcd add -r /rf2_32x128_wm1_tb/*; \
run -all; \
quit -f"
OPT=-sv -sv12compat
LIB = rf_lib
# LOG=-logfile rf2_32x128_wm1_tb.log
LOG=
comp:
vlog $(OPT) -work $(LIB) $(SRC)
sim: comp
vsim rf2_32x128_wm1_tb $(LOG) -c -lib $(LIB) $(CMD)

89
models/memory/cln28hpm/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v Normal file
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@ -0,0 +1,89 @@
`timescale 1ns/1ps
module rf2_32x128_wm1_tb (
output [127 : 0] out_a_reg_data,
output reg clk,
output reg [4 : 0] rs1,
output reg [127 : 0] write_bit_mask,
output reg [4 : 0] rd,
output reg [127 : 0] write_data,
output reg cena,
output reg cenb
);
initial begin
clk <= 1'b0;
rs1 <= 5'b0;
write_bit_mask <= {128{1'b1}};
rd <= 5'b0;
write_data <= 128'b0;
cena <= 1'b1;
cenb <= 1'b1;
#100
cenb <= 1'b0;
write_bit_mask <= {{96{1'b1}}, {32{1'b0}}};
rd <= 5'h0a;
write_data <= 128'h0000_0002_0000_0002_0000_0002_0000_0002;
#10
cenb <= 1'b1;
write_bit_mask <= {128{1'b1}};
rd <= 5'b0;
write_data <= 128'b0;
#100
cena <= 1'b0;
rs1 <= 5'h0a;
#1000
$finish;
end
always @(clk) #5 clk <= ~clk;
rf2_32x128_wm1 first_ram (
.CENYA(),
.AYA(),
.CENYB(),
.WENYB(),
.AYB(),
.QA(out_a_reg_data),
.SOA(),
.SOB(),
.CLKA(clk),
.CENA(cena),
.AA(rs1),
.CLKB(clk),
.CENB(cenb),
.WENB(write_bit_mask),
.AB(rd),
.DB(write_data),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
.TENA(1'b1),
.TCENA(1'b0),
.TAA(5'b0),
.TENB(1'b1),
.TCENB(1'b0),
.TWENB(128'b0),
.TAB(5'b0),
.TDB(128'b0),
.RET1N(1'b1),
.SIA(2'b0),
.SEA(1'b0),
.DFTRAMBYP(1'b0),
.SIB(2'b0),
.SEB(1'b0),
.COLLDISN(1'b1)
);
endmodule

26
models/memory/cln28hpm/rf2_32x128_wm1/vsim/transcript Normal file
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@ -0,0 +1,26 @@
# vsim rf2_32x128_wm1_tb -c -lib rf_lib -do "vcd file rf2_32x128_wm1_tb.vcd; vcd add -r /rf2_32x128_wm1_tb/*; run -all; quit -f"
# Start time: 13:02:14 on Oct 29,2019
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# // ModelSim SE-64 10.6a Mar 16 2017Linux 3.10.0-1062.1.2.el7.x86_64
# //
# // Copyright 1991-2017 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // ModelSim SE-64 and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading work.rf2_32x128_wm1_tb(fast)
# Loading work.rf2_32x128_wm1(fast)
# vcd file rf2_32x128_wm1_tb.vcd
# vcd add -r /rf2_32x128_wm1_tb/*
# run -all
# ** Note: $finish : rf2_32x128_wm1_tb.v(42)
# Time: 220 ns Iteration: 0 Instance: /rf2_32x128_wm1_tb
# End time: 13:02:16 on Oct 29,2019, Elapsed time: 0:00:02
# Errors: 0, Warnings: 0

2
rtl/VX_define.v
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@ -9,7 +9,7 @@
// Uncomment the below line if NW=1
// `define ONLY
`define SYN 1
// `define SYN 1
`define CACHE_NUM_BANKS 8

86
rtl/VX_gpr.v
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@ -16,25 +16,43 @@ module VX_gpr (
wire write_enable;
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0));
`ifndef SYN
// `ifndef SYN
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.reset (reset),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
// byte_enabled_simple_dual_port_ram first_ram(
// .we (write_enable),
// .clk (clk),
// .reset (reset),
// .waddr (VX_writeback_inter.rd),
// .raddr1(VX_gpr_read.rs1),
// .raddr2(VX_gpr_read.rs2),
// .be (VX_writeback_inter.wb_valid),
// .wdata (VX_writeback_inter.write_data),
// .q1 (out_a_reg_data),
// .q2 (out_b_reg_data)
// );
// `else
wire writing_to_zero = (VX_writeback_inter.rd == 5'h0);
reg[31:0] use_before;
wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
integer i;
always @(posedge clk) begin
if (reset) begin
use_before = 0;
end else if (going_to_write) begin
use_before[VX_writeback_inter.rd] = 1;
end
end
`else
wire[`NT_M1:0][31:0] write_bit_mask;
genvar curr_t;
@ -43,7 +61,6 @@ module VX_gpr (
assign write_bit_mask[curr_t] = {32{~local_write}};
end
wire going_to_write = write_enable & (|VX_writeback_inter.wb_valid);
wire cenb = !going_to_write;
@ -51,6 +68,33 @@ module VX_gpr (
wire cena_1 = (VX_gpr_read.rs1 == 0);
wire cena_2 = (VX_gpr_read.rs2 == 0);
wire[`NT_M1:0][31:0] temp_a;
wire[`NT_M1:0][31:0] temp_b;
`ifndef SYN
genvar thread;
genvar curr_bit;
for (thread = 0; thread < `NT; thread = thread + 1)
begin
for (curr_bit = 0; curr_bit < 32; curr_bit=curr_bit+1)
begin
assign out_a_reg_data[thread][curr_bit] = (temp_a[thread][curr_bit] === 1'dx) ? 1'b0 : temp_a[thread][curr_bit];
assign out_b_reg_data[thread][curr_bit] = (temp_b[thread][curr_bit] === 1'dx) ? 1'b0 : temp_b[thread][curr_bit];
end
end
`else
assign out_a_reg_data = (cena_1 | !use_before[VX_gpr_read.rs1]) ? 0 : temp_a;
assign out_b_reg_data = (cena_2 | !use_before[VX_gpr_read.rs2]) ? 0 : temp_b;
`endif
wire[`NT_M1:0][31:0] to_write = writing_to_zero ? 0 : VX_writeback_inter.write_data;
// wire cena_1 = 0;
// wire cena_2 = 0;
// wire[127:0] write_bit_mask = {{32{~(VX_writeback_inter.wb_valid[3])}}, {32{~(VX_writeback_inter.wb_valid[2])}}, {32{~(VX_writeback_inter.wb_valid[1])}}, {32{~(VX_writeback_inter.wb_valid[0])}}};
/* verilator lint_off PINCONNECTEMPTY */
rf2_32x128_wm1 first_ram (
@ -59,7 +103,7 @@ module VX_gpr (
.CENYB(),
.WENYB(),
.AYB(),
.QA(out_a_reg_data),
.QA(temp_a),
.SOA(),
.SOB(),
.CLKA(clk),
@ -69,7 +113,7 @@ module VX_gpr (
.CENB(cenb),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.DB(to_write),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
@ -98,7 +142,7 @@ module VX_gpr (
.CENYB(),
.WENYB(),
.AYB(),
.QA(out_b_reg_data),
.QA(temp_b),
.SOA(),
.SOB(),
.CLKA(clk),
@ -108,7 +152,7 @@ module VX_gpr (
.CENB(cenb),
.WENB(write_bit_mask),
.AB(VX_writeback_inter.rd),
.DB(VX_writeback_inter.write_data),
.DB(to_write),
.EMAA(3'b011),
.EMASA(1'b0),
.EMAB(3'b011),
@ -129,6 +173,6 @@ module VX_gpr (
.COLLDISN(1'b1)
);
/* verilator lint_on PINCONNECTEMPTY */
`endif
// `endif
endmodule

9
rtl/modelsim/Makefile
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@ -73,13 +73,20 @@ SRC = \
../shared_memory/VX_bank_valids.v \
../shared_memory/VX_priority_encoder_sm.v \
../shared_memory/VX_shared_memory.v \
../shared_memory/VX_shared_memory_block.v
../shared_memory/VX_shared_memory_block.v \
../../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \
../../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \
../../models/memory/cln28hpm/rf2_32x128_wm1/rf2_32x128_wm1.v
# ../../models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
# vortex_dpi.h
CMD= \
-do "vcd file vortex.vcd; \
vcd add -r /vortex_tb/*; \
vcd add -r /vortex/*; \
run -all; \
quit -f"

2
rtl/modelsim/vortex_tb.v
View file

@ -102,7 +102,7 @@ module vortex_tb (
if (out_ebreak) begin
gracefulExit();
$finish;
#20 $finish;
end
end