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fixed rtlsim regression

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This commit is contained in:
Blaise Tine 2020-10-26 12:59:58 -04:00
parent d319ae3b97
commit 4bd5ee2673
2 changed files with 8 additions and 8 deletions
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2
driver/rtlsim/Makefile
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@ -55,7 +55,7 @@ VL_FLAGS += verilator.vlt
# Debugigng
ifdef DEBUG
VL_FLAGS += -DVCD_OUTPUT --assert --trace $(DBG_FLAGS)
VL_FLAGS += -DVCD_OUTPUT --assert --trace-fst --trace-threads 1 $(DBG_FLAGS)
CFLAGS += -DVCD_OUTPUT $(DBG_FLAGS)
else
VL_FLAGS += -DNDEBUG

14
hw/simulate/simulator.cpp
View file

@ -96,15 +96,15 @@ void Simulator::reset() {
}
void Simulator::step() {
this->eval_dram_bus();
this->eval_io_bus();
this->eval_csr_bus();
this->eval_snp_bus();
vortex_->clk = 0;
this->eval();
vortex_->clk = 1;
this->eval();
this->eval_dram_bus();
this->eval_io_bus();
this->eval_csr_bus();
this->eval_snp_bus();
}
void Simulator::eval() {
@ -216,7 +216,7 @@ void Simulator::eval_snp_bus() {
#endif
}
if (vortex_->snp_req_valid && vortex_->snp_req_ready) {
if (snp_req_size_) {
if (snp_req_size_ != 0) {
vortex_->snp_req_addr += 1;
vortex_->snp_req_tag += 1;
--snp_req_size_;
@ -289,7 +289,7 @@ void Simulator::flush_caches(uint32_t mem_addr, uint32_t size) {
vortex_->snp_req_valid = 1;
vortex_->snp_rsp_ready = 1;
snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
snp_req_size_ = (size + GLOBAL_BLOCK_SIZE - 1) / GLOBAL_BLOCK_SIZE;
--snp_req_size_;
pending_snp_reqs_ = 1;