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scope fixes

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This commit is contained in:
Blaise Tine 2020-10-13 08:44:55 -07:00
parent 99e209b7a2
commit 4bfc4ee78f
13 changed files with 56 additions and 42 deletions
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18
driver/opae/vlsim/Makefile
View file

@ -20,8 +20,8 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO
#CONFIGS += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1
CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
#CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0
CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=1
#DEBUG=1
SCOPE=1
@ -39,6 +39,8 @@ TOP = vortex_afu_shim
RTL_DIR=../../../hw/rtl
SCRIPT_DIR=../../../hw/scripts
SRCS = fpga.cpp opae_sim.cpp
SRCS += $(RTL_DIR)/fp_cores/svdpi/float_dpi.cpp
@ -67,7 +69,7 @@ endif
ifdef SCOPE
VL_FLAGS += -DSCOPE
CFLAGS += -DSCOPE
SCOPE_CFG = scope
SCOPE_VH = $(RTL_DIR)/scope-defs.vh
endif
VL_FLAGS += -DNOPAE
@ -80,12 +82,14 @@ PROJECT = libopae-c-vlsim.so
all: $(PROJECT)
# generate scope data
scope: ../../../hw/scripts/scope.json
../../../hw/scripts/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc ../scope-defs.h -vl ../../../hw/rtl/scope-defs.vh ../../../hw/scripts/scope.json
scope: $(RTL_DIR)/scope-defs.vh
$(RTL_DIR)/scope-defs.vh: $(SCRIPT_DIR)/scope.json
$(SCRIPT_DIR)/scope.py $(RTL_INCLUDE) $(CONFIGS) -cc ../scope-defs.h -vl $(RTL_DIR)/scope-defs.vh $(SCRIPT_DIR)/scope.json
$(PROJECT): $(SRCS) $(SCOPE_CFG)
$(PROJECT): $(SRCS) $(SCOPE_VH)
verilator --exe --cc $(TOP) --top-module $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT)
OPT_FAST="-O0 -g" make -j -C obj_dir -f V$(TOP).mk
clean:
rm -rf $(PROJECT) obj_dir ../scope-defs.h ../../../hw/rtl/scope-defs.vh
rm -rf $(PROJECT) obj_dir ../scope-defs.h $(RTL_DIR)/scope-defs.vh

2
hw/opae/sources_1c.txt
View file

@ -3,7 +3,7 @@
+define+SYNTHESIS
+define+QUARTUS
+define+FPU_FAST
#+define+SCOPE
+define+SCOPE
#+define+DBG_PRINT_CORE_ICACHE
#+define+DBG_PRINT_CORE_DCACHE

2
hw/opae/vortex_afu.sv
View file

@ -954,7 +954,7 @@ end
assign cmd_run_done = !vx_busy;
Vortex #() vortex (
`SCOPE_BIND_vortex_afu_vortex()
`SCOPE_BIND_vortex_afu_vortex
.clk (clk),
.reset (reset | vx_reset),

2
hw/rtl/VX_cluster.v
View file

@ -372,7 +372,7 @@ module VX_cluster #(
.SNP_REQ_TAG_WIDTH (`L2SNP_TAG_WIDTH),
.SNP_FWD_TAG_WIDTH (`DSNP_TAG_WIDTH)
) l2cache (
`SCOPE_BIND_VX_cluster_l2cache()
`SCOPE_BIND_VX_cluster_l2cache
.clk (clk),
.reset (reset),

4
hw/rtl/VX_core.v
View file

@ -175,7 +175,7 @@ module VX_core #(
VX_pipeline #(
.CORE_ID(CORE_ID)
) pipeline (
`SCOPE_BIND_VX_core_pipeline()
`SCOPE_BIND_VX_core_pipeline
.clk(clk),
.reset(reset),
@ -251,7 +251,7 @@ module VX_core #(
VX_mem_unit #(
.CORE_ID(CORE_ID)
) mem_unit (
`SCOPE_BIND_VX_core_mem_unit()
`SCOPE_BIND_VX_core_mem_unit
.clk (clk),
.reset (reset),

4
hw/rtl/VX_execute.v
View file

@ -54,7 +54,7 @@ module VX_execute #(
VX_lsu_unit #(
.CORE_ID(CORE_ID)
) lsu_unit (
`SCOPE_BIND_VX_execute_lsu_unit()
`SCOPE_BIND_VX_execute_lsu_unit
.clk (clk),
.reset (reset),
.dcache_req_if (dcache_req_if),
@ -121,7 +121,7 @@ module VX_execute #(
VX_gpu_unit #(
.CORE_ID(CORE_ID)
) gpu_unit (
`SCOPE_BIND_VX_execute_gpu_unit()
`SCOPE_BIND_VX_execute_gpu_unit
.clk (clk),
.reset (reset),
.gpu_req_if (gpu_req_if),

4
hw/rtl/VX_fetch.v
View file

@ -29,7 +29,7 @@ module VX_fetch #(
VX_warp_sched #(
.CORE_ID(CORE_ID)
) warp_sched (
`SCOPE_BIND_VX_fetch_warp_sched()
`SCOPE_BIND_VX_fetch_warp_sched
.clk (clk),
.reset (reset),
@ -45,7 +45,7 @@ module VX_fetch #(
VX_icache_stage #(
.CORE_ID(CORE_ID)
) icache_stage (
`SCOPE_BIND_VX_fetch_icache_stage()
`SCOPE_BIND_VX_fetch_icache_stage
.clk (clk),
.reset (reset),

6
hw/rtl/VX_mem_unit.v
View file

@ -77,7 +77,7 @@ module VX_mem_unit # (
.CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`SDRAM_TAG_WIDTH)
) smem (
`SCOPE_BIND_VX_mem_unit_smem()
`SCOPE_BIND_VX_mem_unit_smem
.clk (clk),
.reset (reset),
@ -159,7 +159,7 @@ module VX_mem_unit # (
.DRAM_TAG_WIDTH (`DDRAM_TAG_WIDTH),
.SNP_REQ_TAG_WIDTH (`DSNP_TAG_WIDTH)
) dcache (
`SCOPE_BIND_VX_mem_unit_dcache()
`SCOPE_BIND_VX_mem_unit_dcache
.clk (clk),
.reset (reset),
@ -240,7 +240,7 @@ module VX_mem_unit # (
.CORE_TAG_ID_BITS (`ICORE_TAG_ID_BITS),
.DRAM_TAG_WIDTH (`IDRAM_TAG_WIDTH)
) icache (
`SCOPE_BIND_VX_mem_unit_icache()
`SCOPE_BIND_VX_mem_unit_icache
.clk (clk),
.reset (reset),

6
hw/rtl/VX_pipeline.v
View file

@ -123,7 +123,7 @@ module VX_pipeline #(
VX_fetch #(
.CORE_ID(CORE_ID)
) fetch (
`SCOPE_BIND_VX_pipeline_fetch()
`SCOPE_BIND_VX_pipeline_fetch
.clk (clk),
.reset (reset),
.icache_req_if (core_icache_req_if),
@ -150,7 +150,7 @@ module VX_pipeline #(
VX_issue #(
.CORE_ID(CORE_ID)
) issue (
`SCOPE_BIND_VX_pipeline_issue()
`SCOPE_BIND_VX_pipeline_issue
.clk (clk),
.reset (reset),
@ -170,7 +170,7 @@ module VX_pipeline #(
VX_execute #(
.CORE_ID(CORE_ID)
) execute (
`SCOPE_BIND_VX_pipeline_execute()
`SCOPE_BIND_VX_pipeline_execute
.clk (clk),
.reset (reset),

34
hw/rtl/VX_scope.vh
View file

@ -15,15 +15,19 @@
`define SCOPE_IO_VX_fetch
`define SCOPE_BIND_VX_fetch_icache_stage()
`define SCOPE_BIND_VX_fetch_icache_stage
`define SCOPE_BIND_VX_fetch_warp_sched
`define SCOPE_IO_VX_warp_sched
`define SCOPE_IO_VX_pipeline
`define SCOPE_BIND_VX_pipeline_fetch()
`define SCOPE_BIND_VX_pipeline_fetch
`define SCOPE_IO_VX_core
`define SCOPE_BIND_VX_core_pipeline()
`define SCOPE_BIND_VX_core_pipeline
`define SCOPE_IO_VX_cluster
@ -33,19 +37,23 @@
`define SCOPE_BIND_Vortex_cluster(__i__)
`define SCOPE_BIND_vortex_afu_vortex()
`define SCOPE_BIND_vortex_afu_vortex
`define SCOPE_IO_VX_lsu_unit
`define SCOPE_IO_VX_gpu_unit
`define SCOPE_IO_VX_execute
`define SCOPE_BIND_VX_execute_lsu_unit()
`define SCOPE_BIND_VX_execute_lsu_unit
`define SCOPE_BIND_VX_pipeline_execute()
`define SCOPE_BIND_VX_execute_gpu_unit
`define SCOPE_BIND_VX_pipeline_execute
`define SCOPE_IO_VX_issue
`define SCOPE_BIND_VX_pipeline_issue()
`define SCOPE_BIND_VX_pipeline_issue
`define SCOPE_IO_VX_bank
@ -53,19 +61,19 @@
`define SCOPE_BIND_VX_cache_bank(__i__)
`define SCOPE_BIND_Vortex_l3cache()
`define SCOPE_BIND_Vortex_l3cache
`define SCOPE_BIND_VX_cluster_l2cache()
`define SCOPE_BIND_VX_cluster_l2cache
`define SCOPE_IO_VX_mem_unit
`define SCOPE_BIND_VX_mem_unit_dcache()
`define SCOPE_BIND_VX_mem_unit_dcache
`define SCOPE_BIND_VX_core_mem_unit()
`define SCOPE_BIND_VX_core_mem_unit
`define SCOPE_BIND_VX_mem_unit_icache()
`define SCOPE_BIND_VX_mem_unit_icache
`define SCOPE_BIND_VX_mem_unit_smem()
`define SCOPE_BIND_VX_mem_unit_smem
`define SCOPE_DECL_SIGNALS

2
hw/rtl/Vortex.v
View file

@ -395,7 +395,7 @@ module Vortex (
.SNP_REQ_TAG_WIDTH (`L3SNP_TAG_WIDTH),
.SNP_FWD_TAG_WIDTH (`L2SNP_TAG_WIDTH)
) l3cache (
`SCOPE_BIND_Vortex_l3cache()
`SCOPE_BIND_Vortex_l3cache
.clk (clk),
.reset (reset),

2
hw/scripts/scope.json
View file

@ -32,7 +32,7 @@
},
"VX_core": {
"submodules": {
"pipeline": {"type":"VX_pipeline", "enabled":false},
"pipeline": {"type":"VX_pipeline", "enabled":true},
"mem_unit": {"type":"VX_mem_unit", "enabled":true}
}
},

12
hw/scripts/scope.py
View file

@ -527,7 +527,7 @@ def gen_vl_header(file, modules, taps):
ports[nn] = pp
if (0 == scount):
nn = "SCOPE_BIND_" + ntype + '_' + spath + "()"
nn = "SCOPE_BIND_" + ntype + '_' + spath
pp = create_signal(nn, ports)
for st in new_staps:
if e:
@ -746,13 +746,15 @@ struct scope_tap_t {
continue
paths.pop(-1)
parent = -1
mk = ""
for path in paths:
if not path in mdic:
mk += '/' + path
if not mk in mdic:
index = len(mdic)
mdic[path] = (index, parent)
mdic[mk] = (path, index, parent)
parent = index
else:
parent = mdic[path][0]
parent = mdic[mk][1]
fdic[key][1] = parent
with open(file, 'w') as f:
@ -764,7 +766,7 @@ struct scope_tap_t {
m = mdic[key]
if i > 0:
print(',', file=f)
print("\t{\"" + key + "\", " + str(m[0]) + ", " + str(m[1]) + "}", file=f, end='')
print("\t{\"" + m[0] + "\", " + str(m[1]) + ", " + str(m[2]) + "}", file=f, end='')
i += 1
print("", file=f)
print("};", file=f)