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minor update

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This commit is contained in:
Blaise Tine 2023-03-24 05:40:45 -04:00
parent 87f7bf1f86
commit 4d6e00af28
3 changed files with 228 additions and 3 deletions
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114
hw/rtl/libs/VX_dp_ram.sv
View file

@ -34,7 +34,119 @@ module VX_dp_ram #(
end \
end
`ifdef SYNTHESIS
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
end
assign rdata = ram[raddr];
end
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[raddr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
rdata_r <= ram[raddr];
end
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
if (WRENW > 1) begin
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
end
assign rdata = ram[raddr];
end
end else begin
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[waddr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[raddr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[waddr] <= wdata;
end
assign rdata = ram[raddr];
end
end
end
end
`elsif VIVADO
if (LUTRAM != 0) begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION

115
hw/rtl/libs/VX_sp_ram.sv
View file

@ -34,7 +34,120 @@ module VX_sp_ram #(
end \
end
`ifdef SYNTHESIS
`ifdef QUARTUS
if (LUTRAM != 0) begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
if (WRENW > 1) begin
`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end
end else begin
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
rdata_r <= ram[addr];
end
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
rdata_r <= ram[addr];
end
end
assign rdata = rdata_r;
end else begin
if (NO_RWCHECK != 0) begin
if (WRENW > 1) begin
`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end else begin
if (WRENW > 1) begin
reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
for (integer i = 0; i < WRENW; ++i) begin
if (wren[i])
ram[addr][i] <= wdata[i * WSELW +: WSELW];
end
end
assign rdata = ram[addr];
end else begin
reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION
always @(posedge clk) begin
if (wren)
ram[addr] <= wdata;
end
assign rdata = ram[addr];
end
end
end
end
`elsif VIVADO
if (LUTRAM != 0) begin
`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
`RAM_INITIALIZATION

2
hw/rtl/raster_unit/VX_raster_mem.sv
View file

@ -346,7 +346,7 @@ module VX_raster_mem #(
VX_elastic_buffer #(
.DATAW (PRIM_DATA_WIDTH),
.SIZE (QUEUE_SIZE),
.OUT_REG (QUEUE_SIZE > 2)
.OUT_REG (1)
) buf_out (
.clk (clk),
.reset (reset),