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minor update

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This commit is contained in:
Blaise Tine 2024-03-06 08:10:22 -08:00
parent de0f4dda44
commit 4d7b2b9ea5
5 changed files with 17 additions and 9 deletions
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2
ci/trace_csv.py
View file

@ -225,7 +225,7 @@ def write_csv(log_filename, csv_filename, log_type):
sys.exit()
# sort entries by uuid
entries.sort(key=lambda x: (int(x['core_id']), int(x['warp_id']), int(x['lineno'])))
entries.sort(key=lambda x: (int(x['uuid'])))
for entry in entries:
del entry['lineno']

6
hw/rtl/VX_config.vh
View file

@ -253,11 +253,17 @@
`ifndef NUM_LSU_LANES
`define NUM_LSU_LANES `MIN(`NUM_THREADS, 4)
`endif
`ifndef NUM_LSU_BLOCKS
`define NUM_LSU_BLOCKS 1
`endif
// Number of SFU units
`ifndef NUM_SFU_LANES
`define NUM_SFU_LANES `MIN(`NUM_THREADS, 4)
`endif
`ifndef NUM_SFU_BLOCKS
`define NUM_SFU_BLOCKS 1
`endif
// Size of Instruction Buffer
`ifndef IBUF_SIZE

5
hw/rtl/VX_gpu_pkg.sv
View file

@ -112,12 +112,13 @@ package VX_gpu_pkg;
localparam DCACHE_LINE_SIZE = `L1_LINE_SIZE;
// Input request size
localparam DCACHE_NUM_REQS = `UP((`NUM_LSU_LANES * (`XLEN / 8)) / DCACHE_WORD_SIZE);
localparam DCACHE_CHANNELS = `UP((`NUM_LSU_LANES * (`XLEN / 8)) / DCACHE_WORD_SIZE);
localparam DCACHE_NUM_REQS = `NUM_LSU_BLOCKS * DCACHE_CHANNELS;
// Core request tag Id bits
localparam DCACHE_MERGED_REQS = (`NUM_LSU_LANES * (`XLEN / 8)) / DCACHE_WORD_SIZE;
localparam DCACHE_MEM_BATCHES = (DCACHE_MERGED_REQS + DCACHE_NUM_REQS - 1) / DCACHE_NUM_REQS;
localparam DCACHE_MEM_BATCHES = (DCACHE_MERGED_REQS + DCACHE_CHANNELS - 1) / DCACHE_CHANNELS;
localparam DCACHE_TAG_ID_BITS = (`CLOG2(`LSUQ_OUT_SIZE) + `CLOG2(DCACHE_MEM_BATCHES));
// Core request tag bits

12
hw/rtl/core/VX_lsu_unit.sv
View file

@ -40,6 +40,12 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
localparam LSUQ_SIZEW = `LOG2UP(`LSUQ_IN_SIZE);
localparam REQ_ASHIFT = `CLOG2(WORD_SIZE);
// tag_id = wid + PC + tmask + rd + op_type + align + is_dup + pid + pkt_addr
localparam TAG_ID_WIDTH = `NW_WIDTH + `XLEN + NUM_LANES + `NR_BITS + `INST_LSU_BITS + (NUM_LANES * (REQ_ASHIFT)) + `LSU_DUP_ENABLED + PID_WIDTH + LSUQ_SIZEW;
// tag = uuid + tag_id
localparam TAG_WIDTH = `UUID_WIDTH + TAG_ID_WIDTH;
VX_execute_if #(
.NUM_LANES (NUM_LANES)
) execute_if[BLOCK_SIZE]();
@ -71,12 +77,6 @@ module VX_lsu_unit import VX_gpu_pkg::*; #(
`UNUSED_VAR (execute_if[0].data.rs3_data)
`UNUSED_VAR (execute_if[0].data.tid)
// tag_id = wid + PC + tmask + rd + op_type + align + is_dup + pid + pkt_addr
localparam TAG_ID_WIDTH = `NW_WIDTH + `XLEN + NUM_LANES + `NR_BITS + `INST_LSU_BITS + (NUM_LANES * (REQ_ASHIFT)) + `LSU_DUP_ENABLED + PID_WIDTH + LSUQ_SIZEW;
// tag = uuid + tag_id
localparam TAG_WIDTH = `UUID_WIDTH + TAG_ID_WIDTH;
// full address calculation
wire [NUM_LANES-1:0][`XLEN-1:0] full_addr;

1
hw/rtl/libs/VX_mem_coalescer.sv
View file

@ -136,6 +136,7 @@ module VX_mem_coalescer #(
if (reset) begin
state_r <= STATE_SETUP;
processed_mask_r <= '0;
out_req_valid_r <= 0;
end else begin
state_r <= state_n;
out_req_valid_r <= out_req_valid_n;