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sgemm working

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This commit is contained in:
proshan3 2019-11-25 01:10:38 -05:00
parent ad9623b7dd
commit 4e90b26ab3
62 changed files with 46533 additions and 2417878 deletions
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10
benchmarks/vector/sgemm_nn/Makefile
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@ -1,11 +1,11 @@
LIB_PATH = ../../../runtime
COMP = /nethome/ekim79/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-gcc
COMP = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-gcc
CC_FLAGS = -ffreestanding -O0 -Wl,--gc-sections -nostartfiles -nostdlib -nostartfiles -nodefaultlibs -Wl,-Bstatic,-T,$(LIB_PATH)/mains/vortex_link.ld -march=rv32imv -mabi=ilp32
DMP = /nethome/ekim79/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objdump
CPY = /nethome/ekim79/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objcopy
DMP = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-objdump
CPY = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-objcopy
# VX_STR = ../../startup/vx_start.s
@ -16,8 +16,8 @@ VX_IO = $(LIB_PATH)/io/vx_io.s $(LIB_PATH)/io/vx_io.c
VX_API = $(LIB_PATH)/vx_api/vx_api.c
VX_TEST = $(LIB_PATH)/tests/tests.c
VX_FIO = $(LIB_PATH)/fileio/fileio.s
VX_VEC = test_asm.s #vx_vec_sgemm_nn_backup.s #float --> int
LIBS = /nethome/ekim79/riscv-gnu-toolchain/drops/riscv32-unknown-elf/lib/libc.a /nethome/ekim79/riscv-gnu-toolchain/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
VX_VEC = vx_vec_sgemm_nn.s #float --> int
LIBS = /home/priya/dev/riscv_vec/riscv-gnu/riscv32-unknown-elf/lib/libc.a /home/priya/dev/riscv_vec/riscv-gnu/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
VX_MAIN = vx_vec_sgemm_nn

24
benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.c
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@ -31,7 +31,7 @@ int main()
for (int i = 0; i < (m * n); ++i) d1[i] = 0;
#if 0
#if 1
printf("sgemm_nn\na[%d]:", m*k);
for (int i = 0; i < m*k; ++i) {
if(!(i % k)) printf("\n");
@ -49,18 +49,18 @@ int main()
int ldc = 4; //64;
int vsize = 4;
for (int r = 0; r < k; r++) {
for (int c = 0; c < m; c++) {
for (int i = 0; i < n;) {
for (int r = 0; r < m; r++) {
for (int c = 0; c < n; c++) {
for (int i = 0; i < k;) {
// d1[r*k+i] += a1[r*k+c]*b1[i*n+c];
vx_vec_sgemm_nn(i, c, r, a1, b1, c1, ldc, vsize);
vx_vec_sgemm_nn(i, r, c, a1, b1, c1, ldc, vsize);
i = i + vsize;
}
}
}
// vx_vec_sgemm_nn(n, a1, b1, c1);
#if 1
#if 1
printf("\n\nc[%d]:", m*n);
for (int i = 0; i < m*n; ++i) {
if (!(i % n)) printf("\n");
@ -68,15 +68,17 @@ int main()
}
#endif
for (int r = 0; r < k; r++) {
for (int c = 0; c < m; c++) {
for (int i = 0; i < n; i++) {
d1[r*k+i] += a1[r*k+c]*b1[i*n+c];
for (int r = 0; r < m; r++) {
for (int c = 0; c < n; c++) {
for (int i = 0; i < k; i++) {
d1[c*ldc+i] += a1[c*ldc+r]*b1[i + (r*ldc)];
//printf("d[%d] += a[%d]*b[%d]\n", c*ldc+i, c*ldc+r , i + (r*ldc));
//printf("%d %d %d\n", d1[c*ldc+i] , a1[c*ldc+r] , b1[i + (r*ldc)]);
}
}
}
#if 0
#if 1
printf("\n\nc[%d]:\n", m*n);
for(int i = 0; i < m; ++i) {
for(int j = 0; j < n; ++j) {

81677
benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.dump
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benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.elf
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benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.hex
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83
benchmarks/vector/sgemm_nn/vx_vec_sgemm_nn.s
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@ -1,61 +1,42 @@
.type vx_vec_sgemm_nn, @function
.global vx_vec_sgemm_nn
# RV64IDV system
#
# void
# sgemm_nn(size_t n, size_t m, size_t k,
# int *a, // m * k matrix
# int *b, // k * n matrix
# int *c) // m * n matrix
#
# c += a*b (alpha=1, no transpose on input matrices)
# matrices stored in C row-major order
#
# for (int r = 0; r < k; r++) {
# for (int c = 0; c < m; c++) {
# for (int i = 0; i < n; i++) {
# c[r*k+i] += a[r*k+c]*b[i*n+c];
# }
# }
# }
# a0 = n, a1 = m, a2 = k
# for (int n = 0; n < k; n++) {
# for (int m = 0; m < m; m++) {
# for (int i = 0; i < n;) {
#// d1[n*k+i] += a1[n*k+m]*b1[i*n+m];
# vx_vec_sgemm_nn(i, c, r, a1, b1, c1, ldc);
# i = i + 4;
# }
# }
# }
# a3 = a, a4 = b, a5 = c
# v0 = a, v2 = b, v2 = c
# x0 = i, x1 = c, x2 = r
#
# a0 = i, a1 = m, a2 = n
# a6 = ldc
vx_vec_sgemm_nn:
vsetvli t0, a2, e32, m8 # k
loop_row: # a[m][k]
vlw.v v0, (a3)
sub a2, a2, t0
slli t0, t0, 2
add a3, a3, t0
vsetvli t0, a7, e32
mul t1, a6, a2 # n*ldc
add t2, t1, a1 # i + (n*ldc)
slli t2, t2, 2
add a3, t2, a3 # a[i+ n*ldc]
lw t3, (a3)
vsetvli t1, a1, e32, m8 # m
loop_col: # b[k][n]
vlw.v v1, (a4)
sub a1, a1, t1
slli t1, t1, 2
add a4, a4, t1
mul t4, a1, a6 # m*ldc
add t5, a0, t4 # i + m*ldc
slli t5, t5, 2
add a4, t5, a4 # b[i + m*ldc]
# lw x6, (a4)
vsetvli t2, a0, e32, m8 # n
loop_iner:
vlw.v v2, (a5) # c[][]
sub a0, a0, t2
slli t2, t2, 2
add a5, a5, t2
vlw.v v0, (a4)
vmul.vx v1, v0, t3
mul t6, a2, a6 # n*ldc
add t0, a0, t6 # i + n*ldc
slli t0, t0, 2
add a5, t0, a5 # c[i + m*ldc]
bnez t2, loop_iner
vlw.v v2, (a5) #c
vadd.vv v2, v2, v1
vsw.v v2, (a5)
bnez t1, loop_col
# vadd.vv v0, v0, v0
# vsw.v v0, (a5)
# add a5, a5, t0
bnez t0, loop_row
ret

8
simX/enc.cpp
View file

@ -285,8 +285,8 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
inst.setVlsWidth((code>>shift_func3) & func3_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setVmask((code>>shift_vmask));
inst.setVmop((code>>shift_vmop) && func3_mask);
inst.setVnf((code>>shift_vnf) && func3_mask);
inst.setVmop((code>>shift_vmop) & func3_mask);
inst.setVnf((code>>shift_vnf) & func3_mask);
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);
@ -300,8 +300,8 @@ Instruction *WordDecoder::decode(const std::vector<Byte> &v, Size &idx, trace_in
inst.setVlsWidth((code>>shift_func3) & func3_mask);
inst.setSrcReg((code>>shift_rs2) & reg_mask);
inst.setVmask((code>>shift_vmask));
inst.setVmop((code>>shift_vmop) && func3_mask);
inst.setVnf((code>>shift_vnf) && func3_mask);
inst.setVmop((code>>shift_vmop) & func3_mask);
inst.setVnf((code>>shift_vnf) & func3_mask);
trace_inst->valid_inst = true;
trace_inst->rs1 = ((code>>shift_rs1) & reg_mask);

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simX/obj_dir/Vcache_simX
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208
simX/obj_dir/Vcache_simX.cpp
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@ -1,208 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX) {
Vcache_simX__Syms* __restrict vlSymsp = __VlSymsp = new Vcache_simX__Syms(this, name());
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
VL_CELL (__PVT__v, Vcache_simX_cache_simX);
// Reset internal values
// Reset structure values
clk = VL_RAND_RESET_I(1);
reset = VL_RAND_RESET_I(1);
in_icache_pc_addr = VL_RAND_RESET_I(32);
in_icache_valid_pc_addr = VL_RAND_RESET_I(1);
out_icache_stall = VL_RAND_RESET_I(1);
in_dcache_mem_read = VL_RAND_RESET_I(3);
in_dcache_mem_write = VL_RAND_RESET_I(3);
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_dcache_in_valid[__Vi0] = VL_RAND_RESET_I(1);
}}
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_dcache_in_address[__Vi0] = VL_RAND_RESET_I(32);
}}
out_dcache_stall = VL_RAND_RESET_I(1);
__Vclklast__TOP__clk = VL_RAND_RESET_I(1);
__Vclklast__TOP__reset = VL_RAND_RESET_I(1);
__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr = VL_RAND_RESET_I(28);
__Vm_traceActivity = VL_RAND_RESET_I(32);
}
void Vcache_simX::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX::~Vcache_simX() {
delete __VlSymsp; __VlSymsp=NULL;
}
//--------------------
void Vcache_simX::eval() {
Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Initialize
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
// Evaluate till stable
VL_DEBUG_IF(VL_PRINTF("\n----TOP Evaluate Vcache_simX::eval\n"); );
int __VclockLoop = 0;
QData __Vchange=1;
while (VL_LIKELY(__Vchange)) {
VL_DEBUG_IF(VL_PRINTF(" Clock loop\n"););
vlSymsp->__Vm_activity = true;
_eval(vlSymsp);
__Vchange = _change_request(vlSymsp);
if (++__VclockLoop > 100) vl_fatal(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
}
}
void Vcache_simX::_eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp) {
vlSymsp->__Vm_didInit = true;
_eval_initial(vlSymsp);
vlSymsp->__Vm_activity = true;
int __VclockLoop = 0;
QData __Vchange=1;
while (VL_LIKELY(__Vchange)) {
_eval_settle(vlSymsp);
_eval(vlSymsp);
__Vchange = _change_request(vlSymsp);
if (++__VclockLoop > 100) vl_fatal(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
}
}
//--------------------
// Internal Methods
VL_INLINE_OPT void Vcache_simX::_combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_combo__TOP__1\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v.in_dcache_in_valid[3U] = vlTOPp->in_dcache_in_valid
[3U];
vlSymsp->TOP__v.in_dcache_in_valid[2U] = vlTOPp->in_dcache_in_valid
[2U];
vlSymsp->TOP__v.in_dcache_in_valid[1U] = vlTOPp->in_dcache_in_valid
[1U];
vlSymsp->TOP__v.in_dcache_in_valid[0U] = vlTOPp->in_dcache_in_valid
[0U];
vlSymsp->TOP__v.in_dcache_in_address[3U] = vlTOPp->in_dcache_in_address
[3U];
vlSymsp->TOP__v.in_dcache_in_address[2U] = vlTOPp->in_dcache_in_address
[2U];
vlSymsp->TOP__v.in_dcache_in_address[1U] = vlTOPp->in_dcache_in_address
[1U];
vlSymsp->TOP__v.in_dcache_in_address[0U] = vlTOPp->in_dcache_in_address
[0U];
}
VL_INLINE_OPT void Vcache_simX::_combo__TOP__3(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_combo__TOP__3\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_icache_stall = ((IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__new_stored_valid)
| (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__state)));
}
VL_INLINE_OPT void Vcache_simX::_combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_combo__TOP__5\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlTOPp->out_dcache_stall = ((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__vx_priority_encoder_sm__DOT__more_than_one_valid))
| ((0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__new_stored_valid))
| (0U != (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state))));
}
void Vcache_simX::_eval(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_eval\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__1(vlSymsp);
vlTOPp->__Vm_traceActivity = (2U | vlTOPp->__Vm_traceActivity);
vlTOPp->_combo__TOP__1(vlSymsp);
if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))
| ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
vlSymsp->TOP__v__dmem_controller._sequent__TOP__v__dmem_controller__3(vlSymsp);
vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity);
vlSymsp->TOP__v._sequent__TOP__v__2(vlSymsp);
vlSymsp->TOP__v__dmem_controller._sequent__TOP__v__dmem_controller__4(vlSymsp);
}
vlSymsp->TOP__v._combo__TOP__v__3(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__5(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__7(vlSymsp);
if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))
| ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) {
vlSymsp->TOP__v__dmem_controller._sequent__TOP__v__dmem_controller__8(vlSymsp);
vlTOPp->__Vm_traceActivity = (8U | vlTOPp->__Vm_traceActivity);
}
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__10(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__12(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__14(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__16(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__18(vlSymsp);
vlTOPp->_combo__TOP__3(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__20(vlSymsp);
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__22(vlSymsp);
vlTOPp->_combo__TOP__5(vlSymsp);
// Final
vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk;
vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset;
}
void Vcache_simX::_eval_initial(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_eval_initial\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vcache_simX::final() {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::final\n"); );
// Variables
Vcache_simX__Syms* __restrict vlSymsp = this->__VlSymsp;
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
}
void Vcache_simX::_eval_settle(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_eval_settle\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__dmem_controller._combo__TOP__v__dmem_controller__1(vlSymsp);
vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity);
vlTOPp->_combo__TOP__1(vlSymsp);
vlSymsp->TOP__v._settle__TOP__v__1(vlSymsp);
vlSymsp->TOP__v._settle__TOP__v__4(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__6(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__9(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__11(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__13(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__15(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__17(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__19(vlSymsp);
vlTOPp->_combo__TOP__3(vlSymsp);
vlSymsp->TOP__v__dmem_controller._settle__TOP__v__dmem_controller__21(vlSymsp);
vlTOPp->_combo__TOP__5(vlSymsp);
}
VL_INLINE_OPT QData Vcache_simX::_change_request(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX::_change_request\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// Change detection
QData __req = false; // Logically a bool
__req |= ((vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr ^ vlTOPp->__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr));
VL_DEBUG_IF( if(__req && ((vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr ^ vlTOPp->__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr))) VL_PRINTF(" CHANGE: ../rtl/shared_memory/VX_shared_memory.v:49: shared_memory.block_addr\n"); );
// Final
vlTOPp->__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr
= vlSymsp->TOP__v__dmem_controller.__PVT__shared_memory__DOT__block_addr;
return __req;
}

113
simX/obj_dir/Vcache_simX.h
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@ -1,113 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Primary design header
//
// This header should be included by all source files instantiating the design.
// The class here is then constructed to instantiate the design.
// See the Verilator manual for examples.
#ifndef _Vcache_simX_H_
#define _Vcache_simX_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class Vcache_simX_cache_simX;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX) {
public:
// CELLS
// Public to allow access to /*verilator_public*/ items;
// otherwise the application code can consider these internals.
Vcache_simX_cache_simX* __PVT__v;
// PORTS
// The application code writes and reads these signals to
// propagate new values into/out from the Verilated model.
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_IN8(in_icache_valid_pc_addr,0,0);
VL_OUT8(out_icache_stall,0,0);
VL_IN8(in_dcache_mem_read,2,0);
VL_IN8(in_dcache_mem_write,2,0);
VL_OUT8(out_dcache_stall,0,0);
//char __VpadToAlign7[1];
VL_IN(in_icache_pc_addr,31,0);
VL_IN8(in_dcache_in_valid[4],0,0);
VL_IN(in_dcache_in_address[4],31,0);
// LOCAL SIGNALS
// Internals; generally not touched by application code
// LOCAL VARIABLES
// Internals; generally not touched by application code
VL_SIG8(__Vclklast__TOP__clk,0,0);
VL_SIG8(__Vclklast__TOP__reset,0,0);
//char __VpadToAlign42[2];
VL_SIG(__Vchglast__TOP__v__dmem_controller__shared_memory__DOT__block_addr,27,0);
VL_SIG(__Vm_traceActivity,31,0);
// INTERNAL VARIABLES
// Internals; generally not touched by application code
Vcache_simX__Syms* __VlSymsp; // Symbol table
// PARAMETERS
// Parameters marked /*verilator public*/ for use by application code
// CONSTRUCTORS
private:
Vcache_simX& operator= (const Vcache_simX&); ///< Copying not allowed
Vcache_simX(const Vcache_simX&); ///< Copying not allowed
public:
/// Construct the model; called by application code
/// The special name may be used to make a wrapper with a
/// single model invisible WRT DPI scope names.
Vcache_simX(const char* name="TOP");
/// Destroy the model; called (often implicitly) by application code
~Vcache_simX();
/// Trace signals in the model; called by application code
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
/// Evaluate the model. Application must call when inputs change.
void eval();
/// Simulation complete, run final blocks. Application must call on completion.
void final();
// INTERNAL METHODS
private:
static void _eval_initial_loop(Vcache_simX__Syms* __restrict vlSymsp);
public:
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
private:
static QData _change_request(Vcache_simX__Syms* __restrict vlSymsp);
public:
static void _combo__TOP__1(Vcache_simX__Syms* __restrict vlSymsp);
static void _combo__TOP__3(Vcache_simX__Syms* __restrict vlSymsp);
static void _combo__TOP__5(Vcache_simX__Syms* __restrict vlSymsp);
static void _eval(Vcache_simX__Syms* __restrict vlSymsp);
static void _eval_initial(Vcache_simX__Syms* __restrict vlSymsp);
static void _eval_settle(Vcache_simX__Syms* __restrict vlSymsp);
static void traceChgThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__2(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__3(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__4(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__5(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__6(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__7(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__8(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceChgThis__9(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceFullThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInitThis(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInitThis__1(Vcache_simX__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

91
simX/obj_dir/Vcache_simX.mk
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@ -1,91 +0,0 @@
# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
#
# Execute this makefile from the object directory:
# make -f Vcache_simX.mk
default: Vcache_simX
### Constants...
# Perl executable (from $PERL)
PERL = perl
# Path to Verilator kit (from $VERILATOR_ROOT)
VERILATOR_ROOT = /usr/share/verilator
# Path to SystemPerl kit top (from $SYSTEMPERL)
SYSTEMPERL =
# Path to SystemPerl kit includes (from $SYSTEMPERL_INCLUDE)
SYSTEMPERL_INCLUDE =
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
SYSTEMC_INCLUDE ?=
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
SYSTEMC_LIBDIR ?=
### Switches...
# SystemPerl output mode? 0/1 (from --sp)
VM_SP = 0
# SystemC output mode? 0/1 (from --sc)
VM_SC = 0
# SystemPerl or SystemC output mode? 0/1 (from --sp/--sc)
VM_SP_OR_SC = 0
# Deprecated
VM_PCLI = 1
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
VM_SC_TARGET_ARCH = linux
### Vars...
# Design prefix (from --prefix)
VM_PREFIX = Vcache_simX
# Module prefix (from --prefix)
VM_MODPREFIX = Vcache_simX
# User CFLAGS (from -CFLAGS on Verilator command line)
VM_USER_CFLAGS = \
-std=c++11 -fPIC -O3 \
# User LDLIBS (from -LDFLAGS on Verilator command line)
VM_USER_LDLIBS = \
# User .cpp files (from .cpp's on Verilator command line)
VM_USER_CLASSES = \
args \
core \
enc \
instruction \
mem \
simX \
util \
# User .cpp directories (from .cpp's on Verilator command line)
VM_USER_DIR = \
. \
### Default rules...
# Include list of all generated classes
include Vcache_simX_classes.mk
# Include global rules
include $(VERILATOR_ROOT)/include/verilated.mk
### Executable rules... (from --exe)
VPATH += $(VM_USER_DIR)
args.o: args.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
core.o: core.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
enc.o: enc.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
instruction.o: instruction.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
mem.o: mem.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
simX.o: simX.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
util.o: util.cpp
$(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<
### Link rules... (from --exe)
Vcache_simX: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt
# Verilated -*- Makefile -*-

30
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.cpp
View file

@ -1,30 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dcache_request_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dcache_request_inter) {
// Reset internal values
// Reset structure values
VL_RAND_RESET_W(128,__PVT__out_cache_driver_in_address);
__PVT__out_cache_driver_in_valid = VL_RAND_RESET_I(4);
}
void Vcache_simX_VX_dcache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dcache_request_inter::~Vcache_simX_VX_dcache_request_inter() {
}
//--------------------
// Internal Methods

55
simX/obj_dir/Vcache_simX_VX_dcache_request_inter.h
View file

@ -1,55 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dcache_request_inter_H_
#define _Vcache_simX_VX_dcache_request_inter_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dcache_request_inter) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
VL_SIG8(__PVT__out_cache_driver_in_valid,3,0);
//char __VpadToAlign5[3];
VL_SIGW(__PVT__out_cache_driver_in_address,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dcache_request_inter& operator= (const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed
Vcache_simX_VX_dcache_request_inter(const Vcache_simX_VX_dcache_request_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_dcache_request_inter(const char* name="TOP");
~Vcache_simX_VX_dcache_request_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

28
simX/obj_dir/Vcache_simX_VX_dcache_response_inter.cpp
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@ -1,28 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dcache_response_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dcache_response_inter) {
// Reset internal values
// Reset structure values
}
void Vcache_simX_VX_dcache_response_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dcache_response_inter::~Vcache_simX_VX_dcache_response_inter() {
}
//--------------------
// Internal Methods

53
simX/obj_dir/Vcache_simX_VX_dcache_response_inter.h
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@ -1,53 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dcache_response_inter_H_
#define _Vcache_simX_VX_dcache_response_inter_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dcache_response_inter) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
//char __VpadToAlign12[4];
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dcache_response_inter& operator= (const Vcache_simX_VX_dcache_response_inter&); ///< Copying not allowed
Vcache_simX_VX_dcache_response_inter(const Vcache_simX_VX_dcache_response_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_dcache_response_inter(const char* name="TOP");
~Vcache_simX_VX_dcache_response_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

13421
simX/obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.cpp
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File diff suppressed because it is too large Load diff

1037
simX/obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.h
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File diff suppressed because it is too large Load diff

29
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp
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@ -1,29 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
// Reset internal values
// Reset structure values
VL_RAND_RESET_W(128,__PVT__i_m_readdata);
}
void Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4() {
}
//--------------------
// Internal Methods

54
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h
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@ -1,54 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N1_NB4_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N1_NB4) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
//char __VpadToAlign4[4];
VL_SIGW(__PVT__i_m_readdata,127,0,4);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N1_NB4&); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4(const char* name="TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N1_NB4();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

29
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp
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@ -1,29 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
// Reset internal values
// Reset structure values
VL_RAND_RESET_W(512,__PVT__i_m_readdata);
}
void Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4::~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4() {
}
//--------------------
// Internal Methods

54
simX/obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h
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@ -1,54 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#define _Vcache_simX_VX_dram_req_rsp_inter__N4_NB4_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_dram_req_rsp_inter__N4_NB4) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
//char __VpadToAlign4[4];
VL_SIGW(__PVT__i_m_readdata,511,0,16);
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4& operator= (const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const Vcache_simX_VX_dram_req_rsp_inter__N4_NB4&); ///< Copying not allowed
public:
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4(const char* name="TOP");
~Vcache_simX_VX_dram_req_rsp_inter__N4_NB4();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

28
simX/obj_dir/Vcache_simX_VX_icache_request_inter.cpp
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@ -1,28 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_icache_request_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_icache_request_inter) {
// Reset internal values
// Reset structure values
}
void Vcache_simX_VX_icache_request_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_icache_request_inter::~Vcache_simX_VX_icache_request_inter() {
}
//--------------------
// Internal Methods

53
simX/obj_dir/Vcache_simX_VX_icache_request_inter.h
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@ -1,53 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_icache_request_inter_H_
#define _Vcache_simX_VX_icache_request_inter_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_icache_request_inter) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
//char __VpadToAlign12[4];
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_icache_request_inter& operator= (const Vcache_simX_VX_icache_request_inter&); ///< Copying not allowed
Vcache_simX_VX_icache_request_inter(const Vcache_simX_VX_icache_request_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_icache_request_inter(const char* name="TOP");
~Vcache_simX_VX_icache_request_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

28
simX/obj_dir/Vcache_simX_VX_icache_response_inter.cpp
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@ -1,28 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_VX_icache_response_inter.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_VX_icache_response_inter) {
// Reset internal values
// Reset structure values
}
void Vcache_simX_VX_icache_response_inter::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_VX_icache_response_inter::~Vcache_simX_VX_icache_response_inter() {
}
//--------------------
// Internal Methods

53
simX/obj_dir/Vcache_simX_VX_icache_response_inter.h
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@ -1,53 +0,0 @@
// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_VX_icache_response_inter_H_
#define _Vcache_simX_VX_icache_response_inter_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_VX_icache_response_inter) {
public:
// CELLS
// PORTS
// LOCAL SIGNALS
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
//char __VpadToAlign12[4];
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_VX_icache_response_inter& operator= (const Vcache_simX_VX_icache_response_inter&); ///< Copying not allowed
Vcache_simX_VX_icache_response_inter(const Vcache_simX_VX_icache_response_inter&); ///< Copying not allowed
public:
Vcache_simX_VX_icache_response_inter(const char* name="TOP");
~Vcache_simX_VX_icache_response_inter();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

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simX/obj_dir/Vcache_simX__ALLcls.cpp
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// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX.cpp"
#include "Vcache_simX_cache_simX.cpp"
#include "Vcache_simX_VX_dmem_controller__V0_VB1000.cpp"
#include "Vcache_simX_VX_icache_request_inter.cpp"
#include "Vcache_simX_VX_icache_response_inter.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
#include "Vcache_simX_VX_dcache_request_inter.cpp"
#include "Vcache_simX_VX_dcache_response_inter.cpp"

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simX/obj_dir/Vcache_simX__ALLcls.d
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@ -1,19 +0,0 @@
Vcache_simX__ALLcls.o: Vcache_simX__ALLcls.cpp Vcache_simX.cpp \
Vcache_simX.h /usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
Vcache_simX__Syms.h Vcache_simX_cache_simX.h \
Vcache_simX_VX_dmem_controller__V0_VB1000.h \
Vcache_simX_VX_icache_request_inter.h \
Vcache_simX_VX_icache_response_inter.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h \
Vcache_simX_VX_dcache_response_inter.h Vcache_simX_cache_simX.cpp \
Vcache_simX_VX_dmem_controller__V0_VB1000.cpp \
Vcache_simX_VX_icache_request_inter.cpp \
Vcache_simX_VX_icache_response_inter.cpp \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp \
Vcache_simX_VX_dcache_request_inter.cpp \
Vcache_simX_VX_dcache_response_inter.cpp

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simX/obj_dir/Vcache_simX__ALLsup.cpp
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// DESCRIPTION: Generated by verilator_includer via makefile
#define VL_INCLUDE_OPT include
#include "Vcache_simX__Trace.cpp"
#include "Vcache_simX__Syms.cpp"
#include "Vcache_simX__Trace__Slow.cpp"

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simX/obj_dir/Vcache_simX__ALLsup.d
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Vcache_simX__ALLsup.o: Vcache_simX__ALLsup.cpp Vcache_simX__Trace.cpp \
/usr/share/verilator/include/verilated_vcd_c.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Syms.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h Vcache_simX.h \
Vcache_simX__Inlines.h Vcache_simX_cache_simX.h \
Vcache_simX_VX_dmem_controller__V0_VB1000.h \
Vcache_simX_VX_icache_request_inter.h \
Vcache_simX_VX_icache_response_inter.h \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h \
Vcache_simX_VX_dcache_request_inter.h \
Vcache_simX_VX_dcache_response_inter.h Vcache_simX__Syms.cpp \
Vcache_simX__Trace__Slow.cpp

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simX/obj_dir/Vcache_simX__Inlines.h
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// Verilated -*- C++ -*-
#ifndef _Vcache_simX__Inlines_H_
#define _Vcache_simX__Inlines_H_
#include "verilated.h"
//======================
#ifndef VL_HAVE_CONST_W_16X
# define VL_HAVE_CONST_W_16X
static inline WDataOutP VL_CONST_W_16X(int obits, WDataOutP o
,IData d15,IData d14,IData d13,IData d12,IData d11,IData d10,IData d9,IData d8
,IData d7,IData d6,IData d5,IData d4,IData d3,IData d2,IData d1,IData d0) {
o[15]=d15; o[14]=d14; o[13]=d13; o[12]=d12; o[11]=d11; o[10]=d10; o[9]=d9; o[8]=d8;
o[7]=d7; o[6]=d6; o[5]=d5; o[4]=d4; o[3]=d3; o[2]=d2; o[1]=d1; o[0]=d0;
for(int i=16;i<VL_WORDS_I(obits);i++) o[i] = (IData)0x0;
return o;
}
#endif
//======================
#endif /*guard*/

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simX/obj_dir/Vcache_simX__Syms.cpp
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table implementation internals
#include "Vcache_simX__Syms.h"
#include "Vcache_simX.h"
#include "Vcache_simX_cache_simX.h"
#include "Vcache_simX_VX_dmem_controller__V0_VB1000.h"
#include "Vcache_simX_VX_icache_request_inter.h"
#include "Vcache_simX_VX_icache_response_inter.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_dcache_response_inter.h"
// FUNCTIONS
Vcache_simX__Syms::Vcache_simX__Syms(Vcache_simX* topp, const char* namep)
// Setup locals
: __Vm_namep(namep)
, __Vm_activity(false)
, __Vm_didInit(false)
// Setup submodule names
, TOP__v (Verilated::catName(topp->name(),"v"))
, TOP__v__VX_dcache_req (Verilated::catName(topp->name(),"v.VX_dcache_req"))
, TOP__v__VX_dcache_rsp (Verilated::catName(topp->name(),"v.VX_dcache_rsp"))
, TOP__v__VX_dram_req_rsp (Verilated::catName(topp->name(),"v.VX_dram_req_rsp"))
, TOP__v__VX_dram_req_rsp_icache (Verilated::catName(topp->name(),"v.VX_dram_req_rsp_icache"))
, TOP__v__VX_icache_req (Verilated::catName(topp->name(),"v.VX_icache_req"))
, TOP__v__VX_icache_rsp (Verilated::catName(topp->name(),"v.VX_icache_rsp"))
, TOP__v__dmem_controller (Verilated::catName(topp->name(),"v.dmem_controller"))
{
// Pointer to top level
TOPp = topp;
// Setup each module's pointers to their submodules
TOPp->__PVT__v = &TOP__v;
TOPp->__PVT__v->__PVT__VX_dcache_req = &TOP__v__VX_dcache_req;
TOPp->__PVT__v->__PVT__VX_dcache_rsp = &TOP__v__VX_dcache_rsp;
TOPp->__PVT__v->__PVT__VX_dram_req_rsp = &TOP__v__VX_dram_req_rsp;
TOPp->__PVT__v->__PVT__VX_dram_req_rsp_icache = &TOP__v__VX_dram_req_rsp_icache;
TOPp->__PVT__v->__PVT__VX_icache_req = &TOP__v__VX_icache_req;
TOPp->__PVT__v->__PVT__VX_icache_rsp = &TOP__v__VX_icache_rsp;
TOPp->__PVT__v->__PVT__dmem_controller = &TOP__v__dmem_controller;
// Setup each module's pointer back to symbol table (for public functions)
TOPp->__Vconfigure(this, true);
TOP__v.__Vconfigure(this, true);
TOP__v__VX_dcache_req.__Vconfigure(this, true);
TOP__v__VX_dcache_rsp.__Vconfigure(this, true);
TOP__v__VX_dram_req_rsp.__Vconfigure(this, true);
TOP__v__VX_dram_req_rsp_icache.__Vconfigure(this, true);
TOP__v__VX_icache_req.__Vconfigure(this, true);
TOP__v__VX_icache_rsp.__Vconfigure(this, true);
TOP__v__dmem_controller.__Vconfigure(this, true);
// Setup scope names
}

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Symbol table internal header
//
// Internal details; most calling programs do not need this header
#ifndef _Vcache_simX__Syms_H_
#define _Vcache_simX__Syms_H_
#include "verilated.h"
// INCLUDE MODULE CLASSES
#include "Vcache_simX.h"
#include "Vcache_simX_cache_simX.h"
#include "Vcache_simX_VX_dmem_controller__V0_VB1000.h"
#include "Vcache_simX_VX_icache_request_inter.h"
#include "Vcache_simX_VX_icache_response_inter.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
#include "Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
#include "Vcache_simX_VX_dcache_request_inter.h"
#include "Vcache_simX_VX_dcache_response_inter.h"
// SYMS CLASS
class Vcache_simX__Syms : public VerilatedSyms {
public:
// LOCAL STATE
const char* __Vm_namep;
bool __Vm_activity; ///< Used by trace routines to determine change occurred
bool __Vm_didInit;
//char __VpadToAlign10[6];
// SUBCELL STATE
Vcache_simX* TOPp;
Vcache_simX_cache_simX TOP__v;
Vcache_simX_VX_dcache_request_inter TOP__v__VX_dcache_req;
Vcache_simX_VX_dcache_response_inter TOP__v__VX_dcache_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 TOP__v__VX_dram_req_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 TOP__v__VX_dram_req_rsp_icache;
Vcache_simX_VX_icache_request_inter TOP__v__VX_icache_req;
Vcache_simX_VX_icache_response_inter TOP__v__VX_icache_rsp;
Vcache_simX_VX_dmem_controller__V0_VB1000 TOP__v__dmem_controller;
// COVERAGE
// SCOPE NAMES
// CREATORS
Vcache_simX__Syms(Vcache_simX* topp, const char* namep);
~Vcache_simX__Syms() {};
// METHODS
inline const char* name() { return __Vm_namep; }
inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r;}
} VL_ATTR_ALIGNED(64);
#endif /*guard*/

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obj_dir/Vcache_simX.cpp obj_dir/Vcache_simX.h obj_dir/Vcache_simX.mk obj_dir/Vcache_simX_VX_dcache_request_inter.cpp obj_dir/Vcache_simX_VX_dcache_request_inter.h obj_dir/Vcache_simX_VX_dcache_response_inter.cpp obj_dir/Vcache_simX_VX_dcache_response_inter.h obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.cpp obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h obj_dir/Vcache_simX_VX_icache_request_inter.cpp obj_dir/Vcache_simX_VX_icache_request_inter.h obj_dir/Vcache_simX_VX_icache_response_inter.cpp obj_dir/Vcache_simX_VX_icache_response_inter.h obj_dir/Vcache_simX__Inlines.h obj_dir/Vcache_simX__Syms.cpp obj_dir/Vcache_simX__Syms.h obj_dir/Vcache_simX__Trace.cpp obj_dir/Vcache_simX__Trace__Slow.cpp obj_dir/Vcache_simX__ver.d obj_dir/Vcache_simX_cache_simX.cpp obj_dir/Vcache_simX_cache_simX.h obj_dir/Vcache_simX_classes.mk : /usr/bin/verilator_bin ../rtl/./VX_define_synth.v ../rtl/VX_countones.v ../rtl/VX_define.v ../rtl/VX_dmem_controller.v ../rtl/VX_generic_priority_encoder.v ../rtl/VX_priority_encoder_w_mask.v ../rtl/cache/VX_Cache_Bank.v ../rtl/cache/VX_cache_bank_valid.v ../rtl/cache/VX_cache_data.v ../rtl/cache/VX_cache_data_per_index.v ../rtl/cache/VX_d_cache.v ../rtl/interfaces/VX_dcache_request_inter.v ../rtl/interfaces/VX_dcache_response_inter.v ../rtl/interfaces/VX_dram_req_rsp_inter.v ../rtl/interfaces/VX_icache_request_inter.v ../rtl/interfaces/VX_icache_response_inter.v ../rtl/shared_memory/../VX_define.v ../rtl/shared_memory/VX_bank_valids.v ../rtl/shared_memory/VX_priority_encoder_sm.v ../rtl/shared_memory/VX_shared_memory.v ../rtl/shared_memory/VX_shared_memory_block.v /usr/bin/verilator_bin cache_simX.v

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# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
C "--compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS -std=c++11 -fPIC -O3 -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1"
S 26 40239138 1574470136 "../rtl/./VX_define_synth.v"
S 283 40239133 1574470136 "../rtl/VX_countones.v"
S 7240 40239137 1574470136 "../rtl/VX_define.v"
S 8325 40239139 1574470136 "../rtl/VX_dmem_controller.v"
S 517 40239143 1574470136 "../rtl/VX_generic_priority_encoder.v"
S 683 40239154 1574470136 "../rtl/VX_priority_encoder_w_mask.v"
S 8590 40239164 1574470136 "../rtl/cache/VX_Cache_Bank.v"
S 748 40239165 1574470136 "../rtl/cache/VX_cache_bank_valid.v"
S 7349 40239166 1574470136 "../rtl/cache/VX_cache_data.v"
S 6476 40239167 1574470136 "../rtl/cache/VX_cache_data_per_index.v"
S 14645 40239168 1574470136 "../rtl/cache/VX_d_cache.v"
S 393 40239180 1574470136 "../rtl/interfaces/VX_dcache_request_inter.v"
S 215 40239181 1574470136 "../rtl/interfaces/VX_dcache_response_inter.v"
S 870 40239182 1574470136 "../rtl/interfaces/VX_dram_req_rsp_inter.v"
S 354 40239191 1574470136 "../rtl/interfaces/VX_icache_request_inter.v"
S 212 40239192 1574470136 "../rtl/interfaces/VX_icache_response_inter.v"
S 7240 40239137 1574470136 "../rtl/shared_memory/../VX_define.v"
S 676 40239236 1574470136 "../rtl/shared_memory/VX_bank_valids.v"
S 3038 40239237 1574470136 "../rtl/shared_memory/VX_priority_encoder_sm.v"
S 4962 40239238 1574470136 "../rtl/shared_memory/VX_shared_memory.v"
S 3207 40239239 1574470136 "../rtl/shared_memory/VX_shared_memory_block.v"
S 4117944 1442940 1433741508 "/usr/bin/verilator_bin"
S 3144 40239440 1574470137 "cache_simX.v"
T 9461 40501257 1574470340 "obj_dir/Vcache_simX.cpp"
T 5060 40501256 1574470340 "obj_dir/Vcache_simX.h"
T 2505 40501275 1574470341 "obj_dir/Vcache_simX.mk"
T 836 40501271 1574470341 "obj_dir/Vcache_simX_VX_dcache_request_inter.cpp"
T 1627 40501270 1574470341 "obj_dir/Vcache_simX_VX_dcache_request_inter.h"
T 721 40501273 1574470341 "obj_dir/Vcache_simX_VX_dcache_response_inter.cpp"
T 1529 40501272 1574470341 "obj_dir/Vcache_simX_VX_dcache_response_inter.h"
T 1690042 40501261 1574470341 "obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.cpp"
T 145427 40501260 1574470340 "obj_dir/Vcache_simX_VX_dmem_controller__V0_VB1000.h"
T 792 40501269 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.cpp"
T 1615 40501268 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N1_NB4.h"
T 792 40501267 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.cpp"
T 1616 40501266 1574470341 "obj_dir/Vcache_simX_VX_dram_req_rsp_inter__N4_NB4.h"
T 716 40501263 1574470341 "obj_dir/Vcache_simX_VX_icache_request_inter.cpp"
T 1520 40501262 1574470341 "obj_dir/Vcache_simX_VX_icache_request_inter.h"
T 721 40501265 1574470341 "obj_dir/Vcache_simX_VX_icache_response_inter.cpp"
T 1529 40501264 1574470341 "obj_dir/Vcache_simX_VX_icache_response_inter.h"
T 735 40501251 1574470340 "obj_dir/Vcache_simX__Inlines.h"
T 2656 40501253 1574470340 "obj_dir/Vcache_simX__Syms.cpp"
T 1907 40501252 1574470340 "obj_dir/Vcache_simX__Syms.h"
T 656053 40501255 1574470340 "obj_dir/Vcache_simX__Trace.cpp"
T 854791 40501254 1574470340 "obj_dir/Vcache_simX__Trace__Slow.cpp"
T 1868 40501276 1574470341 "obj_dir/Vcache_simX__ver.d"
T 0 0 1574470341 "obj_dir/Vcache_simX__verFiles.dat"
T 5999 40501259 1574470340 "obj_dir/Vcache_simX_cache_simX.cpp"
T 2955 40501258 1574470340 "obj_dir/Vcache_simX_cache_simX.h"
T 1488 40501274 1574470341 "obj_dir/Vcache_simX_classes.mk"

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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See Vcache_simX.h for the primary calling header
#include "Vcache_simX_cache_simX.h" // For This
#include "Vcache_simX__Syms.h"
//--------------------
// STATIC VARIABLES
//--------------------
VL_CTOR_IMP(Vcache_simX_cache_simX) {
VL_CELL (__PVT__VX_icache_req, Vcache_simX_VX_icache_request_inter);
VL_CELL (__PVT__VX_icache_rsp, Vcache_simX_VX_icache_response_inter);
VL_CELL (__PVT__VX_dram_req_rsp_icache, Vcache_simX_VX_dram_req_rsp_inter__N1_NB4);
VL_CELL (__PVT__VX_dcache_req, Vcache_simX_VX_dcache_request_inter);
VL_CELL (__PVT__VX_dcache_rsp, Vcache_simX_VX_dcache_response_inter);
VL_CELL (__PVT__VX_dram_req_rsp, Vcache_simX_VX_dram_req_rsp_inter__N4_NB4);
VL_CELL (__PVT__dmem_controller, Vcache_simX_VX_dmem_controller__V0_VB1000);
// Reset internal values
// Reset structure values
clk = VL_RAND_RESET_I(1);
reset = VL_RAND_RESET_I(1);
in_icache_pc_addr = VL_RAND_RESET_I(32);
in_icache_valid_pc_addr = VL_RAND_RESET_I(1);
out_icache_stall = VL_RAND_RESET_I(1);
in_dcache_mem_read = VL_RAND_RESET_I(3);
in_dcache_mem_write = VL_RAND_RESET_I(3);
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_dcache_in_valid[__Vi0] = VL_RAND_RESET_I(1);
}}
{ int __Vi0=0; for (; __Vi0<4; ++__Vi0) {
in_dcache_in_address[__Vi0] = VL_RAND_RESET_I(32);
}}
out_dcache_stall = VL_RAND_RESET_I(1);
__PVT__icache_i_m_ready = VL_RAND_RESET_I(1);
__PVT__dcache_i_m_ready = VL_RAND_RESET_I(1);
}
void Vcache_simX_cache_simX::__Vconfigure(Vcache_simX__Syms* vlSymsp, bool first) {
if (0 && first) {} // Prevent unused
this->__VlSymsp = vlSymsp;
}
Vcache_simX_cache_simX::~Vcache_simX_cache_simX() {
}
//--------------------
// Internal Methods
void Vcache_simX_cache_simX::_settle__TOP__v__1(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX_cache_simX::_settle__TOP__v__1\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xeU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| vlSymsp->TOP__v.in_dcache_in_valid[0U]);
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xdU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[1U]
<< 1U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xbU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[2U]
<< 2U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((7U & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[3U]
<< 3U));
}
VL_INLINE_OPT void Vcache_simX_cache_simX::_sequent__TOP__v__2(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX_cache_simX::_sequent__TOP__v__2\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
// ALWAYS at cache_simX.v:93
if (vlTOPp->reset) {
vlSymsp->TOP__v.__PVT__icache_i_m_ready = 0U;
vlSymsp->TOP__v.__PVT__dcache_i_m_ready = 0U;
} else {
vlSymsp->TOP__v.__PVT__icache_i_m_ready = (1U
== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__icache__DOT__state));
vlSymsp->TOP__v.__PVT__dcache_i_m_ready = (1U
== (IData)(vlSymsp->TOP__v__dmem_controller.__PVT__dcache__DOT__state));
}
}
VL_INLINE_OPT void Vcache_simX_cache_simX::_combo__TOP__v__3(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX_cache_simX::_combo__TOP__v__3\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xeU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| vlSymsp->TOP__v.in_dcache_in_valid[0U]);
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xdU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[1U]
<< 1U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((0xbU & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[2U]
<< 2U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid
= ((7U & (IData)(vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_valid))
| (vlSymsp->TOP__v.in_dcache_in_valid[3U]
<< 3U));
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U]
= vlSymsp->TOP__v.in_dcache_in_address[0U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U]
= vlSymsp->TOP__v.in_dcache_in_address[1U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[2U]
= vlSymsp->TOP__v.in_dcache_in_address[2U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[3U]
= vlSymsp->TOP__v.in_dcache_in_address[3U];
}
void Vcache_simX_cache_simX::_settle__TOP__v__4(Vcache_simX__Syms* __restrict vlSymsp) {
VL_DEBUG_IF(VL_PRINTF(" Vcache_simX_cache_simX::_settle__TOP__v__4\n"); );
Vcache_simX* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
// Body
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[0U]
= vlSymsp->TOP__v.in_dcache_in_address[0U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[1U]
= vlSymsp->TOP__v.in_dcache_in_address[1U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[2U]
= vlSymsp->TOP__v.in_dcache_in_address[2U];
vlSymsp->TOP__v__VX_dcache_req.__PVT__out_cache_driver_in_address[3U]
= vlSymsp->TOP__v.in_dcache_in_address[3U];
}

84
simX/obj_dir/Vcache_simX_cache_simX.h
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// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design internal header
// See Vcache_simX.h for the primary calling header
#ifndef _Vcache_simX_cache_simX_H_
#define _Vcache_simX_cache_simX_H_
#include "verilated.h"
#include "Vcache_simX__Inlines.h"
class Vcache_simX__Syms;
class Vcache_simX_VX_icache_request_inter;
class Vcache_simX_VX_icache_response_inter;
class Vcache_simX_VX_dram_req_rsp_inter__N1_NB4;
class Vcache_simX_VX_dcache_request_inter;
class Vcache_simX_VX_dcache_response_inter;
class Vcache_simX_VX_dram_req_rsp_inter__N4_NB4;
class Vcache_simX_VX_dmem_controller__V0_VB1000;
class VerilatedVcd;
//----------
VL_MODULE(Vcache_simX_cache_simX) {
public:
// CELLS
Vcache_simX_VX_icache_request_inter* __PVT__VX_icache_req;
Vcache_simX_VX_icache_response_inter* __PVT__VX_icache_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4* __PVT__VX_dram_req_rsp_icache;
Vcache_simX_VX_dcache_request_inter* __PVT__VX_dcache_req;
Vcache_simX_VX_dcache_response_inter* __PVT__VX_dcache_rsp;
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4* __PVT__VX_dram_req_rsp;
Vcache_simX_VX_dmem_controller__V0_VB1000* __PVT__dmem_controller;
// PORTS
VL_IN8(clk,0,0);
VL_IN8(reset,0,0);
VL_IN8(in_icache_valid_pc_addr,0,0);
VL_OUT8(out_icache_stall,0,0);
VL_IN8(in_dcache_mem_read,2,0);
VL_IN8(in_dcache_mem_write,2,0);
VL_OUT8(out_dcache_stall,0,0);
//char __VpadToAlign7[1];
VL_IN(in_icache_pc_addr,31,0);
VL_IN8(in_dcache_in_valid[4],0,0);
VL_IN(in_dcache_in_address[4],31,0);
// LOCAL SIGNALS
VL_SIG8(__PVT__icache_i_m_ready,0,0);
VL_SIG8(__PVT__dcache_i_m_ready,0,0);
//char __VpadToAlign38[2];
// LOCAL VARIABLES
// INTERNAL VARIABLES
private:
Vcache_simX__Syms* __VlSymsp; // Symbol table
public:
// PARAMETERS
// CONSTRUCTORS
private:
Vcache_simX_cache_simX& operator= (const Vcache_simX_cache_simX&); ///< Copying not allowed
Vcache_simX_cache_simX(const Vcache_simX_cache_simX&); ///< Copying not allowed
public:
Vcache_simX_cache_simX(const char* name="TOP");
~Vcache_simX_cache_simX();
void trace (VerilatedVcdC* tfp, int levels, int options=0);
// USER METHODS
// API METHODS
// INTERNAL METHODS
void __Vconfigure(Vcache_simX__Syms* symsp, bool first);
static void _combo__TOP__v__3(Vcache_simX__Syms* __restrict vlSymsp);
static void _sequent__TOP__v__2(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__v__1(Vcache_simX__Syms* __restrict vlSymsp);
static void _settle__TOP__v__4(Vcache_simX__Syms* __restrict vlSymsp);
static void traceInit (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceFull (VerilatedVcd* vcdp, void* userthis, uint32_t code);
static void traceChg (VerilatedVcd* vcdp, void* userthis, uint32_t code);
} VL_ATTR_ALIGNED(128);
#endif /*guard*/

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simX/obj_dir/Vcache_simX_classes.mk
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# Verilated -*- Makefile -*-
# DESCRIPTION: Verilator output: Make include file with class lists
#
# This file lists generated Verilated files, for including in higher level makefiles.
# See Vcache_simX.mk for the caller.
### Switches...
# Coverage output mode? 0/1 (from --coverage)
VM_COVERAGE = 0
# Tracing output mode? 0/1 (from --trace)
VM_TRACE = 1
### Object file lists...
# Generated module classes, fast-path, compile with highest optimization
VM_CLASSES_FAST += \
Vcache_simX \
Vcache_simX_cache_simX \
Vcache_simX_VX_dmem_controller__V0_VB1000 \
Vcache_simX_VX_icache_request_inter \
Vcache_simX_VX_icache_response_inter \
Vcache_simX_VX_dram_req_rsp_inter__N4_NB4 \
Vcache_simX_VX_dram_req_rsp_inter__N1_NB4 \
Vcache_simX_VX_dcache_request_inter \
Vcache_simX_VX_dcache_response_inter \
# Generated module classes, non-fast-path, compile with low/medium optimization
VM_CLASSES_SLOW += \
# Generated support classes, fast-path, compile with highest optimization
VM_SUPPORT_FAST += \
Vcache_simX__Trace \
# Generated support classes, non-fast-path, compile with low/medium optimization
VM_SUPPORT_SLOW += \
Vcache_simX__Syms \
Vcache_simX__Trace__Slow \
# Global classes, need linked once per executable, fast-path, compile with highest optimization
VM_GLOBAL_FAST += \
verilated \
verilated_vcd_c \
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
VM_GLOBAL_SLOW += \
# Verilated -*- Makefile -*-

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simX/obj_dir/args.d
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args.o: ../args.cpp ../include/args.h

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simX/obj_dir/core.d
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core.o: ../core.cpp ../include/types.h ../include/util.h \
../include/types.h ../include/archdef.h ../include/mem.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/archdef.h ../include/enc.h \
../include/asm-tokens.h ../include/core.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
/usr/share/verilator/include/verilated_vcd_c.h ../include/debug.h

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simX/obj_dir/enc.d
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enc.o: ../enc.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/archdef.h \
../include/enc.h ../include/asm-tokens.h ../include/archdef.h \
../include/instruction.h

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simX/obj_dir/instruction.d
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instruction.o: ../instruction.cpp ../include/instruction.h \
../include/types.h ../include/trace.h ../include/obj.h \
../include/archdef.h ../include/instruction.h ../include/enc.h \
../include/obj.h ../include/asm-tokens.h ../include/core.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
/usr/share/verilator/include/verilated_vcd_c.h ../include/harpfloat.h \
../include/debug.h

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simX/obj_dir/mem.d
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mem.o: ../mem.cpp ../include/debug.h ../include/types.h ../include/util.h \
../include/types.h ../include/mem.h ../include/core.h \
../include/archdef.h ../include/enc.h ../include/instruction.h \
../include/trace.h ../include/obj.h ../include/asm-tokens.h \
../include/mem.h ../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
/usr/share/verilator/include/verilated_vcd_c.h

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simX/obj_dir/simX.d
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simX.o: ../simX.cpp ../include/debug.h ../include/types.h \
../include/core.h ../include/types.h ../include/archdef.h \
../include/enc.h ../include/instruction.h ../include/trace.h \
../include/obj.h ../include/asm-tokens.h ../include/mem.h \
../include/debug.h Vcache_simX.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilatedos.h Vcache_simX__Inlines.h \
/usr/share/verilator/include/verilated_vcd_c.h ../include/enc.h \
../include/instruction.h ../include/mem.h ../include/obj.h \
../include/archdef.h ../include/args.h ../include/help.h

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simX/obj_dir/util.d
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util.o: ../util.cpp ../include/types.h ../include/util.h \
../include/types.h

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simX/obj_dir/verilated.d
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verilated.o: /usr/share/verilator/include/verilated.cpp \
/usr/share/verilator/include/verilated_imp.h \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_heavy.h \
/usr/share/verilator/include/verilated_syms.h

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simX/obj_dir/verilated_vcd_c.d
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verilated_vcd_c.o: /usr/share/verilator/include/verilated_vcd_c.cpp \
/usr/share/verilator/include/verilatedos.h \
/usr/share/verilator/include/verilated.h \
/usr/share/verilator/include/verilated_config.h \
/usr/share/verilator/include/verilated_vcd_c.h

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verilator --compiler gcc -cc cache_simX.v -I. -I../rtl/shared_memory -I../rtl/cache -I../rtl/interfaces -Isimulate -I../rtl --exe simX.cpp args.cpp mem.cpp core.cpp instruction.cpp enc.cpp util.cpp -CFLAGS '-std=c++11 -fPIC -O3' -Wno-UNOPTFLAT -Wno-WIDTH --trace -DVL_DEBUG=1
Makefile:26: recipe for target 'simX' failed