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xilinx synthesis debugging foxes

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This commit is contained in:
Blaise Tine 2024-09-17 06:22:07 -07:00
parent bbe9c0372f
commit 50458bbae0
21 changed files with 710 additions and 413 deletions
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2
configure vendored
View file

@ -65,7 +65,7 @@ copy_files() {
filename_no_ext="${filename%.in}" filename_no_ext="${filename%.in}"
dest_file="$dest_dir/$filename_no_ext" dest_file="$dest_dir/$filename_no_ext"
mkdir -p "$dest_dir" mkdir -p "$dest_dir"
sed "s|@VORTEX_HOME@|$SCRIPT_DIR|g; s|@XLEN@|$XLEN|g; s|@TOOLDIR@|$TOOLDIR|g; s|@OSVERSION@|$OSVERSION|g; s|@INSTALLDIR@|$PREFIX|g" "$file" > "$dest_file" sed "s|@VORTEX_HOME@|$SCRIPT_DIR|g; s|@XLEN@|$XLEN|g; s|@TOOLDIR@|$TOOLDIR|g; s|@OSVERSION@|$OSVERSION|g; s|@INSTALLDIR@|$PREFIX|g; s|@CURRENTDIR@|$CURRENT_DIR|g" "$file" > "$dest_file"
# apply permissions to bash scripts # apply permissions to bash scripts
read -r firstline < "$dest_file" read -r firstline < "$dest_file"
if [[ "$firstline" =~ ^#!.*bash ]]; then if [[ "$firstline" =~ ^#!.*bash ]]; then

17
hw/rtl/VX_platform.vh
View file

@ -56,8 +56,25 @@
`define UNUSED_PIN(x) . x () `define UNUSED_PIN(x) . x ()
`define UNUSED_ARG(x) x `define UNUSED_ARG(x) x
`define __SCOPE (* mark_debug="true" *)
`define __SCOPE_X
`define __SCOPE_ON \
`undef __SCOPE_X \
`define __SCOPE_X `__SCOPE
`define __SCOPE_OFF \
`undef __SCOPE_X \
`define __SCOPE_X
`else // not SYNTHESIS `else // not SYNTHESIS
`define __SCOPE
`define __SCOPE_X
`define __SCOPE_ON
`define __SCOPE_OFF
`ifdef VERILATOR `ifdef VERILATOR
`ifndef TRACING_ALL `ifndef TRACING_ALL

39
hw/rtl/afu/xrt/VX_afu_wrap.sv
View file

@ -21,8 +21,8 @@ module VX_afu_wrap #(
parameter C_M_AXI_MEM_DATA_WIDTH = `VX_MEM_DATA_WIDTH parameter C_M_AXI_MEM_DATA_WIDTH = `VX_MEM_DATA_WIDTH
) ( ) (
// System signals // System signals
input wire ap_clk, input wire clk,
input wire ap_rst_n, input wire reset,
// AXI4 master interface // AXI4 master interface
`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA), `REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
@ -82,8 +82,6 @@ module VX_afu_wrap #(
// convert memory interface to array // convert memory interface to array
`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON); `REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
wire reset = ~ap_rst_n;
reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr; reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
reg [15:0] vx_pending_writes; reg [15:0] vx_pending_writes;
reg vx_busy_wait; reg vx_busy_wait;
@ -122,7 +120,7 @@ module VX_afu_wrap #(
end end
end end
always @(posedge ap_clk) begin always @(posedge clk) begin
if (reset || ap_reset) begin if (reset || ap_reset) begin
state <= STATE_IDLE; state <= STATE_IDLE;
vx_pending_writes <= '0; vx_pending_writes <= '0;
@ -187,7 +185,7 @@ module VX_afu_wrap #(
.AXI_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH), .AXI_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH),
.AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS) .AXI_NUM_BANKS (C_M_AXI_MEM_NUM_BANKS)
) afu_ctrl ( ) afu_ctrl (
.clk (ap_clk), .clk (clk),
.reset (reset), .reset (reset),
.s_axi_awvalid (s_axi_ctrl_awvalid), .s_axi_awvalid (s_axi_ctrl_awvalid),
@ -245,7 +243,7 @@ module VX_afu_wrap #(
) vortex_axi ( ) vortex_axi (
`SCOPE_IO_BIND (1) `SCOPE_IO_BIND (1)
.clk (ap_clk), .clk (clk),
.reset (vx_reset), .reset (vx_reset),
.m_axi_awvalid (m_axi_mem_awvalid_a), .m_axi_awvalid (m_axi_mem_awvalid_a),
@ -301,9 +299,32 @@ module VX_afu_wrap #(
// SCOPE ////////////////////////////////////////////////////////////////////// // SCOPE //////////////////////////////////////////////////////////////////////
`ifdef CHIPSCOPE
ila_afu ila_afu_inst (
.clk (clk),
.probe0 ({
ap_reset,
ap_start,
ap_done,
ap_idle,
interrupt
}),
.probe1 ({
vx_pending_writes,
vx_busy_wait,
vx_busy,
vx_reset,
dcr_wr_valid,
dcr_wr_addr,
dcr_wr_data
})
);
`endif
`ifdef DBG_SCOPE_AFU `ifdef DBG_SCOPE_AFU
`define TRIGGERS { \ `define TRIGGERS { \
reset, \ reset, \
ap_reset, \
ap_start, \ ap_start, \
ap_done, \ ap_done, \
ap_idle, \ ap_idle, \
@ -343,7 +364,7 @@ module VX_afu_wrap #(
initial begin initial begin
$assertoff(0, vortex_axi); $assertoff(0, vortex_axi);
end end
always @(posedge ap_clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
assert_delay_ctr <= '0; assert_delay_ctr <= '0;
assert_enabled <= 0; assert_enabled <= 0;
@ -362,7 +383,7 @@ module VX_afu_wrap #(
`endif `endif
`ifdef DBG_TRACE_AFU `ifdef DBG_TRACE_AFU
always @(posedge ap_clk) begin always @(posedge clk) begin
for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin for (integer i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin
if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin if (m_axi_mem_awvalid_a[i] && m_axi_mem_awready_a[i]) begin
`TRACE(2, ("%t: AFU Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i])) `TRACE(2, ("%t: AFU Wr Req [%0d]: addr=0x%0h, tag=0x%0h\n", $time, i, m_axi_mem_awaddr_a[i], m_axi_mem_awid_a[i]))

22
hw/rtl/afu/xrt/vortex_afu.v
View file

@ -1,10 +1,10 @@
// Copyright © 2019-2023 // Copyright © 2019-2023
// //
// Licensed under the Apache License, Version 2.0 (the "License"); // Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License. // you may not use this file except in compliance with the License.
// You may obtain a copy of the License at // You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0 // http://www.apache.org/licenses/LICENSE-2.0
// //
// Unless required by applicable law or agreed to in writing, software // Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS, // distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -18,12 +18,12 @@ module vortex_afu #(
parameter C_S_AXI_CTRL_DATA_WIDTH = 32, parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
parameter C_M_AXI_MEM_ID_WIDTH = `M_AXI_MEM_ID_WIDTH, parameter C_M_AXI_MEM_ID_WIDTH = `M_AXI_MEM_ID_WIDTH,
parameter C_M_AXI_MEM_ADDR_WIDTH = 64, parameter C_M_AXI_MEM_ADDR_WIDTH = 64,
parameter C_M_AXI_MEM_DATA_WIDTH = `VX_MEM_DATA_WIDTH parameter C_M_AXI_MEM_DATA_WIDTH = `VX_MEM_DATA_WIDTH
) ( ) (
// System signals // System signals
input wire ap_clk, input wire ap_clk,
input wire ap_rst_n, input wire ap_rst_n,
// AXI4 master interface // AXI4 master interface
`REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA), `REPEAT (`M_AXI_MEM_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
@ -45,8 +45,8 @@ module vortex_afu #(
output wire s_axi_ctrl_bvalid, output wire s_axi_ctrl_bvalid,
input wire s_axi_ctrl_bready, input wire s_axi_ctrl_bready,
output wire [1:0] s_axi_ctrl_bresp, output wire [1:0] s_axi_ctrl_bresp,
output wire interrupt output wire interrupt
); );
VX_afu_wrap #( VX_afu_wrap #(
@ -56,14 +56,14 @@ module vortex_afu #(
.C_M_AXI_MEM_ADDR_WIDTH (C_M_AXI_MEM_ADDR_WIDTH), .C_M_AXI_MEM_ADDR_WIDTH (C_M_AXI_MEM_ADDR_WIDTH),
.C_M_AXI_MEM_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH) .C_M_AXI_MEM_DATA_WIDTH (C_M_AXI_MEM_DATA_WIDTH)
) afu_wrap ( ) afu_wrap (
.ap_clk (ap_clk), .clk (ap_clk),
.ap_rst_n (ap_rst_n), .reset (~ap_rst_n),
`REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA), `REPEAT (`M_AXI_MEM_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid), .s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
.s_axi_ctrl_awready (s_axi_ctrl_awready), .s_axi_ctrl_awready (s_axi_ctrl_awready),
.s_axi_ctrl_awaddr (s_axi_ctrl_awaddr), .s_axi_ctrl_awaddr (s_axi_ctrl_awaddr),
.s_axi_ctrl_wvalid (s_axi_ctrl_wvalid), .s_axi_ctrl_wvalid (s_axi_ctrl_wvalid),
.s_axi_ctrl_wready (s_axi_ctrl_wready), .s_axi_ctrl_wready (s_axi_ctrl_wready),
.s_axi_ctrl_wdata (s_axi_ctrl_wdata), .s_axi_ctrl_wdata (s_axi_ctrl_wdata),
@ -81,5 +81,5 @@ module vortex_afu #(
.interrupt (interrupt) .interrupt (interrupt)
); );
endmodule endmodule

0
hw/scripts/ip_gen.sh → hw/scripts/altera_ip_gen.sh
View file

231
hw/scripts/ila_insert.tcl Normal file
View file

@ -0,0 +1,231 @@
######################################################################
# Automatically inserts ILA instances in a batch flow, and calls "implement_debug_core". Can also be used in a GUI flow
# This should ONLY be invoked after synthesis, and before opt_design. If opt_design is called first, marked nets may be missing and not found
# Warning: Currently will skip a net if it has no obvious clock domain on the driver. Nets connected to input buffers will be dropped unless "mark_debug_clock" is attached to the net.
# Nets attached to VIO cores have the "mark_debug" attribute, and will be filtered out unless the "mark_debug_valid" attribute is attached.
# Supports the following additional attributes beyond "mark_debug"
# attribute mark_debug_valid of X : signal is "true"; -- Marks a net for ILA capture, even if net is also attached to a VIO core
# attribute mark_debug_clock of X : signal is "inst1_bufg/clock"; -- Specifies clock net to use for capturing this net. May create a new ILA core for that clock domain
# attribute mark_debug_depth of X : signal is "4096"; -- overrides default depth for this ILA core. valid values: 1024, 2048, ... 132072. Last attribute that is scanned will win.
# attribute mark_debug_adv_trigger of X : signal is "true"; -- specifies that advanced trigger capability will be added to ILA core
# Engineer: J. McCluskey
proc insert_ila { depth } {
# sequence through debug nets and organize them by clock in the
# clock_list array. Also create max and min array for bus indices
set dbgs [get_nets -hierarchical -filter {MARK_DEBUG}]
if {[llength $dbgs] == 0} {
puts "No debug net found. No ILA cores created"
return
}
# process list of nets to find and reject nets that are attached to VIO cores.
# This has a side effect that VIO nets can't be monitored with an ILA
# This can be overridden by using the attribute "mark_debug_valid" = "true" on a net like this.
set net_list {}
foreach net $dbgs {
if { [get_property -quiet MARK_DEBUG_VALID $net] != "true" } {
set pin_list [get_pins -of_objects [get_nets -segments $net]]
set not_vio_net 1
foreach pin $pin_list {
if { [get_property IS_DEBUG_CORE [get_cells -of_object $pin]] == 1 } {
# It seems this net is attached to a debug core (i.e. VIO core) already, so we should skip adding it to the netlist
set not_vio_net 0
break
}
}
if { $not_vio_net == 1 } { lappend net_list $net; }
} else {
lappend net_list $net
}
}
# check again to see if we have any nets left now
if {[llength $net_list] == 0} {
puts "All nets with MARK_DEBUG are already connected to VIO cores. No ILA cores created"
return
}
# Now that the netlist has been filtered, determine bus names and clock domains
foreach d $net_list {
# name is root name of a bus, index is the bit index in the bus
set name [regsub {\[[[:digit:]]+\]$} $d {}]
set index [regsub {^.*\[([[:digit:]]+)\]$} $d {\1}]
if {[string is integer -strict $index]} {
if {![info exists max($name)]} {
set max($name) $index
set min($name) $index
} elseif {$index > $max($name)} {
set max($name) $index
} elseif {$index < $min($name)} {
set min($name) $index
}
} else {
set max($name) -1
}
# Now we search for the local clock net associated with the target net.
# There may be ambiguities or no answer in some cases
if {![info exists clocks($name)]} {
# does MARK_DEBUG_CLOCK decorate this net? If not, then search backwards to the driver cell
set clk_name [get_property -quiet MARK_DEBUG_CLOCK $d]
if { [llength $clk_name] == 0 } {
# trace to the clock net, tracing backwards via the driver pin.
set driver_pin [get_pins -filter {DIRECTION == "OUT" && IS_LEAF == TRUE } -of_objects [ get_nets -segments $d ]]
set driver_cell [get_cells -of_objects $driver_pin]
if { [get_property IS_SEQUENTIAL $driver_cell] == 1 } {
set timing_arc [get_timing_arcs -to $driver_pin]
set cell_clock_pin [get_pins -filter {IS_CLOCK} [get_property FROM_PIN $timing_arc]]
if { [llength $cell_clock_pin] > 1 } {
puts "Error: in insert_ila. Found more than 1 clock pin in driver cell $driver_cell with timing arc $timing_arc for net $d"
continue
}
} else {
# our driver cell is a LUT or LUTMEM in combinatorial mode, we need to trace further.
set paths [get_timing_paths -quiet -through $driver_pin ]
if { [llength $paths] > 0 } {
# note that here we arbitrarily select the start point of the FIRST timing path... there might be multiple clocks with timing paths for this net.
# use MARK_DEBUG_CLOCK to specify another clock in this case.
set cell_clock_pin [get_pins [get_property STARTPOINT_PIN [lindex $paths 0]]]
} else {
# Can't find any timing path, so skip the net, and warn the user.
puts "Critical Warning: from insert_ila.tcl Can't trace any clock domain on driver of net $d"
puts "Please attach the attribute MARK_DEBUG_CLOCK with a string containing the net name of the desired sampling clock, .i.e."
puts "attribute mark_debug_clock of $d : signal is \"inst_bufg/clk\";"
continue
}
}
# clk_net will usually be a list of net segments, which needs filtering to determine the net connected to the driver pin
set clk_net [get_nets -segments -of_objects $cell_clock_pin]
} else {
set clk_net [get_nets -segments $clk_name]
if { [llength $clk_net] == 0 } { puts "MARK_DEBUG_CLOCK attribute on net $d does not match any known net. Please fix."; continue; }
}
# trace forward to net actually connected to clock buffer output, not any of the lower level segment names
set clocks($name) [get_nets -of_objects [get_pins -filter {DIRECTION == "OUT" && IS_LEAF == TRUE } -of_objects $clk_net]]
if { [llength $clocks($name)] == 0 } {
puts "Critical Warning: from insert_ila.tcl Can't trace any clock domain on driver of net $d"
puts "Please attach the attribute MARK_DEBUG_CLOCK with a string containing the net name of the desired sampling clock, .i.e."
puts "attribute mark_debug_clock of $d : signal is \"inst_bufg/clk\";"
continue
}
if {![info exists clock_list($clocks($name))]} {
# found a new clock
puts "New clock found is $clocks($name)"
set clock_list($clocks($name)) [list $name]
set ila_depth($clocks($name)) $depth
set ila_adv_trigger($clocks($name)) false
} else {
lappend clock_list($clocks($name)) $name
}
# Does this net have a "MARK_DEBUG_DEPTH" attribute attached?
set clk_depth [get_property -quiet MARK_DEBUG_DEPTH $d]
if { [llength $clk_depth] != 0 } {
set ila_depth($clocks($name)) $clk_depth
}
# Does this net have a "MARK_DEBUG_ADV_TRIGGER" attribute attached?
set trigger [get_property -quiet MARK_DEBUG_ADV_TRIGGER $d]
if { $trigger == "true" } {
set ila_adv_trigger($clocks($name)) true
}
}
}
set ila_count 0
set trig_out ""
set trig_out_ack ""
if { [llength [array names clock_list]] > 1 } {
set enable_trigger true
} else {
set enable_trigger false
}
foreach c [array names clock_list] {
# Now build and connect an ILA core for each clock domain
[incr ila_count ]
set ila_inst "ila_$ila_count"
# first verify if depth is a member of the set, 1024, 2048, 4096, 8192, ... 131072
if { $ila_depth($c) < 1024 || [expr $ila_depth($c) & ($ila_depth($c) - 1)] || $ila_depth($c) > 131072 } {
# Depth is not right... lets fix it, and continue
if { $ila_depth($c) < 1024 } {
set new_depth 1024
} elseif { $ila_depth($c) > 131072 } {
set new_depth 131072
} else {
# round value to next highest power of 2, (in log space)
set new_depth [expr 1 << int( log($ila_depth($c))/log(2) + .9999 )]
}
puts "Can't create ILA core $ila_inst with depth of $ila_depth($c)! Changed capture depth to $new_depth"
set ila_depth($c) $new_depth
}
# create ILA and connect its clock
puts "Creating ILA $ila_inst with clock $c, capture depth $ila_depth($c) and advanced trigger = $ila_adv_trigger($c)"
create_debug_core $ila_inst ila
if { $ila_adv_trigger($c) } { set mu_cnt 4; } else { set mu_cnt 2; }
set_property C_DATA_DEPTH $ila_depth($c) [get_debug_cores $ila_inst]
set_property C_TRIGIN_EN $enable_trigger [get_debug_cores $ila_inst]
set_property C_TRIGOUT_EN $enable_trigger [get_debug_cores $ila_inst]
set_property C_ADV_TRIGGER $ila_adv_trigger($c) [get_debug_cores $ila_inst]
set_property C_INPUT_PIPE_STAGES 1 [get_debug_cores $ila_inst]
set_property C_EN_STRG_QUAL true [get_debug_cores $ila_inst]
set_property ALL_PROBE_SAME_MU true [get_debug_cores $ila_inst]
set_property ALL_PROBE_SAME_MU_CNT $mu_cnt [get_debug_cores $ila_inst]
set_property port_width 1 [get_debug_ports $ila_inst/clk]
connect_debug_port $ila_inst/clk $c
# hookup trigger ports in a circle if more than one ILA is created
if { $enable_trigger == true } {
create_debug_port $ila_inst trig_in
create_debug_port $ila_inst trig_in_ack
create_debug_port $ila_inst trig_out
create_debug_port $ila_inst trig_out_ack
if { $trig_out != "" } {
connect_debug_port $ila_inst/trig_in [get_nets $trig_out]
}
if { $trig_out_ack != "" } {
connect_debug_port $ila_inst/trig_in_ack [get_nets $trig_out_ack]
}
set trig_out ${ila_inst}_trig_out_$ila_count
create_net $trig_out
connect_debug_port $ila_inst/trig_out [get_nets $trig_out]
set trig_out_ack ${ila_inst}_trig_out_ack_$ila_count
create_net $trig_out_ack
connect_debug_port $ila_inst/trig_out_ack [get_nets $trig_out_ack]
}
# add probes
set nprobes 0
foreach n [lsort $clock_list($c)] {
set nets {}
if {$max($n) < 0} {
lappend nets [get_nets $n]
} else {
# n is a bus name
for {set i $min($n)} {$i <= $max($n)} {incr i} {
lappend nets [get_nets $n[$i]]
}
}
set prb probe$nprobes
if {$nprobes > 0} {
create_debug_port $ila_inst probe
}
set_property port_width [llength $nets] [get_debug_ports $ila_inst/$prb]
connect_debug_port $ila_inst/$prb $nets
incr nprobes
}
}
# at this point, we need to complete the circular connection of trigger outputs and acks
if { $enable_trigger == true } {
connect_debug_port ila_1/trig_in [get_nets $trig_out]
connect_debug_port ila_1/trig_in_ack [get_nets $trig_out_ack]
}
set project_found [get_projects -quiet]
if { $project_found != "New Project" } {
puts "Saving constraints now in project [current_project -quiet]"
save_constraints_as debug_constraints.xdc
}
# run ILA cores implementation
implement_debug_core
# write out probe info file
write_debug_probes -force debug_nets.ltx
}

0
hw/syn/xilinx/scripts/gen_ip.tcl → hw/scripts/xilinx_ip_gen.tcl
View file

2
hw/syn/altera/dut/Makefile
View file

@ -13,7 +13,7 @@ IP_CACHE_DIR := $(ROOT_DIR)/hw/syn/altera/ip_cache/$(DEVICE_FAMILY)
ip-gen: $(IP_CACHE_DIR)/ip_gen.log ip-gen: $(IP_CACHE_DIR)/ip_gen.log
$(IP_CACHE_DIR)/ip_gen.log: $(IP_CACHE_DIR)/ip_gen.log:
$(SCRIPT_DIR)/ip_gen.sh $(IP_CACHE_DIR) $(SCRIPT_DIR)/altera_ip_gen.sh $(IP_CACHE_DIR)
unittest: unittest:
mkdir -p unittest/$(BUILD_DIR) mkdir -p unittest/$(BUILD_DIR)

2
hw/syn/altera/opae/Makefile
View file

@ -102,7 +102,7 @@ all: swconfig ip-gen setup build
ip-gen: $(IP_CACHE_DIR)/ip-gen.log ip-gen: $(IP_CACHE_DIR)/ip-gen.log
$(IP_CACHE_DIR)/ip-gen.log: $(IP_CACHE_DIR)/ip-gen.log:
$(SCRIPT_DIR)/ip_gen.sh $(IP_CACHE_DIR) $(SCRIPT_DIR)/altera_ip_gen.sh $(IP_CACHE_DIR)
swconfig: vortex_afu.h swconfig: vortex_afu.h
vortex_afu.h: $(SRC_DIR)/vortex_afu.json vortex_afu.h: $(SRC_DIR)/vortex_afu.json

2
hw/syn/xilinx/README
View file

@ -5,7 +5,7 @@ platforminfo -l
xbutil validate --device 0000:09:00.1 --verbose xbutil validate --device 0000:09:00.1 --verbose
# generate FPU IPs # generate FPU IPs
vivado -mode batch -source scripts/gen_ip.tcl -tclargs ip/xilinx_u50_gen3x16_xdma_5_202210_1 vivado -mode batch -source xilinx_ip_gen.tcl -tclargs ip/xilinx_u50_gen3x16_xdma_5_202210_1
# build FPGA # build FPGA
PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_1c.log 2>&1 & PREFIX=build_base_1c NUM_CORES=1 TARGET=hw_emu PLATFORM=xilinx_u50_gen3x16_xdma_5_202210_1 make > build_u50_hw_emu_base_1c.log 2>&1 &

4
hw/syn/xilinx/dut/common.mk
View file

@ -31,9 +31,9 @@ project_1/sources.txt:
build: $(PROJECT).xpr build: $(PROJECT).xpr
$(PROJECT).xpr: project_1/sources.txt $(PROJECT).xpr: project_1/sources.txt
ifdef FPU_IP ifdef FPU_IP
MAX_JOBS=$(JOBS) FPU_IP=project_1/ip $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc $(SCRIPT_DIR) $(SRC_DIR)/../scripts MAX_JOBS=$(JOBS) FPU_IP=project_1/ip $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc $(SCRIPT_DIR)
else else
MAX_JOBS=$(JOBS) $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc $(SCRIPT_DIR) $(SRC_DIR)/../scripts MAX_JOBS=$(JOBS) $(VIVADO) -mode batch -source $(SRC_DIR)/project.tcl -tclargs $(TOP_LEVEL_ENTITY) $(DEVICE) project_1/sources.txt $(SRC_DIR)/project.xdc $(SCRIPT_DIR)
endif endif
clean: clean:

8
hw/syn/xilinx/dut/project.tcl
View file

@ -14,9 +14,9 @@
# Start time # Start time
set start_time [clock seconds] set start_time [clock seconds]
if { $::argc != 6 } { if { $::argc != 5 } {
puts "ERROR: Program \"$::argv0\" requires 5 arguments!\n" puts "ERROR: Program \"$::argv0\" requires 5 arguments!\n"
puts "Usage: $::argv0 <top_module> <device_part> <vcs_file> <xdc_file> <tool_dir> <script_dir>\n" puts "Usage: $::argv0 <top_module> <device_part> <vcs_file> <xdc_file> <tool_dir>\n"
exit exit
} }
@ -28,14 +28,12 @@ set device_part [lindex $::argv 1]
set vcs_file [lindex $::argv 2] set vcs_file [lindex $::argv 2]
set xdc_file [lindex $::argv 3] set xdc_file [lindex $::argv 3]
set tool_dir [lindex $::argv 4] set tool_dir [lindex $::argv 4]
set script_dir [lindex $::argv 5]
puts "Using top_module=$top_module" puts "Using top_module=$top_module"
puts "Using device_part=$device_part" puts "Using device_part=$device_part"
puts "Using vcs_file=$vcs_file" puts "Using vcs_file=$vcs_file"
puts "Using xdc_file=$xdc_file" puts "Using xdc_file=$xdc_file"
puts "Using tool_dir=$tool_dir" puts "Using tool_dir=$tool_dir"
puts "Using script_dir=$script_dir"
# Set the number of jobs based on MAX_JOBS environment variable # Set the number of jobs based on MAX_JOBS environment variable
if {[info exists ::env(MAX_JOBS)]} { if {[info exists ::env(MAX_JOBS)]} {
@ -50,7 +48,7 @@ if {[info exists ::env(FPU_IP)]} {
set ip_dir $::env(FPU_IP) set ip_dir $::env(FPU_IP)
set argv [list $ip_dir $device_part] set argv [list $ip_dir $device_part]
set argc 2 set argc 2
source ${script_dir}/gen_ip.tcl source ${tool_dir}/xilinx_ip_gen.tcl
} }
source "${tool_dir}/parse_vcs_list.tcl" source "${tool_dir}/parse_vcs_list.tcl"

6
hw/syn/xilinx/scripts/gen_xo.tcl → hw/syn/xilinx/gen_xo.tcl
View file

@ -1,10 +1,10 @@
# Copyright © 2019-2023 # Copyright © 2019-2023
# #
# Licensed under the Apache License, Version 2.0 (the "License"); # Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License. # you may not use this file except in compliance with the License.
# You may obtain a copy of the License at # You may obtain a copy of the License at
# http://www.apache.org/licenses/LICENSE-2.0 # http://www.apache.org/licenses/LICENSE-2.0
# #
# Unless required by applicable law or agreed to in writing, software # Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, # distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@ -12,7 +12,7 @@
# limitations under the License. # limitations under the License.
if { $::argc != 5 } { if { $::argc != 5 } {
puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n" puts "ERROR: Program \"$::argv0\" requires 5 arguments!\n"
puts "Usage: $::argv0 <xoname> <krnl_name> <vcs_file> <tool_dir> <build_dir>\n" puts "Usage: $::argv0 <xoname> <krnl_name> <vcs_file> <tool_dir> <build_dir>\n"
exit exit
} }

0
hw/syn/xilinx/scripts/kill_build.sh → hw/syn/xilinx/kill_build.sh
View file

0
hw/syn/xilinx/scripts/kill_hwserver.sh → hw/syn/xilinx/kill_hwserver.sh
View file

0
hw/syn/xilinx/scripts/kill_sim.sh → hw/syn/xilinx/kill_sim.sh
View file

39
hw/syn/xilinx/scripts/package_kernel.tcl → hw/syn/xilinx/package_kernel.tcl
View file

@ -71,65 +71,60 @@ set_property -verbose -name "top" -value ${krnl_name} -objects $obj
if { $chipscope == 1 } { if { $chipscope == 1 } {
# hw debugging # hw debugging
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_afu create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_afu
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
CONFIG.C_EN_STRG_QUAL {1} \ CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_DATA_DEPTH {4096} \ CONFIG.C_DATA_DEPTH {8192} \
CONFIG.C_NUM_OF_PROBES {2} \ CONFIG.C_NUM_OF_PROBES {2} \
CONFIG.C_PROBE0_WIDTH {8} \ CONFIG.C_PROBE0_WIDTH {8} \
CONFIG.C_PROBE1_WIDTH {24} \ CONFIG.C_PROBE1_WIDTH {64} \
CONFIG.ALL_PROBE_SAME_MU {false} \
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
] [get_ips ila_afu] ] [get_ips ila_afu]
generate_target {instantiation_template} [get_files ila_afu.xci] generate_target {instantiation_template} [get_files ila_afu.xci]
set_property generate_synth_checkpoint false [get_files ila_afu.xci] set_property generate_synth_checkpoint false [get_files ila_afu.xci]
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_fetch create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_fetch
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
CONFIG.C_EN_STRG_QUAL {1} \ CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_DATA_DEPTH {4096} \ CONFIG.C_DATA_DEPTH {8192} \
CONFIG.C_NUM_OF_PROBES {3} \ CONFIG.C_NUM_OF_PROBES {3} \
CONFIG.C_PROBE0_WIDTH {128} \ CONFIG.C_PROBE0_WIDTH {128} \
CONFIG.C_PROBE1_WIDTH {128} \ CONFIG.C_PROBE1_WIDTH {128} \
CONFIG.C_PROBE2_WIDTH {128} \ CONFIG.C_PROBE2_WIDTH {128} \
CONFIG.ALL_PROBE_SAME_MU {false} \
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
] [get_ips ila_fetch] ] [get_ips ila_fetch]
generate_target {instantiation_template} [get_files ila_fetch.xci] generate_target {instantiation_template} [get_files ila_fetch.xci]
set_property generate_synth_checkpoint false [get_files ila_fetch.xci] set_property generate_synth_checkpoint false [get_files ila_fetch.xci]
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_issue create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_issue
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
CONFIG.C_EN_STRG_QUAL {1} \ CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_DATA_DEPTH {4096} \ CONFIG.C_DATA_DEPTH {8192} \
CONFIG.C_NUM_OF_PROBES {2} \ CONFIG.C_NUM_OF_PROBES {2} \
CONFIG.C_PROBE0_WIDTH {256} \ CONFIG.C_PROBE0_WIDTH {256} \
CONFIG.C_PROBE1_WIDTH {128} \ CONFIG.C_PROBE1_WIDTH {128} \
CONFIG.ALL_PROBE_SAME_MU {false} \
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
] [get_ips ila_issue] ] [get_ips ila_issue]
generate_target {instantiation_template} [get_files ila_issue.xci] generate_target {instantiation_template} [get_files ila_issue.xci]
set_property generate_synth_checkpoint false [get_files ila_issue.xci] set_property generate_synth_checkpoint false [get_files ila_issue.xci]
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_lsu create_ip -name ila -vendor xilinx.com -library ip -version 6.2 -module_name ila_lsu
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \ set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
CONFIG.C_EN_STRG_QUAL {1} \ CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_DATA_DEPTH {4096} \ CONFIG.C_DATA_DEPTH {8192} \
CONFIG.C_NUM_OF_PROBES {4} \ CONFIG.C_NUM_OF_PROBES {4} \
CONFIG.C_PROBE0_WIDTH {256} \ CONFIG.C_PROBE0_WIDTH {256} \
CONFIG.C_PROBE1_WIDTH {128} \ CONFIG.C_PROBE1_WIDTH {128} \
CONFIG.C_PROBE2_WIDTH {288} \ CONFIG.C_PROBE2_WIDTH {288} \
CONFIG.C_PROBE3_WIDTH {256} \ CONFIG.C_PROBE3_WIDTH {256} \
CONFIG.ALL_PROBE_SAME_MU {false} \
CONFIG.ALL_PROBE_SAME_MU_CNT {2} \
] [get_ips ila_lsu] ] [get_ips ila_lsu]
generate_target {instantiation_template} [get_files ila_lsu.xci] generate_target {instantiation_template} [get_files ila_lsu.xci]
set_property generate_synth_checkpoint false [get_files ila_lsu.xci] set_property generate_synth_checkpoint false [get_files ila_lsu.xci]
create_ip -name axis_ila -vendor xilinx.com -library ip -version 1.1 -module_name ila_msched
set_property -dict [list CONFIG.C_ADV_TRIGGER {true} \
CONFIG.C_EN_STRG_QUAL {1} \
CONFIG.C_DATA_DEPTH {4096} \
CONFIG.C_NUM_OF_PROBES {4} \
CONFIG.C_PROBE0_WIDTH {128} \
CONFIG.C_PROBE1_WIDTH {128} \
CONFIG.C_PROBE2_WIDTH {128} \
CONFIG.C_PROBE3_WIDTH {128} \
] [get_ips ila_msched]
generate_target {instantiation_template} [get_files ila_msched.xci]
set_property generate_synth_checkpoint false [get_files ila_msched.xci]
} }
update_compile_order -fileset sources_1 update_compile_order -fileset sources_1

22
hw/syn/xilinx/sandbox/Makefile
View file

@ -19,16 +19,16 @@ KERNEL ?= fibonacci
NCPUS := $(shell lscpu | grep "^Core(s) per socket:" | awk '{print $$4}') NCPUS := $(shell lscpu | grep "^Core(s) per socket:" | awk '{print $$4}')
JOBS ?= $(shell echo $$(( $(NCPUS) > $(MAX_JOBS) ? $(MAX_JOBS) : $(NCPUS) ))) JOBS ?= $(shell echo $$(( $(NCPUS) > $(MAX_JOBS) ? $(MAX_JOBS) : $(NCPUS) )))
COE_FILE := $(shell realpath kernel.bin.coe)
ESCAPED_COE_FILE := $(shell echo "$(COE_FILE)" | sed -e 's/[\/&]/\\&/g')
# include paths # include paths
FPU_INCLUDE = -I$(RTL_DIR)/fpu FPU_INCLUDE = -I$(RTL_DIR)/fpu
ifneq (,$(findstring FPU_FPNEW,$(CONFIGS))) ifneq (,$(findstring FPU_FPNEW,$(CONFIGS)))
FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/include -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/src -J$(THIRD_PARTY_DIR)/cvfpu/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/cvfpu/src FPU_INCLUDE += -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/include -J$(THIRD_PARTY_DIR)/cvfpu/src/common_cells/src -J$(THIRD_PARTY_DIR)/cvfpu/src/fpu_div_sqrt_mvp/hdl -J$(THIRD_PARTY_DIR)/cvfpu/src
endif endif
TEX_INCLUDE = -I$(RTL_DIR)/tex
RASTER_INCLUDE = -I$(RTL_DIR)/raster
OM_INCLUDE = -I$(RTL_DIR)/om
RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR)/core -I$(RTL_DIR)/mem -I$(RTL_DIR)/cache
RTL_INCLUDE += $(FPU_INCLUDE) RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(OM_INCLUDE)
RTL_INCLUDE += -I$(SRC_DIR) RTL_INCLUDE += -I$(SRC_DIR)
# compilation flags # compilation flags
@ -43,9 +43,6 @@ CFLAGS += -DSTACK_BASE_ADDR=32\'hFF000
all: build all: build
project2.tcl: project.tcl
@sed -e "s/@COE_FILE@/$(ESCAPED_COE_FILE)/g" $< > $@
$(KERNEL).bin: $(KERNEL).bin:
$(MAKE) -C $(ROOT_DIR)/kernel clean $(MAKE) -C $(ROOT_DIR)/kernel clean
STACK_BASE_ADDR=0xFF000 $(MAKE) -C $(ROOT_DIR)/kernel STACK_BASE_ADDR=0xFF000 $(MAKE) -C $(ROOT_DIR)/kernel
@ -61,13 +58,14 @@ project_1/sources.txt:
mkdir -p project_1 mkdir -p project_1
$(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -P -Cproject_1/src -Oproject_1/sources.txt $(SCRIPT_DIR)/gen_sources.sh $(CFLAGS) -P -Cproject_1/src -Oproject_1/sources.txt
build: project_1/project_1.xpr build: done.dcp
project_1/project_1.xpr: project_1/sources.txt kernel.bin.coe project2.tcl done.dcp: project_1/sources.txt kernel.bin.coe project.tcl
MAX_JOBS=$(JOBS) $(VIVADO) -mode batch -source project2.tcl -tclargs $(DEVICE) project_1/sources.txt $(SCRIPT_DIR) MAX_JOBS=$(JOBS) $(VIVADO) -mode batch -source project.tcl -tclargs $(DEVICE) project_1/sources.txt $(SCRIPT_DIR)
echo done > done.dcp
run: project_1/project_1.xpr run: project_1/project_1.xpr
$(VIVADO) project_1/project_1.xpr & $(VIVADO) project_1/project_1.xpr &
clean: clean:
rm -rf project_1 project2.tcl $(KERNEL).bin kernel.bin.coe rm -rf project_1 project1.tcl $(KERNEL).bin kernel.bin.coe
rm -rf .Xil *.log *.jou rm -rf .Xil *.log *.jou *.dcp *.rpt

721
hw/syn/xilinx/sandbox/project.tcl.in
View file

@ -11,9 +11,6 @@
# See the License for the specific language governing permissions and # See the License for the specific language governing permissions and
# limitations under the License. # limitations under the License.
# Start time
set start_time [clock seconds]
if { $::argc != 3 } { if { $::argc != 3 } {
puts "ERROR: Program \"$::argv0\" requires 3 arguments!\n" puts "ERROR: Program \"$::argv0\" requires 3 arguments!\n"
puts "Usage: $::argv0 <device_part> <vcs_file> <tool_dir>\n" puts "Usage: $::argv0 <device_part> <vcs_file> <tool_dir>\n"
@ -24,7 +21,7 @@ set device_part [lindex $::argv 0]
set vcs_file [lindex $::argv 1] set vcs_file [lindex $::argv 1]
set tool_dir [lindex $::argv 2] set tool_dir [lindex $::argv 2]
uuts "Using device_part=$device_part" puts "Using device_part=$device_part"
puts "Using vcs_file=$vcs_file" puts "Using vcs_file=$vcs_file"
puts "Using tool_dir=$tool_dir" puts "Using tool_dir=$tool_dir"
@ -37,398 +34,436 @@ if {[info exists ::env(MAX_JOBS)]} {
set num_jobs 0 set num_jobs 0
} }
set origin_dir [file normalize "."] proc run_setup {} {
global device_part vcs_file tool_dir
# Use origin directory path location variable, if specified in the tcl shell # Set the project name
if { [info exists ::origin_dir_loc] } { set project_name "project_1"
set origin_dir $::origin_dir_loc
}
# Set the project name # Use project name variable, if specified in the tcl shell
set project_name "project_1" if { [info exists ::user_project_name] } {
set project_name $::user_project_name
}
# Use project name variable, if specified in the tcl shell source "${tool_dir}/parse_vcs_list.tcl"
if { [info exists ::user_project_name] } { set vlist [parse_vcs_list "${vcs_file}"]
set project_name $::user_project_name
}
source "${tool_dir}/parse_vcs_list.tcl" set vsources_list [lindex $vlist 0]
set vlist [parse_vcs_list "${vcs_file}"] set vincludes_list [lindex $vlist 1]
set vdefines_list [lindex $vlist 2]
set vsources_list [lindex $vlist 0] #puts ${vsources_list}
set vincludes_list [lindex $vlist 1] #puts ${vincludes_list}
set vdefines_list [lindex $vlist 2] #puts ${vdefines_list}
#puts ${vsources_list} # Create project
#puts ${vincludes_list} create_project $project_name $project_name -force -part $device_part
#puts ${vdefines_list}
# Create project # Set the directory path for the new project
create_project $project_name $project_name -force -part $device_part set proj_dir [get_property directory [current_project]]
# Set the directory path for the new project # Create 'sources_1' fileset (if not found)
set proj_dir [get_property directory [current_project]] if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
# Create 'sources_1' fileset (if not found) # add source files
if {[string equal [get_filesets -quiet sources_1] ""]} { set obj [get_filesets sources_1]
create_fileset -srcset sources_1 add_files -norecurse -verbose -fileset $obj ${vsources_list}
}
# add source files # process defines
set obj [get_filesets sources_1] set obj [get_filesets sources_1]
add_files -norecurse -verbose -fileset $obj ${vsources_list} foreach def $vdefines_list {
set_property -name "verilog_define" -value $def -objects $obj
}
# process defines # Set 'sources_1' fileset properties
set obj [get_filesets sources_1] set obj [get_filesets sources_1]
foreach def $vdefines_list { set_property -name "name" -value "sources_1" -objects $obj
set_property -name "verilog_define" -value $def -objects $obj set_property -name "top" -value "design_1_wrapper" -objects $obj
}
# Set 'sources_1' fileset properties # Create 'constrs_1' fileset (if not found)
set obj [get_filesets sources_1] if {[string equal [get_filesets -quiet constrs_1] ""]} {
set_property -name "name" -value "sources_1" -objects $obj create_fileset -constrset constrs_1
set_property -name "top" -value "design_1_wrapper" -objects $obj }
# Create 'constrs_1' fileset (if not found) # Set 'constrs_1' fileset object
if {[string equal [get_filesets -quiet constrs_1] ""]} { set obj [get_filesets constrs_1]
create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object # Empty (no sources present)
set obj [get_filesets constrs_1]
# Empty (no sources present) # Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
set_property -name "constrs_type" -value "XDC" -objects $obj
set_property -name "name" -value "constrs_1" -objects $obj
set_property -name "target_constrs_file" -value "" -objects $obj
# Set 'constrs_1' fileset properties # Create 'sim_1' fileset (if not found)
set obj [get_filesets constrs_1] if {[string equal [get_filesets -quiet sim_1] ""]} {
set_property -name "constrs_type" -value "XDC" -objects $obj create_fileset -simset sim_1
set_property -name "name" -value "constrs_1" -objects $obj }
set_property -name "target_constrs_file" -value "" -objects $obj
# Create 'sim_1' fileset (if not found) set testbench_file ""
if {[string equal [get_filesets -quiet sim_1] ""]} { foreach file ${vsources_list} {
create_fileset -simset sim_1 if {[string match "*testbench.v" $file]} {
} set testbench_file [file normalize $file]
break
}
}
# Set 'sim_1' fileset object # Set 'sim_1' fileset object
set obj [get_filesets sim_1] set obj [get_filesets sim_1]
# Import local files from the original project # Import local files from the original project
set files [list \ set files [list $testbench_file]
[file normalize "testbench.v" ]\ set imported_files [import_files -fileset sim_1 $files]
]
set imported_files [import_files -fileset sim_1 $files]
# Set 'sim_1' fileset file properties for remote files # Set 'sim_1' fileset file properties for remote files
# None # None
# Set 'sim_1' fileset file properties for local files # Set 'sim_1' fileset file properties for local files
set file "testbench.v" set file "testbench.v"
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]] set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property -name "file_type" -value "Verilog" -objects $file_obj set_property -name "file_type" -value "Verilog" -objects $file_obj
set_property -name "is_enabled" -value "1" -objects $file_obj set_property -name "is_enabled" -value "1" -objects $file_obj
set_property -name "is_global_include" -value "0" -objects $file_obj set_property -name "is_global_include" -value "0" -objects $file_obj
set_property -name "library" -value "xil_defaultlib" -objects $file_obj set_property -name "library" -value "xil_defaultlib" -objects $file_obj
set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
set_property -name "used_in_implementation" -value "1" -objects $file_obj set_property -name "used_in_implementation" -value "1" -objects $file_obj
set_property -name "used_in_simulation" -value "1" -objects $file_obj set_property -name "used_in_simulation" -value "1" -objects $file_obj
set_property -name "used_in_synthesis" -value "1" -objects $file_obj set_property -name "used_in_synthesis" -value "1" -objects $file_obj
# Set 'sim_1' fileset properties # Set 'sim_1' fileset properties
set obj [get_filesets sim_1] set obj [get_filesets sim_1]
set_property -name "32bit" -value "0" -objects $obj set_property -name "32bit" -value "0" -objects $obj
set_property -name "force_compile_glbl" -value "0" -objects $obj set_property -name "force_compile_glbl" -value "0" -objects $obj
set_property -name "generate_scripts_only" -value "0" -objects $obj set_property -name "generate_scripts_only" -value "0" -objects $obj
set_property -name "generic" -value "" -objects $obj set_property -name "generic" -value "" -objects $obj
set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
set_property -name "include_dirs" -value "" -objects $obj set_property -name "include_dirs" -value "" -objects $obj
set_property -name "incremental" -value "1" -objects $obj set_property -name "incremental" -value "1" -objects $obj
set_property -name "name" -value "sim_1" -objects $obj set_property -name "name" -value "sim_1" -objects $obj
set_property -name "source_set" -value "sources_1" -objects $obj set_property -name "source_set" -value "sources_1" -objects $obj
set_property -name "systemc_include_dirs" -value "" -objects $obj set_property -name "systemc_include_dirs" -value "" -objects $obj
set_property -name "top" -value "testbench" -objects $obj set_property -name "top" -value "testbench" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
set_property -name "verilog_define" -value "" -objects $obj set_property -name "verilog_define" -value "" -objects $obj
set_property -name "verilog_uppercase" -value "0" -objects $obj set_property -name "verilog_uppercase" -value "0" -objects $obj
# Set 'utils_1' fileset object # Set 'utils_1' fileset object
set obj [get_filesets utils_1] set obj [get_filesets utils_1]
# Empty (no sources present) # Empty (no sources present)
# Set 'utils_1' fileset properties # Set 'utils_1' fileset properties
set obj [get_filesets utils_1] set obj [get_filesets utils_1]
set_property -name "name" -value "utils_1" -objects $obj set_property -name "name" -value "utils_1" -objects $obj
# Proc to create BD design_1 # Proc to create BD design_1
proc cr_bd_design_1 { parentCell } { proc cr_bd_design_1 { parentCell } {
# The design that will be created by this Tcl proc contains the following # The design that will be created by this Tcl proc contains the following
# module references: # module references:
# Vortex_top # Vortex_top
# CHANGE DESIGN NAME HERE # CHANGE DESIGN NAME HERE
set design_name design_1 set design_name design_1
common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..." common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name create_bd_design $design_name
set bCheckIPsPassed 1 set bCheckIPsPassed 1
################################################################## ##################################################################
# CHECK IPs # CHECK IPs
################################################################## ##################################################################
set bCheckIPs 1 set bCheckIPs 1
if { $bCheckIPs == 1 } { if { $bCheckIPs == 1 } {
set list_check_ips "\ set list_check_ips "\
xilinx.com:ip:axi_bram_ctrl:4.1\ xilinx.com:ip:axi_bram_ctrl:4.1\
xilinx.com:ip:blk_mem_gen:8.4\ xilinx.com:ip:blk_mem_gen:8.4\
" "
set list_ips_missing "" set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips { foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv] set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } { if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv lappend list_ips_missing $ip_vlnv
} }
} }
if { $list_ips_missing ne "" } { if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0 set bCheckIPsPassed 0
} }
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
Vortex_top\
"
set list_mods_missing ""
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
} }
################################################################## if { $bCheckIPsPassed != 1 } {
# CHECK Modules common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
################################################################## return 3
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
Vortex_top\
"
set list_mods_missing ""
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
variable script_folder
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
# Create ports
set clk_100MHz [ create_bd_port -dir I -type clk -freq_hz 100000000 clk_100MHz ]
set resetn [ create_bd_port -dir I -type rst resetn ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_LOW} \
] $resetn
set vx_busy [ create_bd_port -dir O vx_busy ]
set vx_reset [ create_bd_port -dir I -type rst vx_reset ]
set_property -dict [ list \
CONFIG.POLARITY {ACTIVE_HIGH} \
] $vx_reset
set dcr_wr_valid [ create_bd_port -dir I dcr_wr_valid ]
set dcr_wr_addr [ create_bd_port -dir I -from 11 -to 0 dcr_wr_addr ]
set dcr_wr_data [ create_bd_port -dir I -from 31 -to 0 dcr_wr_data ]
# Create instance: Vortex_top_0, and set properties
set block_name Vortex_top
set block_cell_name Vortex_top_0
if { [catch {set Vortex_top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $Vortex_top_0 eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} }
# Create instance: axi_bram_ctrl_0, and set properties variable script_folder
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ECC_TYPE {0} \
] $axi_bram_ctrl_0
# Create instance: axi_bram_ctrl_0_bram, and set properties if { $parentCell eq "" } {
set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ] set parentCell [get_bd_cells /]
}
set_property -dict [ list \ # Get object for parentCell
CONFIG.Assume_Synchronous_Clk {true} \ set parentObj [get_bd_cells $parentCell]
CONFIG.Byte_Size {8} \ if { $parentObj == "" } {
CONFIG.Load_Init_File {true} \ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
CONFIG.Coe_File {@COE_FILE@} \ return
CONFIG.EN_SAFETY_CKT {true} \ }
CONFIG.Enable_32bit_Address {true} \
CONFIG.Fill_Remaining_Memory_Locations {false} \
CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
CONFIG.Operating_Mode_A {NO_CHANGE} \
CONFIG.Operating_Mode_B {READ_FIRST} \
CONFIG.Port_B_Write_Rate {0} \
CONFIG.Read_Width_A {512} \
CONFIG.Read_Width_B {512} \
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
CONFIG.Remaining_Memory_Locations {0} \
CONFIG.Use_Byte_Write_Enable {true} \
CONFIG.Use_RSTA_Pin {false} \
CONFIG.Use_RSTB_Pin {true} \
CONFIG.Write_Width_A {512} \
CONFIG.Write_Depth_A {16384} \
CONFIG.use_bram_block {Stand_Alone} \
] $axi_bram_ctrl_0_bram
# Create interface connections # Make sure parentObj is hier blk
connect_bd_intf_net -intf_net Vortex_top_0_m_axi_mem [get_bd_intf_pins Vortex_top_0/m_axi_mem] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI] set parentType [get_property TYPE $parentObj]
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA] if { $parentType ne "hier" } {
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTB] catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Create port connections # Save current instance; Restore later
connect_bd_net -net Vortex_top_0_busy [get_bd_ports vx_busy] [get_bd_pins Vortex_top_0/busy] set oldCurInst [current_bd_instance .]
connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins Vortex_top_0/clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk]
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn]
connect_bd_net -net vx_reset_1 [get_bd_ports vx_reset] [get_bd_pins Vortex_top_0/reset]
connect_bd_net -net dcr_wr_valid_1 [get_bd_ports dcr_wr_valid] [get_bd_pins Vortex_top_0/dcr_wr_valid]
connect_bd_net -net dcr_wr_addr_1 [get_bd_ports dcr_wr_addr] [get_bd_pins Vortex_top_0/dcr_wr_addr]
connect_bd_net -net dcr_wr_data_1 [get_bd_ports dcr_wr_data] [get_bd_pins Vortex_top_0/dcr_wr_data]
# Create address segments # Set parent object as current
assign_bd_address -offset 0x00000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces Vortex_top_0/m_axi_mem] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force current_bd_instance $parentObj
# Perform GUI Layout
regenerate_bd_layout -layout_string { # Create interface ports
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0", # Create ports
"Default View_TopLeft":"-195,-165", set clk_100MHz [ create_bd_port -dir I -type clk -freq_hz 100000000 clk_100MHz ]
"ExpandedHierarchyInLayout":"", set resetn [ create_bd_port -dir I -type rst resetn ]
"guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS set_property -dict [ list \
# -string -flagsOSRD CONFIG.POLARITY {ACTIVE_LOW} \
preplace port clk_100MHz -pg 1 -lvl 0 -x 0 -y 40 -defaultsOSRD ] $resetn
preplace port resetn -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD set vx_busy [ create_bd_port -dir O vx_busy ]
preplace port vx_busy -pg 1 -lvl 4 -x 950 -y 220 -defaultsOSRD set vx_reset [ create_bd_port -dir I -type rst vx_reset ]
preplace port vx_reset -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD set_property -dict [ list \
preplace port dcr_wr_valid -pg 1 -lvl 0 -x 0 -y 130 -defaultsOSRD CONFIG.POLARITY {ACTIVE_HIGH} \
preplace portBus dcr_wr_addr -pg 1 -lvl 0 -x 0 -y 150 -defaultsOSRD ] $vx_reset
preplace portBus dcr_wr_data -pg 1 -lvl 0 -x 0 -y 170 -defaultsOSRD
preplace inst Vortex_top_0 -pg 1 -lvl 1 -x 190 -y 130 -defaultsOSRD set dcr_wr_valid [ create_bd_port -dir I dcr_wr_valid ]
preplace inst axi_bram_ctrl_0 -pg 1 -lvl 2 -x 520 -y 140 -defaultsOSRD set dcr_wr_addr [ create_bd_port -dir I -from 11 -to 0 dcr_wr_addr ]
preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 3 -x 800 -y 140 -defaultsOSRD set dcr_wr_data [ create_bd_port -dir I -from 31 -to 0 dcr_wr_data ]
preplace netloc Vortex_top_0_busy 1 1 3 360J 220 NJ 220 NJ
preplace netloc clk_wiz_clk_out1 1 0 2 20 30 370 # Create instance: Vortex_top_0, and set properties
preplace netloc resetn_1 1 0 2 NJ 20 380J set block_name Vortex_top
preplace netloc vx_reset_1 1 0 1 NJ 110 set block_cell_name Vortex_top_0
preplace netloc dcr_wr_valid_1 1 0 1 NJ 130 if { [catch {set Vortex_top_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
preplace netloc dcr_wr_addr_1 1 0 1 NJ 150 catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
preplace netloc dcr_wr_data_1 1 0 1 NJ 170 return 1
preplace netloc axi_bram_ctrl_0_BRAM_PORTB 1 2 1 N 150 } elseif { $Vortex_top_0 eq "" } {
preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 2 1 N 130 catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
preplace netloc Vortex_top_0_m_axi_mem 1 1 1 N 120 return 1
levelinfo -pg 1 0 190 520 800 950 }
pagesize -pg 1 -db -bbox -sgen -180 0 1060 240
" # Create instance: axi_bram_ctrl_0, and set properties
set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
set_property -dict [ list \
CONFIG.DATA_WIDTH {512} \
CONFIG.ECC_TYPE {0} \
] $axi_bram_ctrl_0
# Create instance: axi_bram_ctrl_0_bram, and set properties
set axi_bram_ctrl_0_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 axi_bram_ctrl_0_bram ]
set_property -dict [ list \
CONFIG.Assume_Synchronous_Clk {true} \
CONFIG.Byte_Size {8} \
CONFIG.Load_Init_File {true} \
CONFIG.Coe_File {@CURRENTDIR@/hw/syn/xilinx/sandbox/kernel.bin.coe} \
CONFIG.EN_SAFETY_CKT {true} \
CONFIG.Enable_32bit_Address {true} \
CONFIG.Fill_Remaining_Memory_Locations {false} \
CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
CONFIG.Operating_Mode_A {NO_CHANGE} \
CONFIG.Operating_Mode_B {READ_FIRST} \
CONFIG.Port_B_Write_Rate {0} \
CONFIG.Read_Width_A {512} \
CONFIG.Read_Width_B {512} \
CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
CONFIG.Register_PortB_Output_of_Memory_Primitives {false} \
CONFIG.Remaining_Memory_Locations {0} \
CONFIG.Use_Byte_Write_Enable {true} \
CONFIG.Use_RSTA_Pin {false} \
CONFIG.Use_RSTB_Pin {true} \
CONFIG.Write_Width_A {512} \
CONFIG.Write_Depth_A {16384} \
CONFIG.use_bram_block {Stand_Alone} \
] $axi_bram_ctrl_0_bram
# Create interface connections
connect_bd_intf_net -intf_net Vortex_top_0_m_axi_mem [get_bd_intf_pins Vortex_top_0/m_axi_mem] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTA]
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_0_bram/BRAM_PORTB]
# Create port connections
connect_bd_net -net Vortex_top_0_busy [get_bd_ports vx_busy] [get_bd_pins Vortex_top_0/busy]
connect_bd_net -net clk_wiz_clk_out1 [get_bd_ports clk_100MHz] [get_bd_pins Vortex_top_0/clk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk]
connect_bd_net -net resetn_1 [get_bd_ports resetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn]
connect_bd_net -net vx_reset_1 [get_bd_ports vx_reset] [get_bd_pins Vortex_top_0/reset]
connect_bd_net -net dcr_wr_valid_1 [get_bd_ports dcr_wr_valid] [get_bd_pins Vortex_top_0/dcr_wr_valid]
connect_bd_net -net dcr_wr_addr_1 [get_bd_ports dcr_wr_addr] [get_bd_pins Vortex_top_0/dcr_wr_addr]
connect_bd_net -net dcr_wr_data_1 [get_bd_ports dcr_wr_data] [get_bd_pins Vortex_top_0/dcr_wr_data]
# Create address segments
assign_bd_address -offset 0x00000000 -range 0x00100000 -target_address_space [get_bd_addr_spaces Vortex_top_0/m_axi_mem] [get_bd_addr_segs axi_bram_ctrl_0/S_AXI/Mem0] -force
# Perform GUI Layout
regenerate_bd_layout -layout_string {
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"1.0",
"Default View_TopLeft":"-195,-165",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
# -string -flagsOSRD
preplace port clk_100MHz -pg 1 -lvl 0 -x 0 -y 40 -defaultsOSRD
preplace port resetn -pg 1 -lvl 0 -x 0 -y 20 -defaultsOSRD
preplace port vx_busy -pg 1 -lvl 4 -x 950 -y 220 -defaultsOSRD
preplace port vx_reset -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD
preplace port dcr_wr_valid -pg 1 -lvl 0 -x 0 -y 130 -defaultsOSRD
preplace portBus dcr_wr_addr -pg 1 -lvl 0 -x 0 -y 150 -defaultsOSRD
preplace portBus dcr_wr_data -pg 1 -lvl 0 -x 0 -y 170 -defaultsOSRD
preplace inst Vortex_top_0 -pg 1 -lvl 1 -x 190 -y 130 -defaultsOSRD
preplace inst axi_bram_ctrl_0 -pg 1 -lvl 2 -x 520 -y 140 -defaultsOSRD
preplace inst axi_bram_ctrl_0_bram -pg 1 -lvl 3 -x 800 -y 140 -defaultsOSRD
preplace netloc Vortex_top_0_busy 1 1 3 360J 220 NJ 220 NJ
preplace netloc clk_wiz_clk_out1 1 0 2 20 30 370
preplace netloc resetn_1 1 0 2 NJ 20 380J
preplace netloc vx_reset_1 1 0 1 NJ 110
preplace netloc dcr_wr_valid_1 1 0 1 NJ 130
preplace netloc dcr_wr_addr_1 1 0 1 NJ 150
preplace netloc dcr_wr_data_1 1 0 1 NJ 170
preplace netloc axi_bram_ctrl_0_BRAM_PORTB 1 2 1 N 150
preplace netloc axi_bram_ctrl_0_BRAM_PORTA 1 2 1 N 130
preplace netloc Vortex_top_0_m_axi_mem 1 1 1 N 120
levelinfo -pg 1 0 190 520 800 950
pagesize -pg 1 -db -bbox -sgen -180 0 1060 240
"
}
# Restore current instance
current_bd_instance $oldCurInst
validate_bd_design
save_bd_design
close_bd_design $design_name
}
# End of cr_bd_design_1()
cr_bd_design_1 ""
set_property EXCLUDE_DEBUG_LOGIC "0" [get_files design_1.bd ]
set_property GENERATE_SYNTH_CHECKPOINT "1" [get_files design_1.bd ]
set_property IS_ENABLED "1" [get_files design_1.bd ]
set_property IS_GLOBAL_INCLUDE "0" [get_files design_1.bd ]
#set_property IS_LOCKED "0" [get_files design_1.bd ]
set_property LIBRARY "xil_defaultlib" [get_files design_1.bd ]
set_property PATH_MODE "RelativeFirst" [get_files design_1.bd ]
set_property PFM_NAME "" [get_files design_1.bd ]
set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
set_property USED_IN "synthesis implementation simulation" [get_files design_1.bd ]
set_property USED_IN_IMPLEMENTATION "1" [get_files design_1.bd ]
set_property USED_IN_SIMULATION "1" [get_files design_1.bd ]
set_property USED_IN_SYNTHESIS "1" [get_files design_1.bd ]
# Call make_wrapper to create wrapper files
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top]
add_files -norecurse -fileset sources_1 $wrapper_path
update_compile_order -fileset sources_1
} }
# Restore current instance proc run_synthesis {} {
current_bd_instance $oldCurInst global num_jobs
# Synthesis
if {$num_jobs != 0} {
launch_runs synth_1 -jobs $num_jobs
} else {
launch_runs synth_1
}
wait_on_run synth_1
open_run synth_1
report_utilization -file utilization.rpt -hierarchical -hierarchical_percentages
validate_bd_design write_checkpoint -force post_synth.dcp
save_bd_design
close_bd_design $design_name
} }
# End of cr_bd_design_1()
cr_bd_design_1 ""
set_property EXCLUDE_DEBUG_LOGIC "0" [get_files design_1.bd ]
set_property GENERATE_SYNTH_CHECKPOINT "1" [get_files design_1.bd ]
set_property IS_ENABLED "1" [get_files design_1.bd ]
set_property IS_GLOBAL_INCLUDE "0" [get_files design_1.bd ]
#set_property IS_LOCKED "0" [get_files design_1.bd ]
set_property LIBRARY "xil_defaultlib" [get_files design_1.bd ]
set_property PATH_MODE "RelativeFirst" [get_files design_1.bd ]
set_property PFM_NAME "" [get_files design_1.bd ]
set_property REGISTERED_WITH_MANAGER "1" [get_files design_1.bd ]
set_property SYNTH_CHECKPOINT_MODE "Hierarchical" [get_files design_1.bd ]
set_property USED_IN "synthesis implementation simulation" [get_files design_1.bd ]
set_property USED_IN_IMPLEMENTATION "1" [get_files design_1.bd ]
set_property USED_IN_SIMULATION "1" [get_files design_1.bd ]
set_property USED_IN_SYNTHESIS "1" [get_files design_1.bd ]
# Call make_wrapper to create wrapper files proc run_implementation {} {
set wrapper_path [make_wrapper -fileset sources_1 -files [ get_files -norecurse design_1.bd] -top] global tool_dir num_jobs
add_files -norecurse -fileset sources_1 $wrapper_path source "${tool_dir}/ila_insert.tcl"
insert_ila 8192
update_compile_order -fileset sources_1 # Implementation
if {$num_jobs != 0} {
launch_runs impl_1 -jobs $num_jobs
} else {
launch_runs impl_1
}
wait_on_run impl_1
open_run impl_1
report_place_status -file place.rpt
report_route_status -file route.rpt
write_checkpoint -force post_impl.dcp
}
# Synthesis proc run_report {} {
if {$num_jobs != 0} { # Generate reports
launch_runs synth_1 -jobs $num_jobs report_timing_summary -file timing.rpt
report_power -file power.rpt
report_drc -file drc.rpt
}
###############################################################################
# Start time
set start_time [clock seconds]
# Check if the post-implementation checkpoint exists
if { [file exists post_impl.dcp] } {
puts "Resuming from post-implementation checkpoint: post_impl.dcp"
open_checkpoint post_impl.dcp
run_report
} elseif { [file exists post_synth.dcp] } {
puts "Resuming from post-synthesis checkpoint: post_synth.dcp"
open_checkpoint post_synth.dcp
run_implementation
run_report
} else { } else {
launch_runs synth_1 # execute full pipeline
run_setup
run_synthesis
run_implementation
run_report
} }
wait_on_run synth_1
open_run synth_1
write_checkpoint -force post_synth.dcp
report_utilization -file utilization.rpt -hierarchical -hierarchical_percentages
# Implementation
if {$num_jobs != 0} {
launch_runs impl_1 -jobs $num_jobs
} else {
launch_runs impl_1
}
wait_on_run impl_1
open_run impl_1
write_checkpoint -force post_impl.dcp
# Generate reports
report_place_status -file place.rpt
report_route_status -file route.rpt
report_timing_summary -file timing.rpt
report_power -file power.rpt
report_drc -file drc.rpt
# End time and calculation # End time and calculation
set elapsed_time [expr {[clock seconds] - $start_time}] set elapsed_time [expr {[clock seconds] - $start_time}]

5
hw/syn/xilinx/xrt/Makefile
View file

@ -122,7 +122,8 @@ ifdef DEBUG
VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all VPP_FLAGS += --vivado.prop fileset.sim_1.xsim.elaborate.debug_level=all
CFLAGS += -DDEBUG_LEVEL=$(DEBUG) $(DBG_TRACE_FLAGS) CFLAGS += -DDEBUG_LEVEL=$(DEBUG) $(DBG_TRACE_FLAGS)
else else
CFLAGS += -DNDEBUG VPP_FLAGS += --debug.chipscope vortex_afu_1
CFLAGS += -DNDEBUG -DCHIPSCOPE $(DBG_SCOPE_FLAGS)
endif endif
else else
VPP_FLAGS += --optimize 3 VPP_FLAGS += --optimize 3
@ -167,7 +168,7 @@ $(BUILD_DIR)/scope.json: $(BUILD_DIR)/vortex.xml
gen-xo: $(XO_CONTAINER) gen-xo: $(XO_CONTAINER)
$(XO_CONTAINER): $(BUILD_DIR)/sources.txt $(XO_CONTAINER): $(BUILD_DIR)/sources.txt
mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source $(SRC_DIR)/../scripts/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR) mkdir -p $(BUILD_DIR); cd $(BUILD_DIR); $(VIVADO) -mode batch -source $(SRC_DIR)/gen_xo.tcl -tclargs ../$(XO_CONTAINER) vortex_afu sources.txt $(SCRIPT_DIR) ../$(BUILD_DIR)
gen-bin: $(XCLBIN_CONTAINER) gen-bin: $(XCLBIN_CONTAINER)
$(XCLBIN_CONTAINER): $(XO_CONTAINER) $(SCOPE_JSON) $(XCLBIN_CONTAINER): $(XO_CONTAINER) $(SCOPE_JSON)

1
sim/simx/cache_sim.cpp
View file

@ -514,6 +514,7 @@ public:
bank_req.type = bank_req_t::Core; bank_req.type = bank_req_t::Core;
bank_req.write = core_req.write; bank_req.write = core_req.write;
pipeline_req = bank_req; pipeline_req = bank_req;
DT(3, simobject_->name() << " core-req: " << core_req);
} }
if (core_req.write) if (core_req.write)