mirror of
https://github.com/vortexgpgpu/vortex.git
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Removed unnessary Verilog files, linked memory tech files, having problem with memory instatiation
This commit is contained in:
Lingjun Zhu
parent
557c987bb0
commit
50d567d70c
58 changed files with 18147 additions and 21848 deletions
1
models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.cr.mti
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1
models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.cr.mti
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2167
models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.mpf
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2167
models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf_tb.mpf
Normal file
File diff suppressed because it is too large
Load diff
249
models/memory/cln28hpc/rf2_32x128_wm1/vsim/transcript
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249
models/memory/cln28hpc/rf2_32x128_wm1/vsim/transcript
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# // ModelSim SE-64 10.6a Mar 16 2017Linux 3.10.0-1062.1.2.el7.x86_64
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# //
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# // Copyright 1991-2017 Mentor Graphics Corporation
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# // All Rights Reserved.
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# //
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# // ModelSim SE-64 and its associated documentation contain trade
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# // secrets and commercial or financial information that are the property of
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# // Mentor Graphics Corporation and are privileged, confidential,
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# // and exempt from disclosure under the Freedom of Information Act,
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# // 5 U.S.C. Section 552. Furthermore, this information
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# // is prohibited from disclosure under the Trade Secrets Act,
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# // 18 U.S.C. Section 1905.
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# //
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# Loading project rf_tb
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# Compile of rf2_32x128_wm1_tb.v was successful.
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vsim work.rf2_32x128_wm1_tb
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# vsim work.rf2_32x128_wm1_tb
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# Start time: 19:36:40 on Oct 19,2019
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# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
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# Loading work.rf2_32x128_wm1_tb(fast)
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# Loading work.rf2_32x128_wm1(fast)
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add wave -position insertpoint \
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sim:/rf2_32x128_wm1_tb/out_a_reg_data \
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sim:/rf2_32x128_wm1_tb/clk \
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sim:/rf2_32x128_wm1_tb/rs1 \
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sim:/rf2_32x128_wm1_tb/write_bit_mask \
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sim:/rf2_32x128_wm1_tb/rd \
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sim:/rf2_32x128_wm1_tb/write_data \
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sim:/rf2_32x128_wm1_tb/cena \
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sim:/rf2_32x128_wm1_tb/cenb
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run
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run
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14065): $hold( posedge CLKB &&& RET1Neq1aTENBeq1:105 ns, negedge CENB:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14290): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[31]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14291): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[30]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14292): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[29]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14293): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[28]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14294): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[27]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14295): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[26]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14296): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[25]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14297): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[24]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14298): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[23]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14299): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[22]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14300): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[21]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14301): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[20]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14302): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[19]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14303): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[18]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14304): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[17]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14305): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[16]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14306): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[15]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14307): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[14]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14308): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[13]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14309): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[12]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14310): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[11]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14311): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[10]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14312): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[9]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14313): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[8]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14314): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[7]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14315): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[6]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14316): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[5]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14317): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[4]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14318): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[3]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14319): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[2]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14320): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[1]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14321): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, negedge WENB[0]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14323): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0aCOLLDISNeq1:105 ns, posedge AB[3]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14325): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0aCOLLDISNeq1:105 ns, posedge AB[1]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14468): $hold( posedge CLKB &&& RET1Neq1aTENBeq1aopopDFTRAMBYPeq1aSEBeq0cpoopDFTRAMBYPeq0aCENBeq0aWENB1eq0cpcp:105 ns, posedge DB[1]:105 ns, 500 ps );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14064): $hold( posedge CLKB &&& RET1Neq1aTENBeq1:115 ns, posedge CENB:115 ns, 500 ps );
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# Time: 115 ns Iteration: 2 Instance: /rf2_32x128_wm1_tb/first_ram
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run
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14043): $hold( posedge CLKA &&& RET1Neq1aTENAeq1:215 ns, negedge CENA:215 ns, 500 ps );
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# Time: 215 ns Iteration: 3 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14045): $hold( posedge CLKA &&& RET1Neq1aTENAeq1aCENAeq0aCOLLDISNeq1:215 ns, posedge AA[3]:215 ns, 500 ps );
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# Time: 215 ns Iteration: 3 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14047): $hold( posedge CLKA &&& RET1Neq1aTENAeq1aCENAeq0aCOLLDISNeq1:215 ns, posedge AA[1]:215 ns, 500 ps );
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# Time: 215 ns Iteration: 3 Instance: /rf2_32x128_wm1_tb/first_ram
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# Causality operation skipped due to absence of debug database file
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quit -sim
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# End time: 19:44:22 on Oct 19,2019, Elapsed time: 0:07:42
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# Errors: 40, Warnings: 1
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# Compile of rf2_32x128_wm1_tb.v was successful.
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vsim work.rf2_32x128_wm1_tb
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# vsim work.rf2_32x128_wm1_tb
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# Start time: 19:44:30 on Oct 19,2019
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# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
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# Loading work.rf2_32x128_wm1_tb(fast)
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# Loading work.rf2_32x128_wm1(fast)
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add wave -position insertpoint \
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sim:/rf2_32x128_wm1_tb/out_a_reg_data \
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sim:/rf2_32x128_wm1_tb/clk \
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sim:/rf2_32x128_wm1_tb/rs1 \
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sim:/rf2_32x128_wm1_tb/write_bit_mask \
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sim:/rf2_32x128_wm1_tb/rd \
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sim:/rf2_32x128_wm1_tb/write_data \
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sim:/rf2_32x128_wm1_tb/cena \
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sim:/rf2_32x128_wm1_tb/cenb
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run
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run
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14065): $setup( negedge CENB:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1:105 ns, 1 ns );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
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# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14290): $setup( negedge WENB[31]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
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# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14291): $setup( negedge WENB[30]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14292): $setup( negedge WENB[29]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14293): $setup( negedge WENB[28]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14294): $setup( negedge WENB[27]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14295): $setup( negedge WENB[26]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14296): $setup( negedge WENB[25]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14297): $setup( negedge WENB[24]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14298): $setup( negedge WENB[23]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14299): $setup( negedge WENB[22]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14300): $setup( negedge WENB[21]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14301): $setup( negedge WENB[20]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14302): $setup( negedge WENB[19]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14303): $setup( negedge WENB[18]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14304): $setup( negedge WENB[17]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14305): $setup( negedge WENB[16]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14306): $setup( negedge WENB[15]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14307): $setup( negedge WENB[14]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14308): $setup( negedge WENB[13]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14309): $setup( negedge WENB[12]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14310): $setup( negedge WENB[11]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14311): $setup( negedge WENB[10]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14312): $setup( negedge WENB[9]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14313): $setup( negedge WENB[8]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14314): $setup( negedge WENB[7]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14315): $setup( negedge WENB[6]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14316): $setup( negedge WENB[5]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14317): $setup( negedge WENB[4]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14318): $setup( negedge WENB[3]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14319): $setup( negedge WENB[2]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14320): $setup( negedge WENB[1]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14321): $setup( negedge WENB[0]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14323): $setup( posedge AB[3]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0aCOLLDISNeq1:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14325): $setup( posedge AB[1]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aCENBeq0aCOLLDISNeq1:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14468): $setup( posedge DB[1]:104500 ps, posedge CLKB &&& RET1Neq1aTENBeq1aopopDFTRAMBYPeq1aSEBeq0cpoopDFTRAMBYPeq0aCENBeq0aWENB1eq0cpcp:105 ns, 1 ns );
|
||||
# Time: 105 ns Iteration: 5 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14064): $setup( posedge CENB:114500 ps, posedge CLKB &&& RET1Neq1aTENBeq1:115 ns, 1 ns );
|
||||
# Time: 115 ns Iteration: 2 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
run
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14043): $setup( negedge CENA:214500 ps, posedge CLKA &&& RET1Neq1aTENAeq1:215 ns, 1 ns );
|
||||
# Time: 215 ns Iteration: 3 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14045): $setup( posedge AA[3]:214500 ps, posedge CLKA &&& RET1Neq1aTENAeq1aCENAeq0aCOLLDISNeq1:215 ns, 1 ns );
|
||||
# Time: 215 ns Iteration: 3 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
# ** Error: /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v(14047): $setup( posedge AA[1]:214500 ps, posedge CLKA &&& RET1Neq1aTENAeq1aCENAeq0aCOLLDISNeq1:215 ns, 1 ns );
|
||||
# Time: 215 ns Iteration: 3 Instance: /rf2_32x128_wm1_tb/first_ram
|
||||
quit -sim
|
||||
# End time: 19:45:39 on Oct 19,2019, Elapsed time: 0:01:09
|
||||
# Errors: 40, Warnings: 0
|
||||
vsim work.rf2_32x128_wm1_tb
|
||||
# vsim work.rf2_32x128_wm1_tb
|
||||
# Start time: 19:45:52 on Oct 19,2019
|
||||
# ** Note: (vsim-8009) Loading existing optimized design _opt
|
||||
# Loading work.rf2_32x128_wm1_tb(fast)
|
||||
# Loading work.rf2_32x128_wm1(fast)
|
||||
quit -sim
|
||||
# End time: 19:46:00 on Oct 19,2019, Elapsed time: 0:00:08
|
||||
# Errors: 0, Warnings: 0
|
||||
# Compile of rf2_32x128_wm1_tb.v was successful.
|
||||
vsim work.rf2_32x128_wm1_tb
|
||||
# vsim work.rf2_32x128_wm1_tb
|
||||
# Start time: 19:46:06 on Oct 19,2019
|
||||
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
|
||||
# Loading work.rf2_32x128_wm1_tb(fast)
|
||||
# Loading work.rf2_32x128_wm1(fast)
|
||||
add wave -position insertpoint \
|
||||
sim:/rf2_32x128_wm1_tb/out_a_reg_data \
|
||||
sim:/rf2_32x128_wm1_tb/clk \
|
||||
sim:/rf2_32x128_wm1_tb/rs1 \
|
||||
sim:/rf2_32x128_wm1_tb/write_bit_mask \
|
||||
sim:/rf2_32x128_wm1_tb/rd \
|
||||
sim:/rf2_32x128_wm1_tb/write_data \
|
||||
sim:/rf2_32x128_wm1_tb/cena \
|
||||
sim:/rf2_32x128_wm1_tb/cenb
|
||||
run
|
||||
run
|
||||
run
|
||||
# End time: 12:47:27 on Oct 21,2019, Elapsed time: 41:01:21
|
||||
# Errors: 0, Warnings: 0
|
||||
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/vsim.wlf
Normal file
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/vsim.wlf
Normal file
Binary file not shown.
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/@_opt/_lib.qdb
Normal file
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/@_opt/_lib.qdb
Normal file
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103
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_info
Normal file
103
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_info
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
m255
|
||||
K4
|
||||
z2
|
||||
13
|
||||
!s112 1.1
|
||||
!i10d 8192
|
||||
!i10e 25
|
||||
!i10f 100
|
||||
cModel Technology
|
||||
Z0 d/nethome/lzhu308/new_work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/vsim
|
||||
T_opt
|
||||
!s110 1571528767
|
||||
V_7UfPa[jf=C_;A]OBZfl?1
|
||||
04 17 4 work rf2_32x128_wm1_tb fast 0
|
||||
=1-246e96c6651a-5daba03e-c1817-31ce
|
||||
o-quiet -auto_acc_if_foreign -work work
|
||||
Z1 tCvgOpt 0
|
||||
n@_opt
|
||||
OL;O;10.6a;65
|
||||
vdatapath_latch_rf2_32x128_wm1
|
||||
Z2 !s110 1571452808
|
||||
!i10b 1
|
||||
!s100 ]INaC9WCl@8^UmeThn]SW3
|
||||
IBVYhO=SVz2k6?d@Kom5ld2
|
||||
Z3 VDg1SIo80bB@j0V0VzS_@n1
|
||||
R0
|
||||
Z4 w1571349566
|
||||
Z5 8/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
|
||||
Z6 F/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
|
||||
L0 59
|
||||
Z7 OL;L;10.6a;65
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
Z8 !s108 1571452808.000000
|
||||
Z9 !s107 /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v|
|
||||
Z10 !s90 -reportprogress|300|-work|work|-vopt|-stats=none|/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v|
|
||||
!i113 0
|
||||
Z11 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact
|
||||
R1
|
||||
vrf2_32x128_wm1
|
||||
R2
|
||||
!i10b 1
|
||||
!s100 <lImI4^G1efnjMSXjGgZA2
|
||||
I<E?A<z^V6afIQ=`cO=ook3
|
||||
R3
|
||||
R0
|
||||
R4
|
||||
R5
|
||||
R6
|
||||
L0 2524
|
||||
R7
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R8
|
||||
R9
|
||||
R10
|
||||
!i113 0
|
||||
R11
|
||||
R1
|
||||
vrf2_32x128_wm1_error_injection
|
||||
R2
|
||||
!i10b 1
|
||||
!s100 XnID8LeZ35:6kV5chaeSG3
|
||||
IW13M?^Yg6nlZESCn3kNIH1
|
||||
R3
|
||||
R0
|
||||
R4
|
||||
R5
|
||||
R6
|
||||
L0 15219
|
||||
R7
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
R8
|
||||
R9
|
||||
R10
|
||||
!i113 0
|
||||
R11
|
||||
R1
|
||||
vrf2_32x128_wm1_tb
|
||||
!s110 1571528764
|
||||
!i10b 1
|
||||
!s100 T7Kkimi8^JkY@hYg9A4S43
|
||||
I8>G;U1;5P=S6ddc=li8]50
|
||||
R3
|
||||
R0
|
||||
w1571542951
|
||||
8/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v
|
||||
F/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v
|
||||
L0 4
|
||||
R7
|
||||
r1
|
||||
!s85 0
|
||||
31
|
||||
!s108 1571528764.000000
|
||||
!s107 /home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v|
|
||||
!s90 -reportprogress|300|-work|work|-vopt|-stats=none|/home/gtcad9/lzhu308/work/projects/vortex/design/Vortex/models/memory/cln28hpc/rf2_32x128_wm1/vsim/rf2_32x128_wm1_tb.v|
|
||||
!i113 0
|
||||
R11
|
||||
R1
|
||||
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_lib.qdb
Normal file
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_lib.qdb
Normal file
Binary file not shown.
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_lib1_0.qdb
Normal file
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_lib1_0.qdb
Normal file
Binary file not shown.
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_lib1_0.qpg
Normal file
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_lib1_0.qpg
Normal file
Binary file not shown.
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_lib1_0.qtl
Normal file
BIN
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_lib1_0.qtl
Normal file
Binary file not shown.
4
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_vmake
Normal file
4
models/memory/cln28hpc/rf2_32x128_wm1/vsim/work/_vmake
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
m255
|
||||
K4
|
||||
z0
|
||||
cModel Technology
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
14
models/memory/cln28hpm/convertToDBAll.csh
Normal file
14
models/memory/cln28hpm/convertToDBAll.csh
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#! /bin/csh
|
||||
|
||||
setenv SNPSLMD_LICENSE_FILE 1910@ece-winlic.ece.gatech.edu
|
||||
setenv PATH "${PATH}:/tools/synopsys/synthesis/j201409sp3/bin"
|
||||
setenv SYNOPSYS /tools/synopsys/synthesis/j201409sp3
|
||||
|
||||
foreach ram (`ls`)
|
||||
if ( -d ./$ram ) then
|
||||
echo $ram
|
||||
cd $ram
|
||||
lc_shell -f ../convert_lib_to_db.tcl
|
||||
cd ..
|
||||
endif
|
||||
end
|
||||
13
models/memory/cln28hpm/convert_lib_to_db.tcl
Executable file
13
models/memory/cln28hpm/convert_lib_to_db.tcl
Executable file
|
|
@ -0,0 +1,13 @@
|
|||
set SOURCE_FILES [glob *.lib]
|
||||
foreach FILE ${SOURCE_FILES} {
|
||||
read_lib $FILE
|
||||
redirect -variable CURR_LIB {get_lib}
|
||||
|
||||
set CURR_LIB [string range $CURR_LIB 2 end-3]
|
||||
set CURR_LIB [lindex $CURR_LIB 0]
|
||||
set FILENAME [string range $FILE 0 end-4]
|
||||
write_lib $CURR_LIB -output ${FILENAME}.db
|
||||
remove_lib $CURR_LIB
|
||||
}
|
||||
|
||||
exit
|
||||
3759
models/memory/cln28hpm/rf2_128x128_wm1/command.log
Normal file
3759
models/memory/cln28hpm/rf2_128x128_wm1/command.log
Normal file
File diff suppressed because it is too large
Load diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
3759
models/memory/cln28hpm/rf2_256x128_wm1/command.log
Normal file
3759
models/memory/cln28hpm/rf2_256x128_wm1/command.log
Normal file
File diff suppressed because it is too large
Load diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
3759
models/memory/cln28hpm/rf2_256x19_wm0/command.log
Normal file
3759
models/memory/cln28hpm/rf2_256x19_wm0/command.log
Normal file
File diff suppressed because it is too large
Load diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
3759
models/memory/cln28hpm/rf2_32x128_wm1/command.log
Normal file
3759
models/memory/cln28hpm/rf2_32x128_wm1/command.log
Normal file
File diff suppressed because it is too large
Load diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
22402
syn/dc.log
22402
syn/dc.log
File diff suppressed because it is too large
Load diff
|
|
@ -1,9 +1,9 @@
|
|||
set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache]
|
||||
set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_125c.db dw_foundation.sldb]
|
||||
set search_path [concat /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_db/ /nethome/dshim8/Desktop/GTCAD-3DPKG-v3/example/tech/cln28hpm/2d_hard_db/ ../rtl/ ../rtl/interfaces ../rtl/pipe_regs ../rtl/shared_memory ../rtl/cache ../models/memory/cln28hpm/2d_hardmacro_db]
|
||||
set link_library [concat * sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db rf2_32x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x128_wm1_ss_0p81v_0p81v_m40c.db rf2_256x19_wm0_ss_0p81v_0p81v_m40c.db rf2_128x128_wm1_ss_0p81v_0p81v_m40c.db dw_foundation.sldb]
|
||||
set symbol_library {}
|
||||
set target_library [concat sc12mc_cln28hpm_base_ulvt_c35_ssg_typical_max_0p81v_m40c.db]
|
||||
|
||||
set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v \
|
||||
set verilog_files [ list VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v VX_Cache_Bank.v VX_cache_data.v VX_d_cache.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v Vortex.v VX_cache_bank_valid.v \
|
||||
]
|
||||
# set verilog_files [ list Vortex.v VX_countones.v VX_priority_encoder_w_mask.v VX_dram_req_rsp_inter.v cache_set.v VX_Cache_Bank.v VX_Cache_Block_DM.v VX_cache_data.v VX_d_cache.v VX_generic_pc.v VX_bank_valids.v VX_priority_encoder_sm.v VX_shared_memory.v VX_shared_memory_block.v VX_dmem_controller.v VX_generic_priority_encoder.v VX_generic_stack.v VX_join_inter.v VX_csr_wrapper.v VX_csr_req_inter.v VX_csr_wb_inter.v VX_gpgpu_inst.v VX_gpu_inst_req_inter.v VX_wstall_inter.v VX_inst_exec_wb_inter.v VX_lsu.v VX_execute_unit.v VX_lsu_addr_gen.v VX_inst_multiplex.v VX_exec_unit_req_inter.v VX_lsu_req_inter.v VX_alu.v VX_back_end.v VX_gpr_stage.v VX_gpr_data_inter.v VX_csr_handler.v VX_decode.v VX_define.v VX_scheduler.v VX_fetch.v VX_front_end.v VX_generic_register.v VX_gpr.v VX_gpr_wrapper.v VX_one_counter.v VX_priority_encoder.v VX_warp_scheduler.v VX_writeback.v byte_enabled_simple_dual_port_ram.v VX_branch_response_inter.v VX_dcache_request_inter.v VX_dcache_response_inter.v VX_frE_to_bckE_req_inter.v VX_gpr_clone_inter.v VX_gpr_jal_inter.v VX_gpr_read_inter.v VX_gpr_wspawn_inter.v VX_icache_request_inter.v VX_icache_response_inter.v VX_inst_mem_wb_inter.v VX_inst_meta_inter.v VX_jal_response_inter.v VX_mem_req_inter.v VX_mw_wb_inter.v VX_warp_ctl_inter.v VX_wb_inter.v VX_d_e_reg.v VX_f_d_reg.v \
|
||||
# ]
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue