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minor update

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This commit is contained in:
Blaise Tine 2024-08-02 23:32:34 -07:00
parent 76f74b8a59
commit 52c5f1ff6b
9 changed files with 21 additions and 20 deletions
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5
hw/rtl/cache/VX_cache_data.sv vendored
View file

@ -62,7 +62,6 @@ module VX_cache_data #(
`UNUSED_SPARAM (INSTANCE_ID)
`UNUSED_PARAM (BANK_ID)
`UNUSED_PARAM (WORD_SIZE)
`UNUSED_VAR (reset)
`UNUSED_VAR (stall)
`UNUSED_VAR (line_addr)
`UNUSED_VAR (init)
@ -91,7 +90,7 @@ module VX_cache_data #(
.SIZE (`CS_LINES_PER_BANK)
) byteen_store (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (write || fill || flush),
.write (init || write || fill || flush),
.wren (1'b1),
@ -162,7 +161,7 @@ module VX_cache_data #(
.RW_ASSERT (1)
) data_store (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (line_read),
.write (line_write),
.wren (line_wren),

2
hw/rtl/cache/VX_cache_mshr.sv vendored
View file

@ -232,7 +232,7 @@ module VX_cache_mshr #(
.LUTRAM (1)
) entries (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (1'b1),
.write (allocate_valid),
.wren (1'b1),

3
hw/rtl/cache/VX_cache_tags.sv vendored
View file

@ -57,7 +57,6 @@ module VX_cache_tags #(
);
`UNUSED_SPARAM (INSTANCE_ID)
`UNUSED_PARAM (BANK_ID)
`UNUSED_VAR (reset)
`UNUSED_VAR (lookup)
// valid, dirty, tag
@ -130,7 +129,7 @@ module VX_cache_tags #(
.RW_ASSERT (1)
) tag_store (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (line_read),
.write (line_write),
.wren (1'b1),

2
hw/rtl/core/VX_fetch.sv
View file

@ -56,7 +56,7 @@ module VX_fetch import VX_gpu_pkg::*; #(
.LUTRAM (1)
) tag_store (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (1'b1),
.write (icache_req_fire),
.wren (1'b1),

2
hw/rtl/core/VX_ipdom_stack.sv
View file

@ -72,7 +72,7 @@ module VX_ipdom_stack #(
.LUTRAM (OUT_REG ? 0 : 1)
) store (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (1'b1),
.write (push),
.wren (1'b1),

7
hw/rtl/core/VX_operands.sv
View file

@ -277,14 +277,13 @@ module VX_operands import VX_gpu_pkg::*; #(
.DATAW (`XLEN * `NUM_THREADS),
.SIZE (PER_BANK_REGS * PER_ISSUE_WARPS),
.WRENW (BYTEENW),
`ifdef GPR_RESET
.RESET_RAM (1),
`endif
.NO_RWCHECK (1)
) gpr_ram (
.clk (clk),
`ifdef GPR_RESET
.reset (reset),
`else
.reset (1'b0),
`endif
.read (pipe_fire_st1),
.wren (wren),
.write (gpr_wr_enabled),

14
hw/rtl/libs/VX_dp_ram.sv
View file

@ -24,6 +24,7 @@ module VX_dp_ram #(
parameter LUTRAM = 0,
parameter RW_ASSERT = 0,
parameter RESET_RAM = 0,
parameter READ_ENABLE = 0,
parameter INIT_ENABLE = 0,
parameter INIT_FILE = "",
parameter [DATAW-1:0] INIT_VALUE = 0,
@ -198,13 +199,16 @@ module VX_dp_ram #(
for (integer i = 0; i < SIZE; ++i) begin
ram[i] <= DATAW'(INIT_VALUE);
end
prev_write <= 0;
prev_data <= '0;
prev_waddr <= '0;
end else begin
if (write) begin
ram[waddr] <= ram_n;
end
end
if (reset) begin
prev_write <= 0;
prev_data <= '0;
prev_waddr <= '0;
end else begin
prev_write <= write;
prev_data <= ram[waddr];
prev_waddr <= waddr;
@ -227,9 +231,9 @@ module VX_dp_ram #(
if (OUT_REG != 0) begin
reg [DATAW-1:0] rdata_r;
always @(posedge clk) begin
if (reset) begin
if (READ_ENABLE && reset) begin
rdata_r <= '0;
end else if (read) begin
end else if (!READ_ENABLE || read) begin
rdata_r <= rdata_w;
end
end

4
hw/rtl/libs/VX_fifo_queue.sv
View file

@ -178,7 +178,7 @@ module VX_fifo_queue #(
.LUTRAM (LUTRAM)
) dp_ram (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (1'b1),
.write (push),
.wren (1'b1),
@ -227,7 +227,7 @@ module VX_fifo_queue #(
.LUTRAM (LUTRAM)
) dp_ram (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (1'b1),
.write (push),
.wren (1'b1),

2
hw/rtl/libs/VX_index_buffer.sv
View file

@ -54,7 +54,7 @@ module VX_index_buffer #(
.LUTRAM (LUTRAM)
) data_table (
.clk (clk),
.reset (1'b0),
.reset (reset),
.read (1'b1),
.write (acquire_en),
.wren (1'b1),