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Merge branch 'master' of https://github.gatech.edu/casl/Vortex

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This commit is contained in:
Blaise Tine 2019-11-24 00:43:39 -05:00
commit 54ece84f79
7 changed files with 92860 additions and 7 deletions
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8
rvvector/benchmark_temp/Makefile
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@ -1,11 +1,11 @@
LIB_PATH = ../../runtime
COMP = /nethome/ekim79/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-gcc
COMP = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-gcc
CC_FLAGS = -ffreestanding -O0 -Wl,--gc-sections -nostartfiles -nostdlib -nostartfiles -nodefaultlibs -Wl,-Bstatic,-T,$(LIB_PATH)/mains/vortex_link.ld -march=rv32imv -mabi=ilp32
DMP = /nethome/ekim79/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objdump
CPY = /nethome/ekim79/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objcopy
DMP = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-objdump
CPY = /home/priya/dev/riscv_vec/riscv-gnu/bin/riscv32-unknown-elf-objcopy
# VX_STR = ../../startup/vx_start.s
@ -21,7 +21,7 @@ VX_VEC2 = vx_vec_saxpy.s #float --> int
VX_VEC3 = vx_vec_sgemm_float.s #float --> int
VX_VEC4 = vx_vec_vsadd.s
VX_VEC5 = vx_vec_memcpy.s
LIBS = /nethome/ekim79/riscv-gnu-toolchain/drops/riscv32-unknown-elf/lib/libc.a /nethome/ekim79/riscv-gnu-toolchain/drops/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
LIBS = /home/priya/dev/riscv_vec/riscv-gnu/riscv32-unknown-elf/lib/libc.a /home/priya/dev/riscv_vec/riscv-gnu/riscv32-unknown-elf/lib/libstdc++.a -static-libgcc -lgcc
VX_MAIN = vx_vec_benchmark

87070
rvvector/benchmark_temp/vx_vec_benchmark.dump Normal file
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BIN
rvvector/benchmark_temp/vx_vec_benchmark.elf Executable file
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rvvector/benchmark_temp/vx_vec_benchmark.hex Normal file
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10
rvvector/benchmark_temp/vx_vec_saxpy.s
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@ -28,15 +28,21 @@
# ret
# a0 n, rs1 a, a2 x, a3 y
# a0 n, a1 a, a2 x, a3 y
vx_vec_saxpy:
vsetvli a4, a0, e32, m8
vsetvli a4, a0, e32, m1
saxpy:
vlw.v v0, (a2)
sub a0, a0, a4
slli a4, a4, 2
add a2, a2, a4
vlw.v v1, (a3)
vmacc.vx v1, rs1, v0
vmul.vx v0, v0, a1
# vmul.vv v0, v0, v1
# li x1, 10
# vmul.vx v0, v0, x1
vadd.vv v1, v0, v1
vsw.v v1, (a3)
add a3, a3, a4
bnez a0, saxpy

181
simX/instruction.cpp
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@ -2016,6 +2016,64 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
}
}
break;
case 37: //vmul
{
D(3, "vmul");
uint8_t *result_ptr;
vector<Reg<char *>> & vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> & vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> & vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (*first_ptr * *second_ptr);
D(3,"Comparing " << *first_ptr << " + " << *second_ptr << " = " << result);
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
for(uint8_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = 0;
}
}
else if(c.vtype.vsew == 16) {
uint16_t *result_ptr;
for(uint16_t i = 0; i < c.vl; i++){
uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (*first_ptr * *second_ptr);
D(3,"Comparing " << *first_ptr << " + " << *second_ptr << " = " << result);
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
for(uint16_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = 0;
}
} else if(c.vtype.vsew == 32) {
uint32_t *result_ptr;
for(uint32_t i = 0; i < c.vl; i++){
uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (*first_ptr * *second_ptr);
D(3,"Comparing " << *first_ptr << " + " << *second_ptr << " = " << result);
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
for(Word i = c.vl; i < VLMAX; i++){
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = 0;
}
}
}
break;
case 45: //vmacc
{
D(3, "vmacc");
@ -2077,6 +2135,129 @@ void Instruction::executeOn(Warp &c, trace_inst_t * trace_inst) {
}
}
break;
case 6:
{
switch(func6)
{
case 0:
{
D(3, "vmadd.vx");
uint8_t *result_ptr;
//vector<Reg<char *>> & vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> & vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> & vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
//uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (reg[rsrc[0]] + *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
for(uint8_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = 0;
}
}
else if(c.vtype.vsew == 16) {
uint16_t *result_ptr;
for(uint16_t i = 0; i < c.vl; i++){
//uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (reg[rsrc[0]] + *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
for(uint16_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = 0;
}
} else if(c.vtype.vsew == 32) {
uint32_t *result_ptr;
for(uint32_t i = 0; i < c.vl; i++){
//uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (reg[rsrc[0]] + *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
for(Word i = c.vl; i < VLMAX; i++){
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = 0;
}
}
}
break;
case 37: //vmul.vx
{
D(3, "vmul.vx");
uint8_t *result_ptr;
//vector<Reg<char *>> & vr1 = c.vreg[rsrc[0]];
vector<Reg<char *>> & vr2 = c.vreg[rsrc[1]];
vector<Reg<char *>> & vd = c.vreg[rdest];
if(c.vtype.vsew == 8){
for(uint8_t i = 0; i < c.vl; i++){
//uint8_t *first_ptr = (uint8_t *)vr1[i].val;
uint8_t *second_ptr = (uint8_t *)vr2[i].val;
uint8_t result = (reg[rsrc[0]] * *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = result;
}
for(uint8_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint8_t *) vd[i].val;
*result_ptr = 0;
}
}
else if(c.vtype.vsew == 16) {
uint16_t *result_ptr;
for(uint16_t i = 0; i < c.vl; i++){
//uint16_t *first_ptr = (uint16_t *)vr1[i].val;
uint16_t *second_ptr = (uint16_t *)vr2[i].val;
uint16_t result = (reg[rsrc[0]] * *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = result;
}
for(uint16_t i = c.vl; i < VLMAX; i++){
result_ptr = (uint16_t *) vd[i].val;
*result_ptr = 0;
}
} else if(c.vtype.vsew == 32) {
uint32_t *result_ptr;
for(uint32_t i = 0; i < c.vl; i++){
//uint32_t *first_ptr = (uint32_t *)vr1[i].val;
uint32_t *second_ptr = (uint32_t *)vr2[i].val;
uint32_t result = (reg[rsrc[0]] * *second_ptr);
D(3,"Comparing " << reg[rsrc[0]] << " + " << *second_ptr << " = " << result);
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = result;
}
for(Word i = c.vl; i < VLMAX; i++){
result_ptr = (uint32_t *) vd[i].val;
*result_ptr = 0;
}
}
}
break;
}
}
break;
case 7:
{
is_vec = true;

3
simX/test_riscv.sh
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@ -3,4 +3,5 @@ echo start > results.txt
# echo ../kernel/vortex_test.hex
make
printf "Fasten your seatbelts ladies and gentelmen!!\n\n\n\n"
cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
#cd obj_dir && ./Vcache_simX -E -a rv32i --core ../../runtime/mains/simple/vx_simple_main.hex -s -b 1> emulator.debug
cd obj_dir && ./Vcache_simX -E -a rv32i --core /home/priya/Desktop/new_vortex/Vortex/rvvector/benchmark_temp/vx_vec_benchmark.hex -s -b 1> emulator.debug