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Generate LIB files for rf2_32x128_wm1

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This commit is contained in:
Lingjun Zhu 2019-10-14 17:08:18 -04:00
parent f28cd286e6
commit 5680b997b5
23 changed files with 284430 additions and 102 deletions
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84
models/memory/cln28hpc/VX_gpr.v
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@ -1,84 +0,0 @@
`include "VX_define.v"
module VX_gpr (
input wire clk,
input wire valid_write_request,
VX_gpr_read_inter VX_gpr_read,
VX_wb_inter VX_writeback_inter,
output reg[`NT_M1:0][31:0] out_a_reg_data,
output reg[`NT_M1:0][31:0] out_b_reg_data
);
wire write_enable;
assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
byte_enabled_simple_dual_port_ram first_ram(
.we (write_enable),
.clk (clk),
.waddr (VX_writeback_inter.rd),
.raddr1(VX_gpr_read.rs1),
.raddr2(VX_gpr_read.rs2),
.be (VX_writeback_inter.wb_valid),
.wdata (VX_writeback_inter.write_data),
.q1 (out_a_reg_data),
.q2 (out_b_reg_data)
);
// // USING RAM blocks
// // First RAM
// byte_enabled_simple_dual_port_ram first_ram(
// .we (write_enable),
// .clk (clk),
// .waddr(VX_writeback_inter.rd),
// .raddr(VX_gpr_read.rs1),
// .be (VX_writeback_inter.wb_valid),
// .wdata(VX_writeback_inter.write_data),
// .q (out_a_reg_data)
// );
// // Second RAM block
// byte_enabled_simple_dual_port_ram second_ram(
// .we (write_enable),
// .clk (clk),
// .waddr(VX_writeback_inter.rd),
// .raddr(VX_gpr_read.rs2),
// .be (VX_writeback_inter.wb_valid),
// .wdata(VX_writeback_inter.write_data),
// .q (out_b_reg_data)
// );
// logic[`NT_M1:0][31:0] gpr[31:0]; // gpr[register_number][thread_number][data_bits]
// wire write_enable;
// assign write_enable = valid_write_request && ((VX_writeback_inter.wb != 0) && (VX_writeback_inter.rd != 5'h0));
// assign read_enable = valid_request;
// // Using Registers
// integer thread_index;
// always_ff@(posedge clk)
// begin
// if (write_enable) begin
// for (thread_index = 0; thread_index <= `NT_M1; thread_index = thread_index + 1) begin
// if (VX_writeback_inter.wb_valid[thread_index]) begin
// gpr[VX_writeback_inter.rd][thread_index] <= VX_writeback_inter.write_data[thread_index];
// end
// end
// end
// out_a_reg_data <= gpr[VX_gpr_read.rs1];
// out_b_reg_data <= gpr[VX_gpr_read.rs2];
// end
endmodule

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.cpf
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@ -30,7 +30,7 @@
# Pipeline: Off
# Read Disturb Test: Off
#
# Creation Date: Sun Oct 13 11:08:47 2019
# Creation Date: Mon Oct 14 16:59:57 2019
# Version: r0p0
#
set_cpf_version 1.1

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.ctl
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@ -30,7 +30,7 @@
// Pipeline: Off
// Read Disturb Test: Off
//
// Creation Date: Sun Oct 13 11:08:48 2019
// Creation Date: Mon Oct 14 16:59:58 2019
// Version: r0p0
STIL 1.0 {
CTL P2001.10;

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.lef
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@ -4,7 +4,7 @@
# PhyVGen V 8.8.0
# ARM Version r0p0
# Creation Date: Sun Oct 13 11:08:55 2019
# Creation Date: Mon Oct 14 17:00:05 2019
# Memory Configuration:

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.mdt
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@ -30,7 +30,7 @@
// Pipeline: Off
// Read Disturb Test: Off
//
// Creation Date: Sun Oct 13 11:08:49 2019
// Creation Date: Mon Oct 14 16:59:59 2019
// Version: r0p0
// Modeling Assumptions: This is Sequential Synchronous Mentor model
// with Mentor ATPG primitives used to test UTI and generate test

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.memlib
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@ -27,7 +27,7 @@
// Redundant Columns: 2
// Test Muxes On
//
// Creation Date: Sun Oct 13 11:08:56 2019
// Creation Date: Mon Oct 14 17:01:15 2019
// Version: r0p0
//
// Modeling Assumptions:

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.tv
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@ -30,7 +30,7 @@
// Pipeline: Off
// Read Disturb Test: Off
//
// Creation Date: Sun Oct 13 11:09:22 2019
// Creation Date: Mon Oct 14 17:01:42 2019
// Version: r0p0
//
// Verified

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
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@ -30,7 +30,7 @@
// Pipeline: Off
// Read Disturb Test: Off
//
// Creation Date: Sun Oct 13 11:09:24 2019
// Creation Date: Mon Oct 14 17:01:43 2019
// Version: r0p0
//
// Modeling Assumptions: This model supports full gate level simulation

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_antenna.clf
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@ -4,7 +4,7 @@
# PhyVGen V 8.8.0
# ARM Version r0p0
# Creation Date: Sun Oct 13 11:08:55 2019
# Creation Date: Mon Oct 14 17:00:05 2019
defineGateSize "rf2_32x128_wm1" "AA[0]" 0.014

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.avm
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@ -13,7 +13,7 @@
#
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 13 11:07:58 2019
# Creation Date: Mon Oct 14 16:59:07 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.dat
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@ -13,7 +13,7 @@
#
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 13 11:08:28 2019
# Creation Date: Mon Oct 14 16:59:37 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1

71103
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib Normal file
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71103
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.lib_sh5p1cm Normal file
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2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ff_0p99v_0p99v_m40c.ps
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@ -13,7 +13,7 @@
%
% Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
%
% Creation Date: Sun Oct 13 11:09:08 2019
% Creation Date: Mon Oct 14 17:01:28 2019
%
% Instance Options:
% Instance Name: rf2_32x128_wm1

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_rtl.v
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@ -31,7 +31,7 @@
// Retention: on
// Power Gating: off
//
// Creation Date: Sun Oct 13 11:09:26 2019
// Creation Date: Mon Oct 14 17:01:45 2019
// Version: r0p0
//
// Verified

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.avm
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@ -13,7 +13,7 @@
#
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 13 11:08:07 2019
# Creation Date: Mon Oct 14 16:59:16 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.dat
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@ -13,7 +13,7 @@
#
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 13 11:08:34 2019
# Creation Date: Mon Oct 14 16:59:43 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1

71103
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.lib Normal file
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models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_ss_0p81v_0p81v_125c.ps
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%
% Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
%
% Creation Date: Sun Oct 13 11:09:15 2019
% Creation Date: Mon Oct 14 17:01:34 2019
%
% Instance Options:
% Instance Name: rf2_32x128_wm1

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.avm
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@ -13,7 +13,7 @@
#
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 13 11:08:16 2019
# Creation Date: Mon Oct 14 16:59:25 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1

2
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.dat
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@ -13,7 +13,7 @@
#
# Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
#
# Creation Date: Sun Oct 13 11:08:40 2019
# Creation Date: Mon Oct 14 16:59:49 2019
#
# Instance Options:
# Instance Name: rf2_32x128_wm1

71103
models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.lib Normal file
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models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1_tt_0p81v_0p81v_0c.ps
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%
% Compiler Name: High Capacity Two Port Register File SVT MVT Compiler
%
% Creation Date: Sun Oct 13 11:09:21 2019
% Creation Date: Mon Oct 14 17:01:41 2019
%
% Instance Options:
% Instance Name: rf2_32x128_wm1