mirror of
https://github.com/vortexgpgpu/vortex.git
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gpr_slice redesign to use multi-banking architecture
This commit is contained in:
Blaise Tine
parent
ed11defd71
commit
56e9e19508
1 changed files with 134 additions and 187 deletions
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@ -14,8 +14,9 @@
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`include "VX_define.vh"
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module VX_gpr_slice import VX_gpu_pkg::*; #(
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parameter CORE_ID = 0,
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parameter CACHE_ENABLE = 0
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parameter CORE_ID = 0,
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parameter NUM_BANKS = 4,
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parameter OUT_REG = 0
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) (
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input wire clk,
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input wire reset,
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@ -25,180 +26,121 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
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VX_operands_if.master operands_if
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);
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`UNUSED_PARAM (CORE_ID)
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localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + 1 + `EX_BITS + `INST_OP_BITS + `INST_ARGS_BITS + `NR_BITS;
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localparam NUM_SRC_REGS = 3;
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localparam REQ_SEL_BITS = `CLOG2(NUM_SRC_REGS);
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localparam REQ_SEL_WIDTH = `UP(REQ_SEL_BITS);
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localparam BANK_SEL_BITS = `CLOG2(NUM_BANKS);
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localparam BANK_SEL_WIDTH = `UP(BANK_SEL_BITS);
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localparam PER_BANK_REGS = `NUM_REGS / NUM_BANKS;
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localparam DATAW = `UUID_WIDTH + ISSUE_WIS_W + `NUM_THREADS + `PC_BITS + 1 + `EX_BITS + `INST_OP_BITS + `INST_ARGS_BITS + `NR_BITS + 3 * `NUM_THREADS * `XLEN;
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localparam RAM_ADDRW = `LOG2UP(`NUM_REGS * PER_ISSUE_WARPS);
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localparam PER_BANK_ADDRW = RAM_ADDRW - BANK_SEL_BITS;
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localparam XLEN_SIZE = `XLEN / 8;
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localparam BYTEENW = `NUM_THREADS * XLEN_SIZE;
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localparam STATE_IDLE = 2'd0;
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localparam STATE_FETCH1 = 2'd1;
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localparam STATE_FETCH2 = 2'd2;
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localparam STATE_FETCH3 = 2'd3;
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localparam STATE_BITS = 2;
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`UNUSED_VAR (writeback_if.data.sop)
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wire [`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data;
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reg [`NR_BITS-1:0] gpr_rd_rid, gpr_rd_rid_n;
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reg [ISSUE_WIS_W-1:0] gpr_rd_wis, gpr_rd_wis_n;
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wire [NUM_SRC_REGS-1:0] req_valid_in;
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wire [NUM_SRC_REGS-1:0] req_ready_in;
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wire [NUM_SRC_REGS-1:0][PER_BANK_ADDRW-1:0] req_data_in;
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wire [NUM_SRC_REGS-1:0][BANK_SEL_WIDTH-1:0] req_bank_idx;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data [PER_ISSUE_WARPS-1:0];
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reg [`NUM_THREADS-1:0][`XLEN-1:0] cache_data_n [PER_ISSUE_WARPS-1:0];
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reg [`NR_BITS-1:0] cache_reg [PER_ISSUE_WARPS-1:0];
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reg [`NR_BITS-1:0] cache_reg_n [PER_ISSUE_WARPS-1:0];
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reg [`NUM_THREADS-1:0] cache_tmask [PER_ISSUE_WARPS-1:0];
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reg [`NUM_THREADS-1:0] cache_tmask_n [PER_ISSUE_WARPS-1:0];
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reg [PER_ISSUE_WARPS-1:0] cache_eop, cache_eop_n;
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wire [NUM_BANKS-1:0] gpr_rd_valid;
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wire [NUM_BANKS-1:0][PER_BANK_ADDRW-1:0] gpr_rd_addr;
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wire [NUM_BANKS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] gpr_rd_data;
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wire [NUM_BANKS-1:0][REQ_SEL_WIDTH-1:0] gpr_rd_req_idx;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs1_data, rs1_data_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs2_data, rs2_data_n;
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reg [`NUM_THREADS-1:0][`XLEN-1:0] rs3_data, rs3_data_n;
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reg [NUM_SRC_REGS-1:0][`NUM_THREADS-1:0][`XLEN-1:0] src_data, src_data_n;
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wire [NUM_SRC_REGS-1:0] src_valid;
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reg [NUM_SRC_REGS-1:0] data_fetched;
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reg data_ready;
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reg [STATE_BITS-1:0] state, state_n;
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reg [`NR_BITS-1:0] rs2, rs2_n;
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reg [`NR_BITS-1:0] rs3, rs3_n;
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reg rs2_ready, rs2_ready_n;
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reg rs3_ready, rs3_ready_n;
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reg data_ready, data_ready_n;
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assign src_valid[0] = (scoreboard_if.data.rs1 != 0) && ~data_fetched[0];
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assign src_valid[1] = (scoreboard_if.data.rs2 != 0) && ~data_fetched[1];
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assign src_valid[2] = (scoreboard_if.data.rs3 != 0) && ~data_fetched[2];
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wire stg_valid_in, stg_ready_in;
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assign req_valid_in[0] = scoreboard_if.valid && src_valid[0];
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assign req_valid_in[1] = scoreboard_if.valid && src_valid[1];
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assign req_valid_in[2] = scoreboard_if.valid && src_valid[2];
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wire is_rs1_zero = (scoreboard_if.data.rs1 == 0);
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wire is_rs2_zero = (scoreboard_if.data.rs2 == 0);
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wire is_rs3_zero = (scoreboard_if.data.rs3 == 0);
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if (ISSUE_WIS != 0) begin
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assign req_data_in[0] = {scoreboard_if.data.wis, scoreboard_if.data.rs1[`NR_BITS-1:BANK_SEL_BITS]};
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assign req_data_in[1] = {scoreboard_if.data.wis, scoreboard_if.data.rs2[`NR_BITS-1:BANK_SEL_BITS]};
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assign req_data_in[2] = {scoreboard_if.data.wis, scoreboard_if.data.rs3[`NR_BITS-1:BANK_SEL_BITS]};
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end else begin
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assign req_data_in[0] = {scoreboard_if.data.rs1[`NR_BITS-1:BANK_SEL_BITS]};
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assign req_data_in[1] = {scoreboard_if.data.rs2[`NR_BITS-1:BANK_SEL_BITS]};
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assign req_data_in[2] = {scoreboard_if.data.rs3[`NR_BITS-1:BANK_SEL_BITS]};
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end
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if (NUM_BANKS > 1) begin
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assign req_bank_idx[0] = scoreboard_if.data.rs1[BANK_SEL_BITS-1:0];
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assign req_bank_idx[1] = scoreboard_if.data.rs2[BANK_SEL_BITS-1:0];
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assign req_bank_idx[2] = scoreboard_if.data.rs3[BANK_SEL_BITS-1:0];
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end else begin
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assign req_bank_idx = '0;
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end
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VX_stream_xbar #(
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.NUM_INPUTS (NUM_SRC_REGS),
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.NUM_OUTPUTS (NUM_BANKS),
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.DATAW (PER_BANK_ADDRW),
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.PERF_CTR_BITS(`PERF_CTR_BITS),
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.OUT_BUF (1) // single-cycle EB since ready_out=1
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) req_xbar (
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.clk (clk),
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.reset (reset),
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`UNUSED_PIN(collisions),
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.valid_in (req_valid_in),
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.data_in (req_data_in),
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.sel_in (req_bank_idx),
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.ready_in (req_ready_in),
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.valid_out (gpr_rd_valid),
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.data_out (gpr_rd_addr),
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.sel_out (gpr_rd_req_idx),
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.ready_out ({NUM_BANKS{1'b1}})
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);
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always @(*) begin
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state_n = state;
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rs2_n = rs2;
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rs3_n = rs3;
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rs2_ready_n = rs2_ready;
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rs3_ready_n = rs3_ready;
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rs1_data_n = rs1_data;
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rs2_data_n = rs2_data;
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rs3_data_n = rs3_data;
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cache_data_n = cache_data;
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cache_reg_n = cache_reg;
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cache_tmask_n= cache_tmask;
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cache_eop_n = cache_eop;
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gpr_rd_rid_n = gpr_rd_rid;
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gpr_rd_wis_n = gpr_rd_wis;
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data_ready_n = data_ready;
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case (state)
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STATE_IDLE: begin
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if (operands_if.valid && operands_if.ready) begin
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data_ready_n = 0;
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end
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if (scoreboard_if.valid && data_ready_n == 0) begin
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data_ready_n = 1;
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if (is_rs3_zero || (CACHE_ENABLE != 0 &&
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scoreboard_if.data.rs3 == cache_reg[scoreboard_if.data.wis] &&
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(scoreboard_if.data.tmask & cache_tmask[scoreboard_if.data.wis]) == scoreboard_if.data.tmask)) begin
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rs3_data_n = (is_rs3_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if.data.wis];
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rs3_ready_n = 1;
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end else begin
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rs3_ready_n = 0;
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gpr_rd_rid_n = scoreboard_if.data.rs3;
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data_ready_n = 0;
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state_n = STATE_FETCH3;
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end
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if (is_rs2_zero || (CACHE_ENABLE != 0 &&
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scoreboard_if.data.rs2 == cache_reg[scoreboard_if.data.wis] &&
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(scoreboard_if.data.tmask & cache_tmask[scoreboard_if.data.wis]) == scoreboard_if.data.tmask)) begin
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rs2_data_n = (is_rs2_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if.data.wis];
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rs2_ready_n = 1;
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end else begin
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rs2_ready_n = 0;
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gpr_rd_rid_n = scoreboard_if.data.rs2;
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data_ready_n = 0;
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state_n = STATE_FETCH2;
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end
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if (is_rs1_zero || (CACHE_ENABLE != 0 &&
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scoreboard_if.data.rs1 == cache_reg[scoreboard_if.data.wis] &&
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(scoreboard_if.data.tmask & cache_tmask[scoreboard_if.data.wis]) == scoreboard_if.data.tmask)) begin
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rs1_data_n = (is_rs1_zero || CACHE_ENABLE == 0) ? '0 : cache_data[scoreboard_if.data.wis];
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end else begin
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gpr_rd_rid_n = scoreboard_if.data.rs1;
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data_ready_n = 0;
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state_n = STATE_FETCH1;
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end
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end
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gpr_rd_wis_n = scoreboard_if.data.wis;
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rs2_n = scoreboard_if.data.rs2;
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rs3_n = scoreboard_if.data.rs3;
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end
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STATE_FETCH1: begin
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rs1_data_n = gpr_rd_data;
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if (~rs2_ready) begin
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gpr_rd_rid_n = rs2;
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state_n = STATE_FETCH2;
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end else if (~rs3_ready) begin
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gpr_rd_rid_n = rs3;
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state_n = STATE_FETCH3;
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end else begin
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data_ready_n = 1;
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state_n = STATE_IDLE;
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end
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end
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STATE_FETCH2: begin
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rs2_data_n = gpr_rd_data;
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if (~rs3_ready) begin
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gpr_rd_rid_n = rs3;
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state_n = STATE_FETCH3;
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end else begin
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data_ready_n = 1;
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state_n = STATE_IDLE;
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end
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end
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STATE_FETCH3: begin
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rs3_data_n = gpr_rd_data;
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data_ready_n = 1;
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state_n = STATE_IDLE;
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end
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endcase
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if (CACHE_ENABLE != 0 && writeback_if.valid) begin
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if ((cache_reg[writeback_if.data.wis] == writeback_if.data.rd)
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|| (cache_eop[writeback_if.data.wis] && writeback_if.data.sop)) begin
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for (integer j = 0; j < `NUM_THREADS; ++j) begin
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if (writeback_if.data.tmask[j]) begin
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cache_data_n[writeback_if.data.wis][j] = writeback_if.data.data[j];
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end
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end
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cache_reg_n[writeback_if.data.wis] = writeback_if.data.rd;
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cache_eop_n[writeback_if.data.wis] = writeback_if.data.eop;
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cache_tmask_n[writeback_if.data.wis] = writeback_if.data.sop ? writeback_if.data.tmask :
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(cache_tmask_n[writeback_if.data.wis] | writeback_if.data.tmask);
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src_data_n = src_data;
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for (integer b = 0; b < NUM_BANKS; ++b) begin
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if (gpr_rd_valid[b]) begin
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src_data_n[gpr_rd_req_idx[b]] = gpr_rd_data[b];
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end
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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state <= STATE_IDLE;
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cache_eop <= {PER_ISSUE_WARPS{1'b1}};
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data_ready <= 0;
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data_fetched <= '0;
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src_data <= '0;
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data_ready <= '0;
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end else begin
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state <= state_n;
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cache_eop <= cache_eop_n;
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data_ready <= data_ready_n;
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if (scoreboard_if.ready) begin
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data_fetched <= '0;
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src_data <= '0;
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data_ready <= '0;
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end else begin
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data_fetched <= data_fetched | req_ready_in;
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src_data <= src_data_n;
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data_ready <= scoreboard_if.valid
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&& (~src_valid[0] || req_ready_in[0])
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&& (~src_valid[1] || req_ready_in[1])
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&& (~src_valid[2] || req_ready_in[2]);
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end
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end
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gpr_rd_rid <= gpr_rd_rid_n;
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gpr_rd_wis <= gpr_rd_wis_n;
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rs2_ready <= rs2_ready_n;
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rs3_ready <= rs3_ready_n;
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rs2 <= rs2_n;
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rs3 <= rs3_n;
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rs1_data <= rs1_data_n;
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rs2_data <= rs2_data_n;
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rs3_data <= rs3_data_n;
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cache_data <= cache_data_n;
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cache_reg <= cache_reg_n;
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cache_tmask <= cache_tmask_n;
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end
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wire stg_valid_in, stg_ready_in;
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assign stg_valid_in = scoreboard_if.valid && data_ready;
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assign scoreboard_if.ready = stg_ready_in && data_ready;
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// We use a toggle buffer since the input signal also toggles
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VX_toggle_buffer #(
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.DATAW (DATAW)
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) toggle_buffer (
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.DATAW (DATAW),
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.PASSTHRU (~OUT_REG)
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) rsp_buffer (
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.clk (clk),
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.reset (reset),
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.valid_in (stg_valid_in),
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@ -211,7 +153,10 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
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scoreboard_if.data.ex_type,
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scoreboard_if.data.op_type,
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scoreboard_if.data.op_args,
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scoreboard_if.data.rd
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scoreboard_if.data.rd,
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src_data_n[0],
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src_data_n[1],
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src_data_n[2]
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}),
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.ready_in (stg_ready_in),
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.valid_out (operands_if.valid),
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@ -224,44 +169,50 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
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operands_if.data.ex_type,
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operands_if.data.op_type,
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operands_if.data.op_args,
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operands_if.data.rd
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operands_if.data.rd,
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operands_if.data.rs1_data,
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operands_if.data.rs2_data,
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operands_if.data.rs3_data
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}),
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.ready_out (operands_if.ready)
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);
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assign operands_if.data.rs1_data = rs1_data;
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assign operands_if.data.rs2_data = rs2_data;
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assign operands_if.data.rs3_data = rs3_data;
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// GPR banks
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reg [RAM_ADDRW-1:0] gpr_rd_addr;
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wire [RAM_ADDRW-1:0] gpr_wr_addr;
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if (ISSUE_WIS != 0) begin
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assign gpr_wr_addr = {writeback_if.data.wis, writeback_if.data.rd};
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always @(posedge clk) begin
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gpr_rd_addr <= {gpr_rd_wis_n, gpr_rd_rid_n};
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end
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end else begin
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assign gpr_wr_addr = writeback_if.data.rd;
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end
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`ifdef GPR_RESET
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reg wr_enabled = 0;
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always @(posedge clk) begin
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gpr_rd_addr <= gpr_rd_rid_n;
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if (reset) begin
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wr_enabled <= 1;
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end
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end
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end
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`else
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wire wr_enabled = 1;
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`endif
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`ifdef GPR_RESET
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reg wr_enabled = 0;
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always @(posedge clk) begin
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if (reset) begin
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wr_enabled <= 1;
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for (genvar b = 0; b < NUM_BANKS; ++b) begin
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wire gpr_wr_enabled;
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if (BANK_SEL_BITS != 0) begin
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assign gpr_wr_enabled = wr_enabled && writeback_if.valid
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&& (gpr_wr_addr[BANK_SEL_BITS-1:0] == BANK_SEL_BITS'(b));
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end else begin
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assign gpr_wr_enabled = wr_enabled && writeback_if.valid;
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end
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wire [BYTEENW-1:0] wren;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign wren[i*XLEN_SIZE+:XLEN_SIZE] = {XLEN_SIZE{writeback_if.data.tmask[i]}};
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end
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end
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`endif
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for (genvar j = 0; j < `NUM_THREADS; ++j) begin
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VX_dp_ram #(
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.DATAW (`XLEN),
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.SIZE (`NUM_REGS * PER_ISSUE_WARPS),
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.DATAW (`XLEN * `NUM_THREADS),
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.SIZE (PER_BANK_REGS * PER_ISSUE_WARPS),
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.WRENW (BYTEENW),
|
||||
`ifdef GPR_RESET
|
||||
.INIT_ENABLE (1),
|
||||
.INIT_VALUE (0),
|
||||
|
|
@ -270,16 +221,12 @@ module VX_gpr_slice import VX_gpu_pkg::*; #(
|
|||
) gpr_ram (
|
||||
.clk (clk),
|
||||
.read (1'b1),
|
||||
`UNUSED_PIN (wren),
|
||||
`ifdef GPR_RESET
|
||||
.write (wr_enabled && writeback_if.valid && writeback_if.data.tmask[j]),
|
||||
`else
|
||||
.write (writeback_if.valid && writeback_if.data.tmask[j]),
|
||||
`endif
|
||||
.waddr (gpr_wr_addr),
|
||||
.wdata (writeback_if.data.data[j]),
|
||||
.raddr (gpr_rd_addr),
|
||||
.rdata (gpr_rd_data[j])
|
||||
.wren (wren),
|
||||
.write (gpr_wr_enabled),
|
||||
.waddr (gpr_wr_addr[BANK_SEL_BITS +: PER_BANK_ADDRW]),
|
||||
.wdata (writeback_if.data.data),
|
||||
.raddr (gpr_rd_addr[b]),
|
||||
.rdata (gpr_rd_data[b])
|
||||
);
|
||||
end
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue