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https://github.com/vortexgpgpu/vortex.git
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minor updates
This commit is contained in:
Blaise Tine
parent
e7eecf8255
commit
5879b2ded1
15 changed files with 65 additions and 53 deletions
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@ -139,10 +139,13 @@ module VX_afu_control #(
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assign s_axi_wready = (wstate == WSTATE_DATA);
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assign s_axi_bresp = 2'b00; // OKAY
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assign s_axi_bvalid = (wstate == WSTATE_RESP);
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assign wmask = {{8{s_axi_wstrb[3]}}, {8{s_axi_wstrb[2]}}, {8{s_axi_wstrb[1]}}, {8{s_axi_wstrb[0]}}};
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assign aw_hs = s_axi_awvalid && s_axi_awready;
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assign wd_hs = s_axi_wvalid && s_axi_wready;
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for (genvar i = 0; i < 4; ++i) begin
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assign wmask[i] = {8{s_axi_wstrb[i]}};
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end
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// wstate
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always @(posedge clk) begin
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if (reset)
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@ -41,9 +41,9 @@ module VX_imadd #(
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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VX_multiplier #(
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.WIDTHA (DATA_WIDTH),
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.WIDTHB (DATA_WIDTH),
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.WIDTHP (PROD_WIDTH),
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.A_WIDTH (DATA_WIDTH),
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.B_WIDTH (DATA_WIDTH),
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.R_WIDTH (PROD_WIDTH),
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.SIGNED (SIGNED),
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.LATENCY (`LATENCY_IMUL)
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) multiplier (
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@ -138,13 +138,14 @@ module VX_lsu_unit #(
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// data formatting
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [REQ_ASHIFT-1:0] req_align_X1 = {req_align[i][1], 1'b1};
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always @(*) begin
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mem_req_byteen[i] = {4{lsu_req_if.wb}};
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case (`INST_LSU_WSIZE(lsu_req_if.op_type))
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0: mem_req_byteen[i][req_align[i]] = 1;
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1: begin
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mem_req_byteen[i][req_align[i]] = 1;
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mem_req_byteen[i][{req_align[i][1], 1'b1}] = 1;
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mem_req_byteen[i][req_align_X1] = 1;
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end
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default : mem_req_byteen[i] = {4{1'b1}};
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endcase
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@ -91,9 +91,9 @@ module VX_muldiv (
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`IGNORE_UNUSED_END
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VX_multiplier #(
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.WIDTHA (33),
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.WIDTHB (33),
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.WIDTHP (66),
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.A_WIDTH (33),
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.B_WIDTH (33),
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.R_WIDTH (66),
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.SIGNED (1),
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.LATENCY (`LATENCY_IMUL)
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) multiplier (
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@ -10,8 +10,8 @@ module VX_divider #(
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parameter D_SIGNED = 0,
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parameter LATENCY = 0
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) (
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input wire clk,
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input wire enable,
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input wire clk,
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input wire enable,
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input wire [N_WIDTH-1:0] numer,
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input wire [D_WIDTH-1:0] denom,
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output wire [Q_WIDTH-1:0] quotient,
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@ -2,21 +2,21 @@
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`TRACING_OFF
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module VX_multiplier #(
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parameter WIDTHA = 1,
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parameter WIDTHB = 1,
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parameter WIDTHP = 1,
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parameter A_WIDTH = 1,
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parameter B_WIDTH = 1,
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parameter R_WIDTH = 1,
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parameter SIGNED = 0,
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parameter LATENCY = 0
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) (
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input wire clk,
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input wire enable,
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input wire [WIDTHA-1:0] dataa,
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input wire [WIDTHB-1:0] datab,
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output wire [WIDTHP-1:0] result
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input wire [A_WIDTH-1:0] dataa,
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input wire [B_WIDTH-1:0] datab,
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output wire [R_WIDTH-1:0] result
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);
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`STATIC_ASSERT ((LATENCY <= 3), ("invalid parameter"))
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wire [WIDTHP-1:0] result_unqual;
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wire [R_WIDTH-1:0] result_unqual;
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if (SIGNED != 0) begin
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assign result_unqual = $signed(dataa) * $signed(datab);
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@ -27,7 +27,7 @@ module VX_multiplier #(
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if (LATENCY == 0) begin
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assign result = result_unqual;
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end else begin
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reg [WIDTHP-1:0] result_pipe [LATENCY-1:0];
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reg [R_WIDTH-1:0] result_pipe [LATENCY-1:0];
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always @(posedge clk) begin
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if (enable) begin
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result_pipe[0] <= result_unqual;
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@ -18,7 +18,8 @@ module VX_raster_csr #(
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);
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`UNUSED_VAR (reset)
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localparam NW_WIDTH = `UP(`NW_BITS);
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localparam NW_WIDTH = `UP(`NW_BITS);
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localparam NUM_CSRS_BITS = `CLOG2(`CSR_RASTER_COUNT);
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raster_csrs_t [`NUM_THREADS-1:0] wdata;
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raster_csrs_t [`NUM_THREADS-1:0] rdata;
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@ -43,12 +44,12 @@ module VX_raster_csr #(
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end
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// CSRs write
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assign wren = {`NUM_THREADS{write_enable}} & write_tmask;
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assign waddr = write_wid;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign wdata[i].pos_mask = {write_data[i].pos_y, write_data[i].pos_x, write_data[i].mask};
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assign wren[i] = write_enable && write_tmask[i];
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assign wdata[i].pos_mask = {write_data[i].pos_y, write_data[i].pos_x, write_data[i].mask};
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assign wdata[i].bcoords = write_data[i].bcoords;
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end
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@ -56,9 +57,11 @@ module VX_raster_csr #(
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assign raddr = raster_csr_if.read_wid;
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wire [NUM_CSRS_BITS-1:0] csr_addr = raster_csr_if.read_addr[NUM_CSRS_BITS-1:0];
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [`CSR_RASTER_COUNT-1:0][31:0] read_data = rdata[i];
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assign raster_csr_if.read_data[i] = read_data[raster_csr_if.read_addr[`CLOG2(`CSR_RASTER_COUNT)-1:0]];
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wire [`CSR_RASTER_COUNT-1:0][31:0] indexable_rdata = rdata[i];
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assign raster_csr_if.read_data[i] = indexable_rdata[csr_addr];
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end
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`UNUSED_VAR (write_uuid)
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@ -2,7 +2,7 @@
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`include "VX_raster_define.vh"
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module VX_raster_edge_function #(
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module VX_raster_edge #(
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parameter LATENCY = 3
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) (
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input wire clk,
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@ -29,9 +29,9 @@ module VX_raster_edge_function #(
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for (genvar i = 0; i < 3; ++i) begin
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VX_multiplier #(
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.WIDTHA (`RASTER_DATA_BITS),
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.WIDTHB (`RASTER_DIM_BITS),
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.WIDTHP (PROD_WIDTH),
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.A_WIDTH (`RASTER_DATA_BITS),
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.B_WIDTH (`RASTER_DIM_BITS),
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.R_WIDTH (PROD_WIDTH),
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.SIGNED (1),
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.LATENCY (`LATENCY_IMUL)
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) x_multiplier (
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@ -43,9 +43,9 @@ module VX_raster_edge_function #(
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);
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VX_multiplier #(
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.WIDTHA (`RASTER_DATA_BITS),
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.WIDTHB (`RASTER_DIM_BITS),
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.WIDTHP (PROD_WIDTH),
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.A_WIDTH (`RASTER_DATA_BITS),
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.B_WIDTH (`RASTER_DIM_BITS),
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.R_WIDTH (PROD_WIDTH),
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.SIGNED (1),
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.LATENCY (`LATENCY_IMUL)
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) y_multiplier (
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@ -7,8 +7,8 @@ module VX_raster_extents #(
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output wire [2:0][`RASTER_DATA_BITS-1:0] extents
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);
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for (genvar i = 0; i < 3; ++i) begin
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assign extents[i] = (~edges[i][0][`RASTER_DATA_BITS-1] ? (edges[i][0] << TILE_LOGSIZE) : `RASTER_DATA_BITS'(0))
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+ (~edges[i][1][`RASTER_DATA_BITS-1] ? (edges[i][1] << TILE_LOGSIZE) : `RASTER_DATA_BITS'(0));
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assign extents[i] = ({`RASTER_DATA_BITS{~edges[i][0][`RASTER_DATA_BITS-1]}} & (edges[i][0] << TILE_LOGSIZE))
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+ ({`RASTER_DATA_BITS{~edges[i][1][`RASTER_DATA_BITS-1]}} & (edges[i][1] << TILE_LOGSIZE));
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end
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endmodule
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@ -296,9 +296,9 @@ module VX_raster_mem #(
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wire [`RASTER_DATA_BITS-1:0] prim_mem_offset;
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VX_multiplier #(
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.WIDTHA (`RASTER_DATA_BITS),
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.WIDTHB (`RASTER_STRIDE_BITS),
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.WIDTHP (`RASTER_DATA_BITS),
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.A_WIDTH (`RASTER_DATA_BITS),
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.B_WIDTH (`RASTER_STRIDE_BITS),
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.R_WIDTH (`RASTER_DATA_BITS),
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.SIGNED (0),
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.LATENCY (`LATENCY_IMUL)
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) multiplier (
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@ -110,9 +110,9 @@ module VX_raster_unit #(
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.extents (mem_extents)
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);
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VX_raster_edge_function #(
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VX_raster_edge #(
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.LATENCY (EDGE_FUNC_LATENCY)
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) raster_edge_function (
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) raster_edge (
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.clk (clk),
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.reset (reset),
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.enable (~edge_func_stall),
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@ -2,9 +2,9 @@
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`define MULT8(clk, en, dst, src1, src2) \
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VX_multiplier #( \
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.WIDTHA (8), \
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.WIDTHB (8), \
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.WIDTHP (16), \
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.A_WIDTH (8), \
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.B_WIDTH (8), \
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.R_WIDTH (16), \
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.LATENCY (`LATENCY_IMUL) \
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) __``dst ( \
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.clk (clk), \
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@ -75,9 +75,9 @@ module VX_rop_mem #(
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wire [31:0] m_y_pitch, baddr_s;
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VX_multiplier #(
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.WIDTHA (`ROP_DIM_BITS),
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.WIDTHB (`ROP_PITCH_BITS),
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.WIDTHP (32),
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.A_WIDTH (`ROP_DIM_BITS),
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.B_WIDTH (`ROP_PITCH_BITS),
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.R_WIDTH (32),
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.LATENCY (`LATENCY_IMUL)
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) multiplier (
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.clk (clk),
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@ -114,9 +114,9 @@ module VX_rop_mem #(
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wire [31:0] m_y_pitch, baddr_s;
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VX_multiplier #(
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.WIDTHA (`ROP_DIM_BITS),
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.WIDTHB (`ROP_PITCH_BITS),
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.WIDTHP (32),
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.A_WIDTH (`ROP_DIM_BITS),
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.B_WIDTH (`ROP_PITCH_BITS),
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.R_WIDTH (32),
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.LATENCY (`LATENCY_IMUL)
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) multiplier (
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.clk (clk),
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@ -45,7 +45,10 @@ RTL_INCLUDE = -I$(RTL_DIR) -I$(RTL_DIR)/libs -I$(RTL_DIR)/interfaces -I$(RTL_DIR
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RTL_INCLUDE += $(FPU_INCLUDE) $(TEX_INCLUDE) $(RASTER_INCLUDE) $(ROP_INCLUDE)
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#CONFIGS += -DEXT_GFX_ENABLE
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CONFIGS += -DNUM_WARPS=2 -DNUM_THREADS=2 -DEXT_F_DISABLE
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#CONFIGS += -DNUM_WARPS=2 -DNUM_THREADS=2 -DEXT_F_DISABLE -DL1_DISABLE
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#CONFIGS += -DNUM_WARPS=2 -DNUM_THREADS=2 -DEXT_F_DISABLE
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#CONFIGS += -DNUM_WARPS=2 -DNUM_THREADS=2
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#CONFIGS += -DNUM_CORES=4
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CONFIGS += -DSYNTHESIS -DVIVADO
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@ -69,7 +72,7 @@ JOBS := $(shell expr $(NCPUS) - 1)
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VPP_FLAGS += --link --target $(TARGET) --platform $(PLATFORM) --save-temps --no_ip_cache
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VPP_FLAGS += --vivado.synth.jobs $(JOBS) --vivado.impl.jobs $(JOBS)
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VPP_FLAGS += --connectivity.sp vortex_afu_1.m_axi_mem:HBM[0:15]
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VPP_FLAGS += --report estimate
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VPP_FLAGS += --report 2
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VPP_FLAGS += --config ../vitis.ini
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# Enable perf counters
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@ -121,8 +124,10 @@ emconfig: $(BIN_DIR)/emconfig.json
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$(BIN_DIR)/emconfig.json:
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mkdir -p $(BIN_DIR); cd $(BUILD_DIR); emconfigutil --platform $(PLATFORM) --od ../$(BIN_DIR)
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chipscope:
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hw_server:
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debug_hw --xvc_pcie /dev/xfpga/xvc_pub.u2305.0 --hw_server &
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chipscope:
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debug_hw --vivado --host localhost --ltx_file $(BUILD_DIR)/_x/link/vivado/vpl/prj/prj.runs/impl_1/debug_nets.ltx &
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clean:
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@ -114,10 +114,10 @@ static int get_bank_info(uint64_t dev_addr, uint32_t* pIdx, uint32_t* pOff) {
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return 0;
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}
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static void wait_for_enter(const std::string &msg) {
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/*static void wait_for_enter(const std::string &msg) {
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std::cout << msg << std::endl;
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std::cin.ignore(std::numeric_limits<std::streamsize>::max(), '\n');
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}
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}*/
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///////////////////////////////////////////////////////////////////////////////
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@ -621,7 +621,7 @@ extern int vx_start(vx_device_h hdevice) {
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auto device = (vx_device*)hdevice;
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wait_for_enter("\nPress ENTER to continue after setting up ILA trigger...");
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//wait_for_enter("\nPress ENTER to continue after setting up ILA trigger...");
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#ifdef CPP_API
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