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RTL code refactoring

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This commit is contained in:
Blaise Tine 2020-04-20 06:59:13 -04:00
parent 07135263f5
commit 58850a2fe8
6 changed files with 22 additions and 23 deletions
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18
hw/rtl/VX_dmem_controller.v
View file

@ -43,7 +43,7 @@ module VX_dmem_controller (
assign dcache_req_dcache_if.core_req_warp_num = dcache_req_if.core_req_warp_num;
assign dcache_req_dcache_if.core_req_pc = dcache_req_if.core_req_pc;
assign dcache_req_dcache_if.core_no_wb_slot = dcache_req_if.core_no_wb_slot;
assign dcache_rsp_dcache_if.core_no_wb_slot = dcache_rsp_if.core_no_wb_slot;
// Shared Memory Request
assign dcache_req_smem_if.core_req_valid = dcache_req_if.core_req_valid & {`NUM_THREADS{to_shm}};
@ -56,7 +56,7 @@ module VX_dmem_controller (
assign dcache_req_smem_if.core_req_warp_num = dcache_req_if.core_req_warp_num;
assign dcache_req_smem_if.core_req_pc = dcache_req_if.core_req_pc;
assign dcache_req_smem_if.core_no_wb_slot = dcache_req_if.core_no_wb_slot || dcache_wants_wb;
assign dcache_rsp_smem_if.core_no_wb_slot = dcache_rsp_if.core_no_wb_slot || dcache_wants_wb;
// Dcache Response
assign dcache_rsp_if.core_wb_valid = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_valid : dcache_rsp_smem_if.core_wb_valid;
@ -66,7 +66,7 @@ module VX_dmem_controller (
assign dcache_rsp_if.core_wb_readdata = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_readdata : dcache_rsp_smem_if.core_wb_readdata;
assign dcache_rsp_if.core_wb_warp_num = dcache_wants_wb ? dcache_rsp_dcache_if.core_wb_warp_num : dcache_rsp_smem_if.core_wb_warp_num;
assign dcache_rsp_if.core_req_ready = to_shm ? dcache_rsp_smem_if.core_req_ready : dcache_rsp_dcache_if.core_req_ready;
assign dcache_req_if.core_req_ready = to_shm ? dcache_req_smem_if.core_req_ready : dcache_req_dcache_if.core_req_ready;
VX_gpu_dcache_dram_req_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_req_if();
VX_gpu_dcache_dram_rsp_if #(.BANK_LINE_WORDS(`DBANK_LINE_WORDS)) gpu_smem_dram_res_if();
@ -108,10 +108,10 @@ module VX_dmem_controller (
.core_req_pc (dcache_req_smem_if.core_req_pc),
// Can submit core Req
.core_req_ready (dcache_rsp_smem_if.core_req_ready),
.core_req_ready (dcache_req_smem_if.core_req_ready),
// Core Cache Can't WB
.core_no_wb_slot (dcache_req_smem_if.core_no_wb_slot),
.core_no_wb_slot (dcache_rsp_smem_if.core_no_wb_slot),
// Cache CWB
.core_wb_valid (dcache_rsp_smem_if.core_wb_valid),
@ -191,10 +191,10 @@ module VX_dmem_controller (
.core_req_pc (dcache_req_dcache_if.core_req_pc),
// Can submit core Req
.core_req_ready (dcache_rsp_dcache_if.core_req_ready),
.core_req_ready (dcache_req_dcache_if.core_req_ready),
// Core Cache Can't WB
.core_no_wb_slot (dcache_req_dcache_if.core_no_wb_slot),
.core_no_wb_slot (dcache_rsp_dcache_if.core_no_wb_slot),
// Cache CWB
.core_wb_valid (dcache_rsp_dcache_if.core_wb_valid),
@ -272,10 +272,10 @@ module VX_dmem_controller (
.core_req_pc (icache_req_if.core_req_pc),
// Can submit core Req
.core_req_ready (icache_rsp_if.core_req_ready),
.core_req_ready (icache_req_if.core_req_ready),
// Core Cache Can't WB
.core_no_wb_slot (icache_req_if.core_no_wb_slot),
.core_no_wb_slot (icache_rsp_if.core_no_wb_slot),
// Cache CWB
.core_wb_valid (icache_rsp_if.core_wb_valid),

4
hw/rtl/VX_icache_stage.v
View file

@ -39,10 +39,10 @@ module VX_icache_stage (
assign icache_stage_valids = fe_inst_meta_id.valid & {`NUM_THREADS{!icache_stage_delay}};
// Cache can't accept request
assign icache_stage_delay = ~icache_rsp_if.core_req_ready;
assign icache_stage_delay = ~icache_req_if.core_req_ready;
// Core can't accept response
assign icache_req_if.core_no_wb_slot = total_freeze;
assign icache_rsp_if.core_no_wb_slot = total_freeze;
integer curr_w;
always @(posedge clk) begin

4
hw/rtl/VX_lsu.v
View file

@ -56,10 +56,10 @@ module VX_lsu (
assign dcache_req_if.core_req_pc = use_pc;
// Core can't accept response
assign dcache_req_if.core_no_wb_slot = no_slot_mem;
assign dcache_rsp_if.core_no_wb_slot = no_slot_mem;
// Cache can't accept request
assign out_delay = ~dcache_rsp_if.core_req_ready;
assign out_delay = ~dcache_req_if.core_req_ready;
// Core Response
assign mem_wb_if.rd = dcache_rsp_if.core_wb_req_rd;

7
hw/rtl/Vortex.v
View file

@ -94,12 +94,13 @@ module Vortex #(
assign dcache_req_qual_if.core_req_mem_write = dcache_req_if.core_req_mem_write;
assign dcache_req_qual_if.core_req_addr = dcache_req_if.core_req_addr;
assign dcache_req_qual_if.core_req_writedata = dcache_req_if.core_req_writedata;
assign dcache_req_if.core_req_ready = dcache_req_qual_if.core_req_ready;
assign dcache_req_qual_if.core_req_rd = dcache_req_if.core_req_rd;
assign dcache_req_qual_if.core_req_wb = dcache_req_if.core_req_wb;
assign dcache_req_qual_if.core_req_warp_num = dcache_req_if.core_req_warp_num;
assign dcache_req_qual_if.core_req_pc = dcache_req_if.core_req_pc;
assign dcache_req_qual_if.core_no_wb_slot = dcache_req_if.core_no_wb_slot;
assign dcache_req_qual_if.core_req_pc = dcache_req_if.core_req_pc;
VX_gpu_dcache_rsp_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_rsp_if();
VX_gpu_dcache_req_if #(.NUM_REQUESTS(`INUM_REQUESTS)) icache_req_if();

7
hw/rtl/interfaces/VX_gpu_dcache_req_if.v
View file

@ -13,14 +13,13 @@ interface VX_gpu_dcache_req_if #(
wire [NUM_REQUESTS-1:0][2:0] core_req_mem_write;
wire [NUM_REQUESTS-1:0][31:0] core_req_addr;
wire [NUM_REQUESTS-1:0][31:0] core_req_writedata;
wire core_req_ready;
// Core request Meta data
wire [4:0] core_req_rd;
wire [NUM_REQUESTS-1:0][1:0] core_req_wb;
wire [`NW_BITS-1:0] core_req_warp_num;
wire [31:0] core_req_pc;
wire core_no_wb_slot;
wire [31:0] core_req_pc;
endinterface

5
hw/rtl/interfaces/VX_gpu_dcache_rsp_if.v
View file

@ -15,11 +15,10 @@ interface VX_gpu_dcache_rsp_if #(
`IGNORE_WARNINGS_END
wire [NUM_REQUESTS-1:0][31:0] core_wb_pc;
wire [NUM_REQUESTS-1:0][31:0] core_wb_readdata;
wire core_no_wb_slot;
// Core response meta data
wire [`NW_BITS-1:0] core_wb_warp_num;
wire core_req_ready;
wire [`NW_BITS-1:0] core_wb_warp_num;
endinterface