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minor update

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This commit is contained in:
Blaise Tine 2024-02-28 16:36:26 -08:00
parent 51ae0b71f3
commit 59497e52df
2 changed files with 20 additions and 24 deletions
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17
hw/rtl/core/VX_decode.sv
View file

@ -538,12 +538,27 @@ module VX_decode #(
`endif
`ifdef DBG_TRACE_CORE_PIPELINE
`ifdef FLEN_64
wire fdst_d = decode_if.data.imm[0];
`else
wire fdst_d = 0;
`endif
`ifdef XLEN_64
wire fcvt_l = decode_if.data.imm[1];
`else
wire fcvt_l = 0;
`endif
`ifdef EXT_F_ENABLE
wire rd_float = 1'(decode_if.data.rd >> 5) || 1'(decode_if.data.rs2 >> 5);
`else
wire rd_float = 0;
`endif
always @(posedge clk) begin
if (decode_if.valid && decode_if.ready) begin
`TRACE(1, ("%d: core%0d-decode: wid=%0d, PC=0x%0h, instr=0x%0h, ex=", $time, CORE_ID, decode_if.data.wid, decode_if.data.PC, instr));
trace_ex_type(1, decode_if.data.ex_type);
`TRACE(1, (", op="));
trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.rd, decode_if.data.rs2, decode_if.data.use_imm, decode_if.data.imm);
trace_ex_op(1, decode_if.data.ex_type, decode_if.data.op_type, decode_if.data.op_mod, decode_if.data.use_imm, fdst_d, fcvt_l, rd_float);
`TRACE(1, (", mod=%0d, tmask=%b, wb=%b, rd=%0d, rs1=%0d, rs2=%0d, rs3=%0d, imm=0x%0h, opds=%b%b%b%b, use_pc=%b, use_imm=%b (#%0d)\n",
decode_if.data.op_mod, decode_if.data.tmask, decode_if.data.wb, decode_if.data.rd, decode_if.data.rs1, decode_if.data.rs2, decode_if.data.rs3, decode_if.data.imm, use_rd, use_rs1, use_rs2, use_rs3, decode_if.data.use_PC, decode_if.data.use_imm, decode_if.data.uuid));
end

27
hw/rtl/core/VX_trace.vh
View file

@ -29,31 +29,12 @@ endtask
task trace_ex_op(input int level,
input [`EX_BITS-1:0] ex_type,
input [`INST_OP_BITS-1:0] op_type,
input [`INST_MOD_BITS-1:0] op_mod,
`UNUSED_ARG(input [`NR_BITS-1:0] rd),
`UNUSED_ARG(input [`NR_BITS-1:0] rs2),
input [`INST_MOD_BITS-1:0] op_mod,
input use_imm,
`UNUSED_ARG(input [`XLEN-1:0] imm)
input fdst_d,
input fcvt_l,
input rd_float
);
`ifdef FLEN_64
logic fdst_d = imm[0];
`else
logic fdst_d = 0;
`endif
`ifdef XLEN_64
logic fcvt_l = imm[1];
`else
logic fcvt_l = 0;
`endif
`ifdef EXT_F_ENABLE
logic rd_float = 1'(rd >> 5) || 1'(rs2 >> 5);
`else
logic rd_float = 0;
`endif
case (ex_type)
`EX_ALU: begin
if (`INST_ALU_IS_BR(op_mod)) begin