Add modified RTL files for parameterized builds with VX_define_synth.v

.gitignore

@@ -4,3 +4,5 @@
 ./rtl/modelsim/*.vcd
 *.vcd
 .*
+*.pyc
+__pycache__

rtl/Makefile

@@ -9,7 +9,7 @@ MULTI_CORE=Vortex_SOC.v
 EXE=--exe ./simulate/test_bench.cpp
 MULTI_EXE=--exe ./simulate/multi_test_bench.cpp
 
-COMP=--compiler gcc
+COMP=--compiler gcc --language 1800-2009
 
 WNO=-Wno-UNDRIVEN --Wno-PINMISSING -Wno-STMTDLY -Wno-WIDTH -Wno-UNSIGNED -Wno-UNOPTFLAT -Wno-LITENDIAN
 # WNO=

rtl/VX_define.v

@@ -125,9 +125,6 @@
    -199
 
 
-
-`define NUMBER_CORES_PER_CLUSTER 2
-`define NUMBER_CLUSTERS 1
 `define NUMBER_CORES (`NUMBER_CORES_PER_CLUSTER*`NUMBER_CLUSTERS)
 
 // `define SINGLE_CORE_BENCH 0
@@ -135,8 +132,6 @@
 // ========================================= Dcache Configurable Knobs =========================================
 
 // General Cache Knobs
-   // Size of cache in bytes
-   `define DCACHE_SIZE_BYTES 1024
    // Size of line inside a bank in bytes
    `define DBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
    // Number of banks {1, 2, 4, 8,...}
@@ -156,9 +151,9 @@
 // Queues feeding into banks Knobs {1, 2, 4, 8, ...}
 
    // Core Request Queue Size
-   `define DREQQ_SIZE `NT*`NW
+   `define DREQQ_SIZE `NW
    // Miss Reserv Queue Knob
-   `define DMRVQ_SIZE `DREQQ_SIZE
+   `define DMRVQ_SIZE (`NW*`NT)
    // Dram Fill Rsp Queue Size
    `define DDFPQ_SIZE 2
    // Snoop Req Queue
@@ -188,8 +183,6 @@
 // ========================================= Icache Configurable Knobs =========================================
 
 // General Cache Knobs
-   // Size of cache in bytes
-   `define ICACHE_SIZE_BYTES 1024
    // Size of line inside a bank in bytes
    `define IBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
    // Number of banks {1, 2, 4, 8,...}
@@ -294,8 +287,6 @@
 // ========================================= L2cache Configurable Knobs =========================================
 
 // General Cache Knobs
-   // Size of cache in bytes
-   `define LLCACHE_SIZE_BYTES 1024
    // Size of line inside a bank in bytes
    `define LLBANK_LINE_SIZE_BYTES `GLOBAL_BLOCK_SIZE_BYTES
    // Number of banks {1, 2, 4, 8,...}
@@ -315,9 +306,9 @@
 // Queues feeding into banks Knobs {1, 2, 4, 8, ...}
 
    // Core Request Queue Size
-   `define LLREQQ_SIZE (`NT*`NW*`NUMBER_CORES_PER_CLUSTER)
+   `define LLREQQ_SIZE (2*`NUMBER_CORES_PER_CLUSTER)
    // Miss Reserv Queue Knob
-   `define LLMRVQ_SIZE `LLREQQ_SIZE
+   `define LLMRVQ_SIZE (`DNUMBER_BANKS*`NUMBER_CORES_PER_CLUSTER)
    // Dram Fill Rsp Queue Size
    `define LLDFPQ_SIZE 2
    // Snoop Req Queue
@@ -345,7 +336,6 @@
 
 
 // ========================================= L3cache Configurable Knobs =========================================
-// `define L3C 1
 // General Cache Knobs
    // Size of cache in bytes
    `define L3CACHE_SIZE_BYTES 1024

rtl/VX_define_synth.v

@@ -1,7 +1,21 @@
+
 `ifndef VX_DEFINE_SYNTH
 `define VX_DEFINE_SYNTH
 
-`define NT 2
+`define NT 4
 `define NW 8
+`define NUMBER_CORES_PER_CLUSTER 2
+`define NUMBER_CLUSTERS 1
+`define DCACHE_SIZE_BYTES 4096
+`define ICACHE_SIZE_BYTES 1024
+
+// L2 Cache size
+`define LLCACHE_SIZE_BYTES 8192
+
+
+// `define QUEUE_FORCE_MLAB 1
+
+// Use l3 cache (required for cluster behavior)
+// `define L3C 1
 
 `endif

rtl/VX_generic_queue_ll.v

@@ -1,3 +1,4 @@
+`include "VX_define_synth.v"
 
 module VX_generic_queue_ll
 	#(
@@ -24,7 +25,12 @@ module VX_generic_queue_ll
         assign full     = 0;
     end else begin
 
-        (* syn_ramstyle = "mlab" *) reg[DATAW-1:0]          data[SIZE-1:0];
+        `ifdef QUEUE_FORCE_MLAB
+        (* syn_ramstyle = "mlab" *) reg[DATAW-1:0] data[SIZE-1:0];
+        `else
+        reg[DATAW-1:0] data[SIZE-1:0];
+        `endif
+
         reg[DATAW-1:0]          curr_r, head_r;
         reg[$clog2(SIZE+1)-1:0] size_r;
         reg[$clog2(SIZE)-1:0]   wr_ctr_r;