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FIX

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felsabbagh3 2020-04-05 00:17:02 -07:00
parent 91a926e3b6
commit 5b633bca61
1 changed files with 1 additions and 1 deletions
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2
rtl/VX_alu.v
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@ -177,7 +177,7 @@ module VX_alu(
assign upper_immed = {in_upper_immed, {12{1'b0}}};
always @(in_alu_op or ALU_in1 or ALU_in2) begin
always @(*) begin
case(in_alu_op)
`ADD: out_alu_result = $signed(ALU_in1) + $signed(ALU_in2);
`SUB: out_alu_result = $signed(ALU_in1) - $signed(ALU_in2);