Yosys synthesis fixes

hw/rtl/core/VX_lsu_slice.sv

@@ -87,7 +87,7 @@ module VX_lsu_slice import VX_gpu_pkg::*, VX_trace_pkg::*; #(
     wire [NUM_LANES-1:0]            mem_req_mask;
     wire                            mem_req_rw;
     wire [NUM_LANES-1:0][LSU_ADDR_WIDTH-1:0] mem_req_addr;
-    reg  [NUM_LANES-1:0][LSU_WORD_SIZE-1:0] mem_req_byteen;
+    wire [NUM_LANES-1:0][LSU_WORD_SIZE-1:0] mem_req_byteen;
     reg  [NUM_LANES-1:0][LSU_WORD_SIZE*8-1:0] mem_req_data;
     wire [TAG_WIDTH-1:0]            mem_req_tag;
     wire                            mem_req_ready;
@@ -158,27 +158,30 @@ module VX_lsu_slice import VX_gpu_pkg::*, VX_trace_pkg::*; #(
 
     // byte enable formatting
     for (genvar i = 0; i < NUM_LANES; ++i) begin
+        reg [LSU_WORD_SIZE-1:0] mem_req_byteen_r;
         always @(*) begin
-            mem_req_byteen[i] = '0;
+            mem_req_byteen_r = '0;
             case (`INST_LSU_WSIZE(execute_if.data.op_type))
                 0: begin // 8-bit
-                    mem_req_byteen[i][req_align[i]] = 1'b1;
+                    mem_req_byteen_r[req_align[i]] = 1'b1;
                 end
                 1: begin // 16 bit
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:1], 1'b0}] = 1'b1;
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:1], 1'b1}] = 1'b1;
+                    mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:1], 1'b0}] = 1'b1;
+                    mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:1], 1'b1}] = 1'b1;
                 end
             `ifdef XLEN_64
                 2: begin // 32 bit
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b00}] = 1'b1;
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b01}] = 1'b1;
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b10}] = 1'b1;
-                    mem_req_byteen[i][{req_align[i][REQ_ASHIFT-1:2], 2'b11}] = 1'b1;
+                    mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:2], 2'b00}] = 1'b1;
+                    mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:2], 2'b01}] = 1'b1;
+                    mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:2], 2'b10}] = 1'b1;
+                    mem_req_byteen_r[{req_align[i][REQ_ASHIFT-1:2], 2'b11}] = 1'b1;
                 end
             `endif
-                default : mem_req_byteen[i] = {LSU_WORD_SIZE{1'b1}};
+                // 3: 64 bit
+                default : mem_req_byteen_r = {LSU_WORD_SIZE{1'b1}};
             endcase
         end
+        assign mem_req_byteen[i] = mem_req_byteen_r;
     end
 
     // memory misalignment not supported!

hw/rtl/libs/VX_rr_arbiter.sv

@@ -384,12 +384,18 @@ module VX_rr_arbiter #(
 
         wire [NUM_REQS-1:0] req_masked = requests & pointer_reg;
 
-        assign mask_higher_pri_regs[NUM_REQS-1:1] = mask_higher_pri_regs[NUM_REQS-2:0] | req_masked[NUM_REQS-2:0];
         assign mask_higher_pri_regs[0] = 1'b0;
+        for (genvar i = 1; i < NUM_REQS; ++i) begin
+            assign mask_higher_pri_regs[i] = mask_higher_pri_regs[i-1] | req_masked[i-1];
+        end
+
         assign grant_masked[NUM_REQS-1:0] = req_masked[NUM_REQS-1:0] & ~mask_higher_pri_regs[NUM_REQS-1:0];
 
-        assign unmask_higher_pri_regs[NUM_REQS-1:1] = unmask_higher_pri_regs[NUM_REQS-2:0] | requests[NUM_REQS-2:0];
         assign unmask_higher_pri_regs[0] = 1'b0;
+        for (genvar i = 1; i < NUM_REQS; ++i) begin
+            assign unmask_higher_pri_regs[i] = unmask_higher_pri_regs[i-1] | requests[i-1];
+        end
+
         assign grant_unmasked[NUM_REQS-1:0] = requests[NUM_REQS-1:0] & ~unmask_higher_pri_regs[NUM_REQS-1:0];
 
         wire no_req_masked = ~(|req_masked);

hw/syn/yosys/Makefile

@@ -89,5 +89,8 @@ build: $(BUILD_DIR)/project.v
 elaborate: $(BUILD_DIR)/project.v
 	cd $(BUILD_DIR); $(SRC_DIR)/synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v -P="elaborate"
 
+synthesis: $(BUILD_DIR)/project.v
+	cd $(BUILD_DIR); $(SRC_DIR)/synth.sh -t$(TOP_LEVEL_ENTITY) -sproject.v -P="synthesis"
+
 clean:
 	$(RMDIR) $(BUILD_DIR)

hw/syn/yosys/synth.sh

@@ -1,12 +1,12 @@
 #!/bin/bash
 
 # Copyright © 2019-2023
-# 
+#
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 # http://www.apache.org/licenses/LICENSE-2.0
-# 
+#
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
 # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -87,18 +87,18 @@ while getopts "s:t:I:D:P:Wh" arg; do
     W) # allow warnings
         no_warnings=0
         ;;
-    h | *) 
+    h | *)
       usage
       exit 0
       ;;
   esac
 done
 
-{    
+{
     # read design sources
-    for dir in "${dir_list[@]}" 
+    for dir in "${dir_list[@]}"
     do
-        for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f) 
+        for file in $(find $dir -maxdepth 1 -name '*.v' -o -name '*.sv' -type f)
         do
             echo "read_verilog -defer -nolatches $macro_args $inc_args -sv $file"
         done
@@ -111,11 +111,16 @@ done
     if echo "$process" | grep -q "elaborate"; then
         echo "hierarchy -top $top_level"
     fi
-    
+
+    # synthesize design
+    if echo "$process" | grep -q "synthesis"; then
+        echo "synth -top $top_level"
+    fi
+
     # convert to netlist
     if echo "$process" | grep -q "netlist"; then
         echo "proc; opt"
-    fi    
+    fi
 
     # convert to gate logic
     if echo "$process" | grep -q "techmap"; then
@@ -126,8 +131,11 @@ done
     if echo "$process" | grep -q "verilog"; then
         echo "write_verilog synth.v"
     fi
+
+    # Generate a summary report
+    echo "stat"
 } > synth.ys
 
-yosys -l yosys.log synth.ys
+yosys -l yosys.log -s synth.ys
 
 checkErrors yosys.log