mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 05:17:45 -04:00
simx 64-bit addressing fixes
This commit is contained in:
Blaise Tine
parent
39ef09be1d
commit
5bd6561514
15 changed files with 84 additions and 54 deletions
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@ -37,6 +37,7 @@ endif
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CFLAGS += -O3 -mcmodel=medany -fno-rtti -fno-exceptions -nostartfiles -fdata-sections -ffunction-sections
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CFLAGS += -I./include -I../hw
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CFLAGS += -DXLEN_$(XLEN)
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PROJECT = libvortexrt
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@ -1,15 +1,25 @@
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#include <VX_config.h>
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#include <VX_types.h>
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.type vx_serial, @function
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.global vx_serial
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vx_serial:
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addi sp, sp, -24
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#if (XLEN == 64)
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sd ra, 40(sp)
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sd s4, 32(sp)
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sd s3, 24(sp)
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sd s2, 16(sp)
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sd s1, 8(sp)
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sd s0, 0(sp)
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#else
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sw ra, 20(sp)
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sw s4, 16(sp)
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sw s3, 12(sp)
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sw s2, 8(sp)
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sw s1, 4(sp)
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sw s0, 0(sp)
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#endif
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mv s4, a0 # s4 <- callback
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mv s3, a1 # s3 <- arg
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csrr s2, CSR_NT # s2 <- NT
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@ -26,12 +36,21 @@ label_join:
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.insn r 0x0b, 3, 0, x0, x0, x0 # join
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addi s0, s0, 1 # index++
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blt s0, s2, label_loop # loop back
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#if (XLEN == 64)
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ld ra, 40(sp)
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ld s4, 32(sp)
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ld s3, 24(sp)
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ld s2, 16(sp)
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ld s1, 8(sp)
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ld s0, 0(sp)
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#else
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lw ra, 20(sp)
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lw s4, 16(sp)
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lw s3, 12(sp)
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lw s2, 8(sp)
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lw s1, 4(sp)
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lw s0, 0(sp)
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#endif
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addi sp, sp, 24
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ret
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@ -74,7 +74,14 @@ init_regs:
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.option pop
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# set stack pointer register
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#if (XLEN == 64)
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li a0, (STACK_BASE_ADDR >> 32) # load upper 32 bits stack base address
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slli a0, a0, 32 # shift left 32 bits
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li sp, (STACK_BASE_ADDR & 0xffffffff) # load lower 32 bits stack base address
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or sp, sp, a0 # combine upper and lower bits
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#else
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li sp, STACK_BASE_ADDR # load stack base address
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#endif
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csrr a0, CSR_GTID # get global thread id
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sll a1, a0, STACK_LOG2_SIZE
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sub sp, sp, a1
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@ -20,8 +20,9 @@ RamMemDevice::RamMemDevice(const char *filename, uint32_t wordSize)
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contents_.push_back(input.get());
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} while (input);
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while (contents_.size() & (wordSize-1))
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while (contents_.size() & (wordSize-1)) {
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contents_.push_back(0x00);
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}
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}
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RamMemDevice::RamMemDevice(uint64_t size, uint32_t wordSize)
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@ -29,7 +30,7 @@ RamMemDevice::RamMemDevice(uint64_t size, uint32_t wordSize)
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, wordSize_(wordSize)
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{}
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void RamMemDevice::read(void *data, uint64_t addr, uint64_t size) {
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void RamMemDevice::read(void* data, uint64_t addr, uint64_t size) {
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auto addr_end = addr + size;
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if ((addr & (wordSize_-1))
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|| (addr_end & (wordSize_-1))
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@ -44,7 +45,7 @@ void RamMemDevice::read(void *data, uint64_t addr, uint64_t size) {
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}
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}
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void RamMemDevice::write(const void *data, uint64_t addr, uint64_t size) {
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void RamMemDevice::write(const void* data, uint64_t addr, uint64_t size) {
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auto addr_end = addr + size;
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if ((addr & (wordSize_-1))
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|| (addr_end & (wordSize_-1))
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@ -68,26 +69,26 @@ void RomMemDevice::write(const void* /*data*/, uint64_t /*addr*/, uint64_t /*siz
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///////////////////////////////////////////////////////////////////////////////
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bool MemoryUnit::ADecoder::lookup(uint64_t a, uint32_t wordSize, mem_accessor_t* ma) {
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uint64_t e = a + (wordSize - 1);
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assert(e >= a);
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bool MemoryUnit::ADecoder::lookup(uint64_t addr, uint32_t wordSize, mem_accessor_t* ma) {
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uint64_t end = addr + (wordSize - 1);
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assert(end >= addr);
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for (auto iter = entries_.rbegin(), iterE = entries_.rend(); iter != iterE; ++iter) {
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if (a >= iter->start && e <= iter->end) {
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if (addr >= iter->start && end <= iter->end) {
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ma->md = iter->md;
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ma->addr = a - iter->start;
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ma->addr = addr - iter->start;
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return true;
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}
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}
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return false;
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}
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void MemoryUnit::ADecoder::map(uint64_t a, uint64_t e, MemDevice &m) {
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assert(e >= a);
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entry_t entry{&m, a, e};
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void MemoryUnit::ADecoder::map(uint64_t start, uint64_t end, MemDevice &md) {
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assert(end >= start);
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entry_t entry{&md, start, end};
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entries_.emplace_back(entry);
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}
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void MemoryUnit::ADecoder::read(void *data, uint64_t addr, uint64_t size) {
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void MemoryUnit::ADecoder::read(void* data, uint64_t addr, uint64_t size) {
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mem_accessor_t ma;
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if (!this->lookup(addr, size, &ma)) {
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std::cout << "lookup of 0x" << std::hex << addr << " failed.\n";
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@ -96,7 +97,7 @@ void MemoryUnit::ADecoder::read(void *data, uint64_t addr, uint64_t size) {
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ma.md->read(data, ma.addr, size);
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}
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void MemoryUnit::ADecoder::write(const void *data, uint64_t addr, uint64_t size) {
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void MemoryUnit::ADecoder::write(const void* data, uint64_t addr, uint64_t size) {
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mem_accessor_t ma;
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if (!this->lookup(addr, size, &ma)) {
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std::cout << "lookup of 0x" << std::hex << addr << " failed.\n";
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@ -132,7 +133,7 @@ MemoryUnit::TLBEntry MemoryUnit::tlbLookup(uint64_t vAddr, uint32_t flagMask) {
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}
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}
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void MemoryUnit::read(void *data, uint64_t addr, uint64_t size, bool sup) {
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void MemoryUnit::read(void* data, uint64_t addr, uint64_t size, bool sup) {
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uint64_t pAddr;
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if (enableVM_) {
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uint32_t flagMask = sup ? 8 : 1;
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@ -144,7 +145,7 @@ void MemoryUnit::read(void *data, uint64_t addr, uint64_t size, bool sup) {
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return decoder_.read(data, pAddr, size);
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}
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void MemoryUnit::write(const void *data, uint64_t addr, uint64_t size, bool sup) {
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void MemoryUnit::write(const void* data, uint64_t addr, uint64_t size, bool sup) {
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uint64_t pAddr;
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if (enableVM_) {
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uint32_t flagMask = sup ? 16 : 2;
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@ -169,7 +170,6 @@ void MemoryUnit::tlbRm(uint64_t va) {
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RAM::RAM(uint32_t page_size, uint64_t capacity)
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: capacity_(capacity)
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, size_(0)
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, page_bits_(log2ceil(page_size))
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, last_page_(nullptr)
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, last_page_index_(0) {
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@ -223,14 +223,14 @@ uint8_t *RAM::get(uint64_t address) const {
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return page + page_offset;
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}
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void RAM::read(void *data, uint64_t addr, uint64_t size) {
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void RAM::read(void* data, uint64_t addr, uint64_t size) {
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uint8_t* d = (uint8_t*)data;
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for (uint64_t i = 0; i < size; i++) {
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d[i] = *this->get(addr + i);
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}
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}
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void RAM::write(const void *data, uint64_t addr, uint64_t size) {
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void RAM::write(const void* data, uint64_t addr, uint64_t size) {
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const uint8_t* d = (const uint8_t*)data;
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for (uint64_t i = 0; i < size; i++) {
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*this->get(addr + i) = d[i];
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@ -13,8 +13,8 @@ class MemDevice {
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public:
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virtual ~MemDevice() {}
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virtual uint64_t size() const = 0;
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virtual void read(void *data, uint64_t addr, uint64_t size) = 0;
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virtual void write(const void *data, uint64_t addr, uint64_t size) = 0;
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virtual void read(void* data, uint64_t addr, uint64_t size) = 0;
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virtual void write(const void* data, uint64_t addr, uint64_t size) = 0;
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};
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///////////////////////////////////////////////////////////////////////////////
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@ -22,11 +22,11 @@ public:
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class RamMemDevice : public MemDevice {
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public:
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RamMemDevice(uint64_t size, uint32_t wordSize);
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RamMemDevice(const char *filename, uint32_t wordSize);
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RamMemDevice(const char* filename, uint32_t wordSize);
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~RamMemDevice() {}
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void read(void *data, uint64_t addr, uint64_t size) override;
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void write(const void *data, uint64_t addr, uint64_t size) override;
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void read(void* data, uint64_t addr, uint64_t size) override;
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void write(const void* data, uint64_t addr, uint64_t size) override;
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virtual uint64_t size() const {
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return contents_.size();
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@ -51,7 +51,7 @@ public:
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~RomMemDevice();
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void write(const void *data, uint64_t addr, uint64_t size) override;
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void write(const void* data, uint64_t addr, uint64_t size) override;
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};
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///////////////////////////////////////////////////////////////////////////////
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@ -64,19 +64,19 @@ public:
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: faultAddr(a)
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, notFound(nf)
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{}
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uint64_t faultAddr;
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bool notFound;
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uint64_t faultAddr;
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bool notFound;
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};
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MemoryUnit(uint64_t pageSize = 0);
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void attach(MemDevice &m, uint64_t start, uint64_t end);
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void read(void *data, uint64_t addr, uint64_t size, bool sup);
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void write(const void *data, uint64_t addr, uint64_t size, bool sup);
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void read(void* data, uint64_t addr, uint64_t size, bool sup);
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void write(const void* data, uint64_t addr, uint64_t size, bool sup);
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void tlbAdd(uint64_t virt, uint64_t phys, uint32_t flags);
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void tlbRm(uint64_t va);
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void tlbRm(uint64_t vaddr);
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void tlbFlush() {
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tlb_.clear();
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}
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@ -86,25 +86,25 @@ private:
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public:
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ADecoder() {}
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void read(void *data, uint64_t addr, uint64_t size);
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void write(const void *data, uint64_t addr, uint64_t size);
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void read(void* data, uint64_t addr, uint64_t size);
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void write(const void* data, uint64_t addr, uint64_t size);
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void map(uint64_t start, uint64_t end, MemDevice &md);
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private:
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struct mem_accessor_t {
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MemDevice* md;
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uint64_t addr;
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MemDevice* md;
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uint64_t addr;
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};
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struct entry_t {
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MemDevice *md;
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uint64_t start;
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uint64_t end;
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MemDevice* md;
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uint64_t start;
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uint64_t end;
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};
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bool lookup(uint64_t a, uint32_t wordSize, mem_accessor_t*);
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bool lookup(uint64_t addr, uint32_t wordSize, mem_accessor_t*);
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std::vector<entry_t> entries_;
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};
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@ -122,9 +122,9 @@ private:
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TLBEntry tlbLookup(uint64_t vAddr, uint32_t flagMask);
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std::unordered_map<uint64_t, TLBEntry> tlb_;
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uint64_t pageSize_;
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ADecoder decoder_;
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bool enableVM_;
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uint64_t pageSize_;
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ADecoder decoder_;
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bool enableVM_;
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};
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///////////////////////////////////////////////////////////////////////////////
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@ -139,8 +139,8 @@ public:
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uint64_t size() const override;
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void read(void *data, uint64_t addr, uint64_t size) override;
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void write(const void *data, uint64_t addr, uint64_t size) override;
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void read(void* data, uint64_t addr, uint64_t size) override;
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void write(const void* data, uint64_t addr, uint64_t size) override;
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void loadBinImage(const char* filename, uint64_t destination);
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void loadHexImage(const char* filename);
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@ -158,7 +158,6 @@ private:
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uint8_t *get(uint64_t address) const;
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uint64_t capacity_;
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uint64_t size_;
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uint32_t page_bits_;
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mutable std::unordered_map<uint64_t, uint8_t*> pages_;
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mutable uint8_t* last_page_;
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@ -61,7 +61,7 @@ int main(int argc, char **argv) {
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// setup base DCRs
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processor.write_dcr(DCR_BASE_STARTUP_ADDR0, STARTUP_ADDR & 0xffffffff);
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#if XLEN == 64
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#if (XLEN == 64)
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processor.write_dcr(DCR_BASE_STARTUP_ADDR1, STARTUP_ADDR >> 32);
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#endif
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processor.write_dcr(DCR_BASE_MPM_CLASS, 0);
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@ -273,7 +273,7 @@ bool Cluster::running() const {
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return false;
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}
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bool Cluster::getIRegValue(int* value, int reg) const {
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bool Cluster::getIRegValue(Word* value, int reg) const {
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for (auto& core : cores_) {
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if (core->check_exit()) {
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*value = core->getIRegValue(reg);
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@ -52,7 +52,7 @@ public:
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bool running() const;
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bool getIRegValue(int* value, int reg) const;
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bool getIRegValue(Word* value, int reg) const;
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void bind(SimPort<MemReq>* mem_req_port, SimPort<MemRsp>* mem_rsp_port);
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@ -123,7 +123,11 @@ void Core::reset() {
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void Core::attach_ram(RAM* ram) {
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// bind RAM to memory unit
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mmu_.attach(*ram, 0, 0xFFFFFFFF);
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#if (XLEN == 64)
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mmu_.attach(*ram, 0, 0xFFFFFFFFFFFFFFFF);
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#else
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mmu_.attach(*ram, 0, 0xFFFFFFFF);
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#endif
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}
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void Core::cout_flush() {
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@ -108,7 +108,7 @@ public:
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return dcrs_;
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}
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uint32_t getIRegValue(int reg) const {
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Word getIRegValue(int reg) const {
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return warps_.at(0)->getIRegValue(reg);
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}
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@ -78,7 +78,7 @@ int main(int argc, char **argv) {
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// setup base DCRs
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processor.write_dcr(DCR_BASE_STARTUP_ADDR0, STARTUP_ADDR & 0xffffffff);
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#if XLEN == 64
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#if (XLEN == 64)
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processor.write_dcr(DCR_BASE_STARTUP_ADDR1, STARTUP_ADDR >> 32);
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#endif
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processor.write_dcr(DCR_BASE_MPM_CLASS, 0);
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@ -73,7 +73,7 @@ int ProcessorImpl::run() {
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SimPlatform::instance().reset();
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this->clear_perf_counters();
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bool running;
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int exitcode = 0;
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Word exitcode = 0;
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do {
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SimPlatform::instance().tick();
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running = false;
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@ -13,13 +13,13 @@
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namespace vortex {
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typedef uint8_t Byte;
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#if XLEN == 32
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#if (XLEN == 32)
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typedef uint32_t Word;
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typedef int32_t WordI;
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typedef uint64_t DWord;
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typedef int64_t DWordI;
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typedef uint32_t FWord;
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#elif XLEN == 64
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#elif (XLEN == 64)
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typedef uint64_t Word;
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typedef int64_t WordI;
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typedef __uint128_t DWord;
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@ -24,7 +24,7 @@ Warp::Warp(Core *core, uint32_t warp_id)
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void Warp::clear() {
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active_ = false;
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PC_ = core_->dcrs().base_dcrs.read(DCR_BASE_STARTUP_ADDR0);
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#if XLEN == 64
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#if (XLEN == 64)
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PC_ = (uint64_t(core_->dcrs().base_dcrs.read(DCR_BASE_STARTUP_ADDR1)) << 32) | PC_;
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#endif
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tmask_.reset();
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@ -87,7 +87,7 @@ public:
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return 0;
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}
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uint32_t getIRegValue(uint32_t reg) const {
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Word getIRegValue(uint32_t reg) const {
|
||||
return ireg_file_.at(0).at(reg);
|
||||
}
|
||||
|
||||
|
|
|
|||
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Reference in a new issue