update scope tap testing

ci/regression.sh.in

@@ -260,11 +260,11 @@ config2()
     # disabling ZICOND extension
     CONFIGS="-DEXT_ZICOND_DISABLE" ./ci/blackbox.sh --driver=rtlsim --app=demo
 
-    # test 128-bit MEM block
+    # test 128-bit memory block
     CONFIGS="-DMEM_BLOCK_SIZE=16" ./ci/blackbox.sh --driver=opae --app=mstress
     CONFIGS="-DMEM_BLOCK_SIZE=16" ./ci/blackbox.sh --driver=xrt --app=mstress
 
-    # test XLEN-bit MEM block
+    # test XLEN-bit memory block
     CONFIGS="-DMEM_BLOCK_SIZE=$XSIZE" ./ci/blackbox.sh --driver=opae --app=mstress
     CONFIGS="-DMEM_BLOCK_SIZE=$XSIZE" ./ci/blackbox.sh --driver=simx --app=mstress
 
@@ -272,7 +272,7 @@ config2()
     CONFIGS="-DMEM_BLOCK_SIZE=16" ./ci/blackbox.sh --driver=rtlsim --app=mstress --threads=8
     CONFIGS="-DMEM_BLOCK_SIZE=16" ./ci/blackbox.sh --driver=simx --app=mstress --threads=8
 
-    # test single-bank DRAM
+    # test single-bank memory
     if [ "$XLEN" == "64" ]; then
         CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=48" ./ci/blackbox.sh --driver=opae --app=mstress
         CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=48" ./ci/blackbox.sh --driver=xrt --app=mstress
@@ -281,11 +281,16 @@ config2()
         CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32" ./ci/blackbox.sh --driver=xrt --app=mstress
     fi
 
-    # test 33-bit DRAM address
+    # test larger memory address
+    if [ "$XLEN" == "64" ]; then
+        CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=49" ./ci/blackbox.sh --driver=opae --app=mstress
+        CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=49" ./ci/blackbox.sh --driver=xrt --app=mstress
+    else
         CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=33" ./ci/blackbox.sh --driver=opae --app=mstress
         CONFIGS="-DPLATFORM_MEMORY_ADDR_WIDTH=33" ./ci/blackbox.sh --driver=xrt --app=mstress
+    fi
 
-    # test DRAM banks interleaving
+    # test memory banks interleaving
     CONFIGS="-DPLATFORM_MEMORY_INTERLEAVE=1" ./ci/blackbox.sh --driver=opae --app=mstress
     CONFIGS="-DPLATFORM_MEMORY_INTERLEAVE=0" ./ci/blackbox.sh --driver=opae --app=mstress
 
@@ -326,8 +331,8 @@ scope()
 {
     echo "begin scope tests..."
 
-    ./ci/blackbox.sh --driver=opae --scope --app=demo --args="-n1"
+    SCOPE_DEPTH=1024 ./ci/blackbox.sh --driver=opae --app=demo --args="-n1" --scope
-    ./ci/blackbox.sh --driver=xrt --scope --app=demo --args="-n1"
+    SCOPE_DEPTH=1024 ./ci/blackbox.sh --driver=xrt --app=demo --args="-n1" --scope
 
     echo "debugging scope done!"
 }

runtime/common/scope.cpp

@@ -261,6 +261,20 @@ int vx_scope_start(scope_callback_t* callback, vx_device_h hdevice, uint64_t sta
     }
   }
 
+  // setup capture size
+  const char* capture_size_env = std::getenv("SCOPE_DEPTH");
+  if (capture_size_env != nullptr) {
+    std::stringstream ss(capture_size_env);
+    uint32_t capture_size;
+    if (ss >> capture_size) {
+      for (auto& tap : json_obj["taps"]) {
+        auto id = tap["id"].get<uint32_t>();
+        uint64_t cmd_depth = (capture_size << 11) | (id << 3) | CMD_SET_DEPTH;
+        CHECK_ERR(g_callback.registerWrite(hdevice, cmd_depth));
+      }
+    }
+  }
+
   // set stop time
   if (stop_time != uint64_t(-1)) {
     std::cout << "[SCOPE] stop time: " << std::dec << stop_time << "s" << std::endl;

sim/opaesim/opae_sim.cpp

@@ -78,8 +78,9 @@ static uint64_t trace_stop_time = TRACE_STOP_TIME;
 
 bool sim_trace_enabled() {
   if (timestamp >= trace_start_time
-   && timestamp < trace_stop_time)
+   && timestamp < trace_stop_time) {
     return true;
+   }
   return trace_enabled;
 }
 
@@ -207,8 +208,9 @@ public:
     std::lock_guard<std::mutex> guard(mutex_);
 
     // simulate CPU-GPU latency
-    for (uint32_t i = 0; i < CPU_GPU_LATENCY; ++i)
+    for (uint32_t i = 0; i < CPU_GPU_LATENCY; ++i) {
       this->tick();
+    }
 
     // simulate mmio request
     device_->vcp2af_sRxPort_c0_mmioRdValid = 1;
@@ -225,8 +227,9 @@ public:
     std::lock_guard<std::mutex> guard(mutex_);
 
     // simulate CPU-GPU latency
-    for (uint32_t i = 0; i < CPU_GPU_LATENCY; ++i)
+    for (uint32_t i = 0; i < CPU_GPU_LATENCY; ++i) {
       this->tick();
+    }
 
     // simulate mmio request
     device_->vcp2af_sRxPort_c0_mmioWrValid = 1;
@@ -329,8 +332,9 @@ private:
     // schedule CCI read responses
     std::list<cci_rd_req_t>::iterator cci_rd_it(cci_reads_.end());
     for (auto it = cci_reads_.begin(), ie = cci_reads_.end(); it != ie; ++it) {
-      if (it->cycles_left > 0)
+      if (it->cycles_left > 0) {
         it->cycles_left -= 1;
+      }
       if ((cci_rd_it == ie) && (it->cycles_left == 0)) {
         cci_rd_it = it;
       }
@@ -339,8 +343,9 @@ private:
     // schedule CCI write responses
     std::list<cci_wr_req_t>::iterator cci_wr_it(cci_writes_.end());
     for (auto it = cci_writes_.begin(), ie = cci_writes_.end(); it != ie; ++it) {
-      if (it->cycles_left > 0)
+      if (it->cycles_left > 0) {
         it->cycles_left -= 1;
+      }
       if ((cci_wr_it == ie) && (it->cycles_left == 0)) {
         cci_wr_it = it;
       }