ALL tests passing - handshake

rtl/VX_cache/VX_cache_miss_resrv.v

@@ -118,6 +118,10 @@ module VX_cache_miss_resrv
 		assign miss_resrv_addr_st0  = addr_table[dequeue_index];
 		assign {miss_resrv_data_st0, miss_resrv_tid_st0, miss_resrv_rd_st0, miss_resrv_wb_st0, miss_resrv_warp_num_st0, miss_resrv_mem_read_st0, miss_resrv_mem_write_st0} = metadata_table[dequeue_index];
 
+
+		wire mrvq_push = miss_add && enqueue_possible && (MRVQ_SIZE != 2);
+		wire mrvq_pop  = miss_resrv_pop && dequeue_possible;
+
 		wire update_ready = (|make_ready);
 		integer i;
 		always @(posedge clk) begin
@@ -128,8 +132,7 @@ module VX_cache_miss_resrv
 				addr_table  <= 0;
 				pc_table    <= 0;
 			end else begin
-				if (miss_add && enqueue_possible && (MRVQ_SIZE != 2)) begin
-					size                          <= size + 1;
+				if (mrvq_push) begin
 					valid_table[enqueue_index]    <= 1;
 					ready_table[enqueue_index]    <= 0;
 					pc_table[enqueue_index]       <= miss_add_pc;
@@ -142,8 +145,7 @@ module VX_cache_miss_resrv
 					ready_table <= ready_table | make_ready;
 				end
 
-				if (miss_resrv_pop && dequeue_possible) begin
-					size                          <= size - 1;
+				if (mrvq_pop) begin
 					valid_table[dequeue_index]    <= 0;
 					ready_table[dequeue_index]    <= 0;
 					addr_table[dequeue_index]     <= 0;
@@ -152,6 +154,16 @@ module VX_cache_miss_resrv
 					head_ptr                      <= head_ptr + 1;
 				end
 
+				if (!(mrvq_push && mrvq_pop)) begin
+					if (mrvq_push) begin
+						size <= size + 1;
+					end
+
+					if (mrvq_pop) begin
+						size <= size - 1;
+					end
+				end
+
 			end
 		end
 

rtl/VX_cache/VX_tag_data_access.v

@@ -239,7 +239,7 @@ module VX_tag_data_access
     wire[3:0] sh_mask = (b0 ? 4'b0011 : 4'b1100);
 
     wire should_write = (sw || sb || sh) && valid_req_st1e && use_read_valid_st1e && !miss_st1e;
-    wire force_write  = real_writefill && valid_req_st1e && miss_st1e && (!use_read_valid_st1e || (use_read_valid_st1e && !miss_st1e));
+    wire force_write  = real_writefill;
 
     wire[`DBANK_LINE_SIZE_RNG][3:0]  we;
     wire[`DBANK_LINE_SIZE_RNG][31:0] data_write;
@@ -277,7 +277,7 @@ module VX_tag_data_access
 	assign readdata_st1e       = use_read_data_st1e;
 	assign readtag_st1e        = use_read_tag_st1e;
 	assign fill_sent           = miss_st1e;
-	assign fill_saw_dirty_st1e = force_write && dirty_st1e && miss_st1e;
+	assign fill_saw_dirty_st1e = real_writefill && dirty_st1e;
 	assign invalidate_line     = is_snp_st1e && !miss_st1e;
 
 endmodule

rtl/VX_cache/VX_tag_data_structure.v

@@ -93,7 +93,7 @@ module VX_tag_data_structure
     		end
     	end else if (fill_sent) begin
             dirty[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
-            valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
+            // valid[write_addr[`LINE_SELECT_ADDR_RNG]] <= 0;
         end
 
         if (invalidate) begin

rtl/VX_define.v

@@ -219,7 +219,7 @@
 
 // Dram Fill Rsp Queue Size
 `ifndef DDFPQ_SIZE
-`define DDFPQ_SIZE 2
+`define DDFPQ_SIZE 32
 `endif
 
 // Snoop Req Queue
@@ -327,7 +327,7 @@
 
 // Dram Fill Rsp Queue Size
 `ifndef IDFPQ_SIZE
-`define IDFPQ_SIZE 2
+`define IDFPQ_SIZE 32
 `endif
 
 // Snoop Req Queue
@@ -433,7 +433,7 @@
 
 // Dram Fill Rsp Queue Size
 `ifndef SDFPQ_SIZE
-`define SDFPQ_SIZE 16
+`define SDFPQ_SIZE 0
 `endif
 
 // Snoop Req Queue
@@ -538,7 +538,7 @@
 
 // Dram Fill Rsp Queue Size
 `ifndef LLDFPQ_SIZE
-`define LLDFPQ_SIZE 2
+`define LLDFPQ_SIZE 32
 `endif
 
 // Snoop Req Queue
@@ -643,7 +643,7 @@
 
 // Dram Fill Rsp Queue Size
 `ifndef L3DFPQ_SIZE
-`define L3DFPQ_SIZE 2
+`define L3DFPQ_SIZE 32
 `endif
 
 // Snoop Req Queue

rtl/VX_fetch.v

@@ -98,5 +98,8 @@ module VX_fetch (
 		assign fe_inst_meta_fi.instruction = 32'h0;
 		assign fe_inst_meta_fi.inst_pc     = warp_pc;
 
+		wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000e94) && (warp_num == 0);
+		wire end_mat_add   = scheduled_warp && (warp_pc == 32'h80000ef0) && (warp_num == 0);
+
 
 endmodule

rtl/Vortex.v

@@ -30,11 +30,31 @@ module Vortex
 	input  wire [31:0]      dram_fill_rsp_addr,
 	input  wire [31:0]      dram_fill_rsp_data[`DBANK_LINE_SIZE_RNG],
 
+
+	// DRAM Icache Req
+	output wire                              I_dram_req,
+	output wire                              I_dram_req_write,
+	output wire                              I_dram_req_read,
+	output wire [31:0]                       I_dram_req_addr,
+	output wire [31:0]                       I_dram_req_size,
+	output wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_req_data,
+	output wire [31:0]                       I_dram_expected_lat,
+
+	// DRAM Icache Res
+	output wire                              I_dram_fill_accept,
+	input  wire                              I_dram_fill_rsp,
+	input  wire [31:0]                       I_dram_fill_rsp_addr,
+	input  wire [`IBANK_LINE_SIZE_RNG][31:0] I_dram_fill_rsp_data,
+
 	// LLC Snooping
 	input  wire             snp_req,
 	input  wire [31:0]      snp_req_addr,
 	output wire             snp_req_delay,
 
+	input  wire                              I_snp_req,
+	input  wire [31:0]                       I_snp_req_addr,
+	output wire                              I_snp_req_delay,
+
 	output wire             out_ebreak
 
 `else 

runtime/mains/simple/vx_simple_main.c

@@ -55,14 +55,33 @@ int main()
 
 	vx_print_str("Let's start... (This might take a while)\n");
 	unsigned what[36];
+	bool passed = true;
 	for (int i = 0; i < 36; i++)
 	{
 		what[i] = i;
+		// vx_print_hex(i);
+		// vx_printf(": ", what[i]);
+		if (what[i] != i)
+		{
+			passed = false;
+			vx_printf("T1 Fail On ", i);
+		}
 	}
 
 	for (int i = 0; i < 36; i++)
 	{
-		vx_printf("Value: ", what[i]);
+		// vx_print_hex(i);
+		// vx_printf(": ", what[i]);
+		if (what[i] != i)
+		{
+			passed = false;
+			vx_printf("T2 Fail on ", i);
+		}
+	}
+
+	if (passed)
+	{
+		vx_print_str("Wr->read and repeat(Wr) tests passed!\n");
 	}
 
 
@@ -80,8 +99,8 @@ int main()
 
 
 	// Test wspawn
-	// vx_print_str("test_wspawn\n");
-	// test_wsapwn();
+	vx_print_str("test_wspawn\n");
+	test_wsapwn();
 
 	vx_print_str("Shared Memory test\n");
 	unsigned * ptr = (unsigned *) 0xFFFF0000;
@@ -99,31 +118,34 @@ int main()
 
 	}
 
-	// vx_print_str("vx_spawnWarps mat_add_kernel\n");
+	vx_print_str("vx_spawnWarps mat_add_kernel\n");
 
-	// mat_add_args_t arguments;
-	// arguments.x         = x;
-	// arguments.y         = y;
-	// arguments.z         = z;
-	// arguments.numColums = 4;
-	// arguments.numRows   = 4;
+	mat_add_args_t arguments;
+	arguments.x         = x;
+	arguments.y         = y;
+	arguments.z         = z;
+	arguments.numColums = 4;
+	arguments.numRows   = 4;
 
 
-	// int numWarps   = 4;
-	// int numThreads = 4;
+	int numWarps   = 4;
+	int numThreads = 4;
 
-	// vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments);
+	vx_spawnWarps(numWarps, numThreads, mat_add_kernel, &arguments);
 
-	// for (int i = 0; i < numWarps; i++)
-	// {
-	// 	for (int j = 0; j < numThreads; j++)
-	// 	{
-	// 		unsigned index = (i * arguments.numColums) + j;
-	// 		vx_print_hex(z[index]);
-	// 		vx_print_str(" ");
-	// 	}
-	// 	vx_print_str("\n");
-	// }
+	vx_print_str("Waiting to ensure other warps are done... (Take a while)\n");
+	for (int i = 0; i < 5000; i++) {}
+
+	for (int i = 0; i < numWarps; i++)
+	{
+		for (int j = 0; j < numThreads; j++)
+		{
+			unsigned index = (i * arguments.numColums) + j;
+			vx_print_hex(z[index]);
+			vx_print_str(" ");
+		}
+		vx_print_str("\n");
+	}
 
 	return 0;
 }

runtime/tests/tests.c

@@ -100,6 +100,8 @@ void test_wsapwn()
 	vx_wspawn(4, func_ptr);
 	simple_kernel();
 
+	for (int i = 0; i < 100; i++) {}
+
 	vx_print_hex(wsapwn_arr[0]);
 	vx_print_str("\n");
 	vx_print_hex(wsapwn_arr[1]);