mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-25 06:17:38 -04:00
Merge branch 'simx64'
This commit is contained in:
Santosh Srivatsan
commit
5edb9098ce
115 changed files with 9835 additions and 246 deletions
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@ -16,7 +16,7 @@
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using namespace vortex;
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static bool HasDivergentThreads(const ThreadMask &thread_mask,
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const std::vector<std::vector<Word>> ®_file,
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const std::vector<std::vector<DoubleWord>> ®_file,
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unsigned reg) {
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bool cond;
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size_t thread_idx = 0;
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@ -52,7 +52,7 @@ inline void update_fcrs(uint32_t fflags, Core* core, uint32_t tid, uint32_t wid)
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void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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assert(tmask_.any());
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Word nextPC = PC_ + core_->arch().wsize();
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DoubleWord nextPC = PC_ + 4;
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Word func2 = instr.getFunc2();
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Word func3 = instr.getFunc3();
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@ -64,13 +64,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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int rsrc0 = instr.getRSrc(0);
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int rsrc1 = instr.getRSrc(1);
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int rsrc2 = instr.getRSrc(2);
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Word immsrc = instr.getImm();
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DoubleWord immsrc = instr.getImm();
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Word vmask = instr.getVmask();
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int num_threads = core_->arch().num_threads();
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std::vector<Word[3]> rsdata(num_threads);
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std::vector<Word> rddata(num_threads);
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std::vector<DoubleWord[3]> rsdata(num_threads);
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std::vector<DoubleWord> rddata(num_threads);
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int num_rsrcs = instr.getNRSrc();
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if (num_rsrcs) {
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@ -123,7 +123,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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for (int t = 0; t < num_threads; ++t) {
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if (!tmask_.test(t))
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continue;
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rddata[t] = (immsrc << 12) & 0xfffff000;
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// simx64
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rddata[t] = (immsrc << 12) & 0xfffffffffffff000;
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}
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rd_write = true;
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break;
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@ -133,7 +134,8 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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for (int t = 0; t < num_threads; ++t) {
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if (!tmask_.test(t))
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continue;
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rddata[t] = ((immsrc << 12) & 0xfffff000) + PC_;
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// simx64
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rddata[t] = ((immsrc << 12) & 0xfffffffffffff000) + PC_;
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}
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rd_write = true;
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break;
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@ -148,48 +150,42 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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if (func7 & 0x1) {
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switch (func3) {
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case 0:
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// MUL
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rddata[t] = ((WordI)rsdata[t][0]) * ((WordI)rsdata[t][1]);
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// RV32M: MUL
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rddata[t] = ((DoubleWordI)rsdata[t][0]) * ((DoubleWordI)rsdata[t][1]);
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trace->alu.type = AluType::IMUL;
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break;
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case 1: {
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// MULH
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int64_t first = (int64_t)rsdata[t][0];
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if (rsdata[t][0] & 0x80000000) {
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first = first | 0xFFFFFFFF00000000;
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}
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int64_t second = (int64_t)rsdata[t][1];
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if (rsdata[t][1] & 0x80000000) {
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second = second | 0xFFFFFFFF00000000;
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}
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uint64_t result = first * second;
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rddata[t] = (result >> 32) & 0xFFFFFFFF;
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// RV32M: MULH
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// simx64
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__int128_t first = sext128((__int128_t)rsdata[t][0], 64);
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__int128_t second = sext128((__int128_t)rsdata[t][1], 64);
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rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
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trace->alu.type = AluType::IMUL;
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} break;
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case 2: {
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// MULHSU
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int64_t first = (int64_t)rsdata[t][0];
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if (rsdata[t][0] & 0x80000000) {
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first = first | 0xFFFFFFFF00000000;
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}
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int64_t second = (int64_t)rsdata[t][1];
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rddata[t] = ((first * second) >> 32) & 0xFFFFFFFF;
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// RV32M: MULHSU
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// simx64
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__int128_t first = sext128((__int128_t)rsdata[t][0], 64);
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__int128_t second = (__int128_t)rsdata[t][1];
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rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
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trace->alu.type = AluType::IMUL;
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} break;
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case 3: {
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// MULHU
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uint64_t first = (uint64_t)rsdata[t][0];
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uint64_t second = (uint64_t)rsdata[t][1];
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rddata[t] = ((first * second) >> 32) & 0xFFFFFFFF;
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// RV32M: MULHU
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// simx64
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__uint128_t first = (__int128_t)rsdata[t][0];
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__uint128_t second = (__int128_t)rsdata[t][1];
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rddata[t] = ((first * second) >> 64) & 0xFFFFFFFFFFFFFFFF;
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trace->alu.type = AluType::IMUL;
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} break;
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case 4: {
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// DIV
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WordI dividen = rsdata[t][0];
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WordI divisor = rsdata[t][1];
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// RV32M: DIV
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// simx64
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DoubleWordI dividen = rsdata[t][0];
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DoubleWordI divisor = rsdata[t][1];
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if (divisor == 0) {
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rddata[t] = -1;
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} else if (dividen == WordI(0x80000000) && divisor == WordI(0xffffffff)) {
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} else if (dividen == DoubleWordI(0x8000000000000000) && divisor == DoubleWordI(0xffffffffffffffff)) {
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rddata[t] = dividen;
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} else {
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rddata[t] = dividen / divisor;
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@ -197,9 +193,10 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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trace->alu.type = AluType::IDIV;
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} break;
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case 5: {
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// DIVU
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Word dividen = rsdata[t][0];
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Word divisor = rsdata[t][1];
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// RV32M: DIVU
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// simx64
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DoubleWord dividen = rsdata[t][0];
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DoubleWord divisor = rsdata[t][1];
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if (divisor == 0) {
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rddata[t] = -1;
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} else {
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@ -208,12 +205,13 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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trace->alu.type = AluType::IDIV;
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} break;
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case 6: {
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// REM
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WordI dividen = rsdata[t][0];
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WordI divisor = rsdata[t][1];
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// RV32M: REM
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// simx64
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DoubleWordI dividen = rsdata[t][0];
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DoubleWordI divisor = rsdata[t][1];
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if (rsdata[t][1] == 0) {
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rddata[t] = dividen;
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} else if (dividen == WordI(0x80000000) && divisor == WordI(0xffffffff)) {
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} else if (dividen == DoubleWordI(0x8000000000000000) && divisor == DoubleWordI(0xffffffffffffffff)) {
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rddata[t] = 0;
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} else {
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rddata[t] = dividen % divisor;
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@ -221,9 +219,9 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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trace->alu.type = AluType::IDIV;
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} break;
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case 7: {
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// REMU
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Word dividen = rsdata[t][0];
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Word divisor = rsdata[t][1];
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// RV32M: REMU
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DoubleWord dividen = rsdata[t][0];
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DoubleWord divisor = rsdata[t][1];
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if (rsdata[t][1] == 0) {
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rddata[t] = dividen;
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} else {
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@ -238,44 +236,44 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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switch (func3) {
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case 0:
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if (func7) {
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// SUB
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// RV32I: SUB
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rddata[t] = rsdata[t][0] - rsdata[t][1];
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} else {
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// ADD
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// RV32I: ADD
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rddata[t] = rsdata[t][0] + rsdata[t][1];
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}
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break;
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case 1:
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// SHL
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// RV32I: SHL
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rddata[t] = rsdata[t][0] << rsdata[t][1];
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break;
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case 2:
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// LT
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rddata[t] = (WordI(rsdata[t][0]) < WordI(rsdata[t][1]));
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// RV32I: LT
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rddata[t] = (DoubleWordI(rsdata[t][0]) < DoubleWordI(rsdata[t][1]));
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break;
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case 3:
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// LTU
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rddata[t] = (Word(rsdata[t][0]) < Word(rsdata[t][1]));
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// RV32I: LTU
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rddata[t] = (DoubleWord(rsdata[t][0]) < DoubleWord(rsdata[t][1]));
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break;
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case 4:
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// XOR
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// RV32I: XOR
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rddata[t] = rsdata[t][0] ^ rsdata[t][1];
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break;
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case 5:
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if (func7) {
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// SRA
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rddata[t] = WordI(rsdata[t][0]) >> WordI(rsdata[t][1]);
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// RV32I: SRA
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rddata[t] = DoubleWordI(rsdata[t][0]) >> DoubleWordI(rsdata[t][1]);
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} else {
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// SHR
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rddata[t] = Word(rsdata[t][0]) >> Word(rsdata[t][1]);
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// RV32I: SHR
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rddata[t] = DoubleWord(rsdata[t][0]) >> DoubleWord(rsdata[t][1]);
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}
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break;
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case 6:
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// OR
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// RV32I: OR
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rddata[t] = rsdata[t][0] | rsdata[t][1];
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break;
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case 7:
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// AND
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// RV32I: AND
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rddata[t] = rsdata[t][0] & rsdata[t][1];
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break;
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default:
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@ -294,42 +292,42 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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continue;
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switch (func3) {
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case 0:
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// ADDI
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// RV32I: ADDI
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rddata[t] = rsdata[t][0] + immsrc;
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break;
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case 1:
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// SLLI
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// RV32I: SLLI
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rddata[t] = rsdata[t][0] << immsrc;
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break;
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case 2:
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// SLTI
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rddata[t] = (WordI(rsdata[t][0]) < WordI(immsrc));
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// RV32I: SLTI
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rddata[t] = (DoubleWordI(rsdata[t][0]) < DoubleWordI(immsrc));
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break;
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case 3: {
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// SLTIU
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rddata[t] = (Word(rsdata[t][0]) < Word(immsrc));
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// RV32I: SLTIU
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rddata[t] = (DoubleWord(rsdata[t][0]) < DoubleWord(immsrc));
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} break;
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case 4:
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// XORI
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// RV32I: XORI
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rddata[t] = rsdata[t][0] ^ immsrc;
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break;
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case 5:
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if (func7) {
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// SRAI
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Word result = WordI(rsdata[t][0]) >> immsrc;
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// RV32I: SRAI
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DoubleWord result = WordI(rsdata[t][0]) >> immsrc;
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rddata[t] = result;
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} else {
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// SRLI
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Word result = Word(rsdata[t][0]) >> immsrc;
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// RV32I: SRLI
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DoubleWord result = Word(rsdata[t][0]) >> immsrc;
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rddata[t] = result;
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}
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break;
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case 6:
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// ORI
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// RV32I: ORI
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rddata[t] = rsdata[t][0] | immsrc;
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break;
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case 7:
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// ANDI
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// RV32I: ANDI
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rddata[t] = rsdata[t][0] & immsrc;
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break;
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}
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|
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@ -346,38 +344,38 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
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continue;
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switch (func3) {
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case 0:
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// BEQ
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// RV32I: BEQ
|
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if (rsdata[t][0] == rsdata[t][1]) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 1:
|
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// BNE
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// RV32I: BNE
|
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if (rsdata[t][0] != rsdata[t][1]) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 4:
|
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// BLT
|
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if (WordI(rsdata[t][0]) < WordI(rsdata[t][1])) {
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// RV32I: BLT
|
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if (DoubleWordI(rsdata[t][0]) < DoubleWordI(rsdata[t][1])) {
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nextPC = PC_ + immsrc;
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}
|
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break;
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case 5:
|
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// BGE
|
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if (WordI(rsdata[t][0]) >= WordI(rsdata[t][1])) {
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// RV32I: BGE
|
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if (DoubleWordI(rsdata[t][0]) >= DoubleWordI(rsdata[t][1])) {
|
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nextPC = PC_ + immsrc;
|
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}
|
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break;
|
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case 6:
|
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// BLTU
|
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if (Word(rsdata[t][0]) < Word(rsdata[t][1])) {
|
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// RV32I: BLTU
|
||||
if (DoubleWord(rsdata[t][0]) < DoubleWord(rsdata[t][1])) {
|
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nextPC = PC_ + immsrc;
|
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}
|
||||
break;
|
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case 7:
|
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// BGEU
|
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if (Word(rsdata[t][0]) >= Word(rsdata[t][1])) {
|
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// RV32I: BGEU
|
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if (DoubleWord(rsdata[t][0]) >= DoubleWord(rsdata[t][1])) {
|
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nextPC = PC_ + immsrc;
|
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}
|
||||
break;
|
||||
|
|
@ -425,32 +423,39 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
for (int t = 0; t < num_threads; ++t) {
|
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if (!tmask_.test(t))
|
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continue;
|
||||
Word mem_addr = ((rsdata[t][0] + immsrc) & 0xFFFFFFFC); // word aligned
|
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Word shift_by = ((rsdata[t][0] + immsrc) & 0x00000003) * 8;
|
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Word data_read = core_->dcache_read(mem_addr, 4);
|
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DoubleWord mem_addr = ((rsdata[t][0] + immsrc) & 0xFFFFFFFFFFFFFFF8); // word aligned
|
||||
Word shift_by = ((rsdata[t][0] + immsrc) & 0x00000007) * 8;
|
||||
// simx64
|
||||
DoubleWord data_read = core_->dcache_read(mem_addr, 8);
|
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trace->mem_addrs.at(t).push_back({mem_addr, 4});
|
||||
DP(4, "LOAD MEM: ADDRESS=0x" << std::hex << mem_addr << ", DATA=0x" << data_read);
|
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switch (func3) {
|
||||
case 0:
|
||||
// LBI
|
||||
// RV32I: LBI
|
||||
rddata[t] = sext32((data_read >> shift_by) & 0xFF, 8);
|
||||
break;
|
||||
case 1:
|
||||
// LHI
|
||||
// RV32I: LHI
|
||||
rddata[t] = sext32((data_read >> shift_by) & 0xFFFF, 16);
|
||||
break;
|
||||
case 2:
|
||||
// LW
|
||||
rddata[t] = data_read;
|
||||
// RV32I: LW
|
||||
rddata[t] = sext32((data_read >> shift_by) & 0xFFFFFFFF, 32);
|
||||
break;
|
||||
case 3:
|
||||
// RV64I: LD
|
||||
rddata[t] = data_read;
|
||||
case 4:
|
||||
// LBU
|
||||
rddata[t] = Word((data_read >> shift_by) & 0xFF);
|
||||
// RV32I: LBU
|
||||
rddata[t] = DoubleWord((data_read >> shift_by) & 0xFF);
|
||||
break;
|
||||
case 5:
|
||||
// LHU
|
||||
rddata[t] = Word((data_read >> shift_by) & 0xFFFF);
|
||||
// RV32I: LHU
|
||||
rddata[t] = DoubleWord((data_read >> shift_by) & 0xFFFF);
|
||||
break;
|
||||
case 6:
|
||||
// RV64I: LWU
|
||||
rddata[t] = DoubleWord((data_read >> shift_by) & 0xFFFFFFFF);
|
||||
default:
|
||||
std::abort();
|
||||
}
|
||||
|
|
@ -490,22 +495,25 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
for (int t = 0; t < num_threads; ++t) {
|
||||
if (!tmask_.test(t))
|
||||
continue;
|
||||
Word mem_addr = rsdata[t][0] + immsrc;
|
||||
DoubleWord mem_addr = rsdata[t][0] + immsrc;
|
||||
trace->mem_addrs.at(t).push_back({mem_addr, (1u << func3)});
|
||||
DP(4, "STORE MEM: ADDRESS=0x" << std::hex << mem_addr);
|
||||
switch (func3) {
|
||||
case 0:
|
||||
// SB
|
||||
// RV32I: SB
|
||||
core_->dcache_write(mem_addr, rsdata[t][1] & 0x000000FF, 1);
|
||||
break;
|
||||
case 1:
|
||||
// SH
|
||||
core_->dcache_write(mem_addr, rsdata[t][1], 2);
|
||||
// RV32I: SH
|
||||
core_->dcache_write(mem_addr, rsdata[t][1] & 0x0000FFFF, 2);
|
||||
break;
|
||||
case 2:
|
||||
// SW
|
||||
core_->dcache_write(mem_addr, rsdata[t][1], 4);
|
||||
// RV32I: SW
|
||||
core_->dcache_write(mem_addr, rsdata[t][1] & 0xFFFFFFFF, 4);
|
||||
break;
|
||||
case 3:
|
||||
// RV64I: SD
|
||||
core_->dcache_write(mem_addr, rsdata[t][1], 8);
|
||||
default:
|
||||
std::abort();
|
||||
}
|
||||
|
|
@ -527,6 +535,120 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
}
|
||||
}
|
||||
break;
|
||||
// simx64
|
||||
case R_INST_64: {
|
||||
if (func7 & 0x1){
|
||||
switch (func3) {
|
||||
case 0:
|
||||
// RV64M: MULW
|
||||
rddata[t] = sext64((WordI)rsdata[t][0] * (WordI)rsdata[t][1], 32);
|
||||
break;
|
||||
case 4: {
|
||||
// RV64M: DIVW
|
||||
int32_t dividen = (WordI) rsdata[t][0];
|
||||
int32_t divisor = (WordI) rsdata[t][1];
|
||||
if (divisor == 0){
|
||||
rddata[t] = -1;
|
||||
} else if (dividen == WordI(0x80000000) && divisor == WordI(0xFFFFFFFF)) {
|
||||
rddata[t] = sext64(dividen, 32);
|
||||
} else {
|
||||
rddata[t] = sext64(dividen / divisor, 32);
|
||||
}
|
||||
} break;
|
||||
case 5: {
|
||||
// RV64M: DIVUW
|
||||
uint32_t dividen = (Word) rsdata[0];
|
||||
uint32_t divisor = (Word) rsdata[1];
|
||||
if (divisor == 0){
|
||||
rddata[t] = -1;
|
||||
} else {
|
||||
rddata[t] = sext64(dividen / divisor, 32);
|
||||
}
|
||||
} break;
|
||||
case 6: {
|
||||
// RV64M: REMW
|
||||
int32_t dividen = (WordI) rsdata[0];
|
||||
int32_t divisor = (WordI) rsdata[1];
|
||||
if (divisor == 0){
|
||||
rddata[t] = sext64(dividen, 32);
|
||||
} else if (dividen == WordI(0x80000000) && divisor == WordI(0xFFFFFFFF)) {
|
||||
rddata[t] = 0;
|
||||
} else {
|
||||
rddata[t] = sext64(dividen % divisor, 32);
|
||||
}
|
||||
} break;
|
||||
case 7: {
|
||||
// RV64M: REMUW
|
||||
uint32_t dividen = (Word) rsdata[0];
|
||||
uint32_t divisor = (Word) rsdata[1];
|
||||
if (divisor == 0){
|
||||
rddata[t] = sext64(dividen, 32);
|
||||
} else {
|
||||
rddata[t] = sext64(dividen % divisor, 32);
|
||||
}
|
||||
} break;
|
||||
default:
|
||||
std::abort();
|
||||
}
|
||||
} else {
|
||||
switch (func3) {
|
||||
case 0:
|
||||
if (func7){
|
||||
// RV64I: SUBW
|
||||
rddata[t] = sext64((Word)rsdata[0] - (Word)rsdata[1], 32);
|
||||
}
|
||||
else{
|
||||
// RV64I: ADDW
|
||||
rddata[t] = sext64((Word)rsdata[0] + (Word)rsdata[1], 32);
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
// RV64I: SLLW
|
||||
rddata[t] = sext64((Word)rsdata[0] << (Word)rsdata[1], 32);
|
||||
break;
|
||||
case 5:
|
||||
if (func7) {
|
||||
// RV64I: SRAW
|
||||
rddata[t] = sext64((WordI)rsdata[0] >> (WordI)rsdata[1], 32);
|
||||
} else {
|
||||
// RV64I: SRLW
|
||||
rddata[t] = sext64((Word)rsdata[0] >> (Word)rsdata[1], 32);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
std::abort();
|
||||
}
|
||||
}
|
||||
rd_write = true;
|
||||
} break;
|
||||
|
||||
// simx64
|
||||
case I_INST_64: {
|
||||
switch (func3) {
|
||||
case 0:
|
||||
// RV64I: ADDIW
|
||||
rddata[t] = sext64((Word)rsdata[0] + (Word)immsrc, 32);
|
||||
break;
|
||||
case 1:
|
||||
// RV64I: SLLIW
|
||||
rddata[t] = sext64((Word)rsdata[0] << (Word)immsrc, 32);
|
||||
break;
|
||||
case 5:
|
||||
if (func7) {
|
||||
// RV64I: SRAIW
|
||||
DoubleWord result = sext64((WordI)rsdata[0] >> (WordI)immsrc, 32);
|
||||
rddata[t] = result;
|
||||
} else {
|
||||
// RV64I: SRLIW
|
||||
DoubleWord result = sext64((Word)rsdata[0] >> (Word)immsrc, 32);
|
||||
rddata[t] = result;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
std::abort();
|
||||
}
|
||||
rd_write = true;
|
||||
} break;
|
||||
case SYS_INST:
|
||||
for (int t = 0; t < num_threads; ++t) {
|
||||
if (!tmask_.test(t))
|
||||
|
|
@ -538,10 +660,10 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
trace->alu.type = AluType::SYSCALL;
|
||||
trace->fetch_stall = true;
|
||||
switch (csr_addr) {
|
||||
case 0: // ECALL
|
||||
case 0: // RV32I: ECALL
|
||||
core_->trigger_ecall();
|
||||
break;
|
||||
case 1: // EBREAK
|
||||
case 1: // RV32I: EBREAK
|
||||
core_->trigger_ebreak();
|
||||
break;
|
||||
case 0x002: // URET
|
||||
|
|
@ -556,40 +678,40 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
csr_value = core_->get_csr(csr_addr, t, id_);
|
||||
switch (func3) {
|
||||
case 1:
|
||||
// CSRRW
|
||||
// RV32I: CSRRW
|
||||
rddata[t] = csr_value;
|
||||
core_->set_csr(csr_addr, rsdata[t][0], t, id_);
|
||||
trace->used_iregs.set(rsrc0);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 2:
|
||||
// CSRRS
|
||||
// RV32I: CSRRS
|
||||
rddata[t] = csr_value;
|
||||
core_->set_csr(csr_addr, csr_value | rsdata[t][0], t, id_);
|
||||
trace->used_iregs.set(rsrc0);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 3:
|
||||
// CSRRC
|
||||
// RV32I: CSRRC
|
||||
rddata[t] = csr_value;
|
||||
core_->set_csr(csr_addr, csr_value & ~rsdata[t][0], t, id_);
|
||||
trace->used_iregs.set(rsrc0);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 5:
|
||||
// CSRRWI
|
||||
// RV32I: CSRRWI
|
||||
rddata[t] = csr_value;
|
||||
core_->set_csr(csr_addr, rsrc0, t, id_);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 6:
|
||||
// CSRRSI;
|
||||
// RV32I: CSRRSI;
|
||||
rddata[t] = csr_value;
|
||||
core_->set_csr(csr_addr, csr_value | rsrc0, t, id_);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 7:
|
||||
// CSRRCI
|
||||
// RV32I: CSRRCI
|
||||
rddata[t] = csr_value;
|
||||
core_->set_csr(csr_addr, csr_value & ~rsrc0, t, id_);
|
||||
rd_write = true;
|
||||
|
|
@ -612,80 +734,177 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
uint32_t frm = get_fpu_rm(func3, core_, t, id_);
|
||||
uint32_t fflags = 0;
|
||||
switch (func7) {
|
||||
case 0x00: //FADD
|
||||
case 0x00: // RV32F: FADD.S
|
||||
rddata[t] = rv_fadd(rsdata[t][0], rsdata[t][1], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FMA;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x04: //FSUB
|
||||
case 0x01: // RV32D: FADD.D
|
||||
rddata[t] = rv_fadd_d(rsdata[t][0], rsdata[t][1], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FMA;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x04: // RV32F: FSUB.S
|
||||
rddata[t] = rv_fsub(rsdata[t][0], rsdata[t][1], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FMA;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x08: //FMUL
|
||||
case 0x05: // RV32D: FSUB.D
|
||||
rddata[t] = rv_fsub_d(rsdata[t][0], rsdata[t][1], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FMA;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x08: // RV32F: FMUL.S
|
||||
rddata[t] = rv_fmul(rsdata[t][0], rsdata[t][1], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FMA;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x0c: //FDIV
|
||||
case 0x09: // RV32F: FMUL.D
|
||||
rddata[t] = rv_fmul_d(rsdata[t][0], rsdata[t][1], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FMA;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x0c: // RV32F: FDIV.S
|
||||
rddata[t] = rv_fdiv(rsdata[t][0], rsdata[t][1], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FDIV;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x2c: //FSQRT
|
||||
case 0x0c: // RV32F: FDIV.D
|
||||
rddata[t] = rv_fdiv_d(rsdata[t][0], rsdata[t][1], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FDIV;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x2c: // RV32F: FSQRT.S
|
||||
rddata[t] = rv_fsqrt(rsdata[t][0], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FSQRT;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
break;
|
||||
break;
|
||||
case 0x2d: // RV32D: FSQRT.D
|
||||
rddata[t] = rv_fsqrt_d(rsdata[t][0], frm, &fflags);
|
||||
trace->fpu.type = FpuType::FSQRT;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
break;
|
||||
case 0x10:
|
||||
switch (func3) {
|
||||
case 0: // FSGNJ.S
|
||||
case 0: // RV32F: FSGNJ.S
|
||||
rddata[t] = rv_fsgnj(rsdata[t][0], rsdata[t][1]);
|
||||
break;
|
||||
case 1: // FSGNJN.S
|
||||
case 1: // RV32F: FSGNJN.S
|
||||
rddata[t] = rv_fsgnjn(rsdata[t][0], rsdata[t][1]);
|
||||
break;
|
||||
case 2: // FSGNJX.S
|
||||
case 2: // RV32F: FSGNJX.S
|
||||
rddata[t] = rv_fsgnjx(rsdata[t][0], rsdata[t][1]);
|
||||
break;
|
||||
}
|
||||
case 0x11:
|
||||
switch (func3) {
|
||||
case 0: // RV32F: FSGNJ.D
|
||||
rddata[t] = rv_fsgnj_d(rsdata[t][0], rsdata[t][1]);
|
||||
break;
|
||||
case 1: // RV32F: FSGNJN.D
|
||||
rddata[t] = rv_fsgnjn_d(rsdata[t][0], rsdata[t][1]);
|
||||
break;
|
||||
case 2: // RV32F: FSGNJX.D
|
||||
rddata[t] = rv_fsgnjx_d(rsdata[t][0], rsdata[t][1]);
|
||||
break;
|
||||
}
|
||||
trace->fpu.type = FpuType::FNCP;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x14:
|
||||
if (func3) {
|
||||
// FMAX.S
|
||||
// RV32F: FMAX.S
|
||||
rddata[t] = rv_fmax(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
} else {
|
||||
// FMIN.S
|
||||
// RV32F: FMIN.S
|
||||
rddata[t] = rv_fmin(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
}
|
||||
trace->fpu.type = FpuType::FNCP;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x60:
|
||||
if (rsrc1 == 0) {
|
||||
// FCVT.W.S
|
||||
rddata[t] = rv_ftoi(rsdata[t][0], frm, &fflags);
|
||||
case 0x15:
|
||||
if (func3) {
|
||||
// RV32D: FMAX.D
|
||||
rddata[t] = rv_fmax_d(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
} else {
|
||||
// FCVT.WU.S
|
||||
rddata[t] = rv_ftou(rsdata[t][0], frm, &fflags);
|
||||
// RV32D: FMIN.D
|
||||
rddata[t] = rv_fmin_d(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
}
|
||||
trace->fpu.type = FpuType::FNCP;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x60:
|
||||
switch(rsrc1) {
|
||||
case 0:
|
||||
// RV32F: FCVT.W.S
|
||||
rddata[t] = sext64(rv_ftoi(rsdata[0], frm, &fflags), 32);
|
||||
break;
|
||||
case 1:
|
||||
// RV32F: FCVT.WU.S
|
||||
rddata[t] = sext64(rv_ftou(rsdata[0], frm, &fflags), 32);
|
||||
break;
|
||||
case 2:
|
||||
// RV64F: FCVT.L.S
|
||||
rddata[t] = rv_ftol(rsdata[0], frm, &fflags);
|
||||
break;
|
||||
case 3:
|
||||
// RV64F: FCVT.LU.S
|
||||
rddata[t] = rv_ftolu(rsdata[0], frm, &fflags);
|
||||
break;
|
||||
}
|
||||
trace->fpu.type = FpuType::FCVT;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
break;
|
||||
case 0x61:
|
||||
switch(rsrc1) {
|
||||
case 0:
|
||||
// RV32F: FCVT.W.D
|
||||
rddata[t] = sext64(rv_ftoi_d(rsdata[0], frm, &fflags), 32);
|
||||
break;
|
||||
case 1:
|
||||
// RV32F: FCVT.WU.D
|
||||
rddata[t] = sext64(rv_ftou_d(rsdata[0], frm, &fflags), 32);
|
||||
break;
|
||||
case 2:
|
||||
// RV64F: FCVT.L.D
|
||||
rddata[t] = rv_ftol_d(rsdata[0], frm, &fflags);
|
||||
break;
|
||||
case 3:
|
||||
// RV64F: FCVT.LU.D
|
||||
rddata[t] = rv_ftolu_d(rsdata[0], frm, &fflags);
|
||||
break;
|
||||
}
|
||||
trace->fpu.type = FpuType::FCVT;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
break;
|
||||
case 0x70:
|
||||
if (func3) {
|
||||
// FCLASS.S
|
||||
// RV32F: FCLASS.S
|
||||
rddata[t] = rv_fclss(rsdata[t][0]);
|
||||
} else {
|
||||
// FMV.X.W
|
||||
// RV32F: FMV.X.W
|
||||
rddata[t] = rsdata[t][0];
|
||||
}
|
||||
trace->fpu.type = FpuType::FNCP;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
break;
|
||||
case 0x71:
|
||||
if (func3) {
|
||||
// RV32D: FCLASS.S
|
||||
rddata[t] = rv_fclss_d(rsdata[t][0]);
|
||||
} else {
|
||||
// RV64D: FMV.X.D
|
||||
rddata[t] = rsdata[t][0];
|
||||
}
|
||||
trace->fpu.type = FpuType::FNCP;
|
||||
|
|
@ -694,35 +913,87 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
case 0x50:
|
||||
switch(func3) {
|
||||
case 0:
|
||||
// FLE.S
|
||||
// RV32F: FLE.S
|
||||
rddata[t] = rv_fle(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
break;
|
||||
case 1:
|
||||
// FLT.S
|
||||
// RV32F: FLT.S
|
||||
rddata[t] = rv_flt(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
break;
|
||||
case 2:
|
||||
// FEQ.S
|
||||
// RV32F: FEQ.S
|
||||
rddata[t] = rv_feq(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
break;
|
||||
}
|
||||
trace->fpu.type = FpuType::FNCP;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x51:
|
||||
switch(func3) {
|
||||
case 0:
|
||||
// RV32D: FLE.D
|
||||
rddata[t] = rv_fle_d(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
break;
|
||||
case 1:
|
||||
// RV32D: FLT.D
|
||||
rddata[t] = rv_flt_d(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
break;
|
||||
case 2:
|
||||
// RV32D: FEQ.D
|
||||
rddata[t] = rv_feq_d(rsdata[t][0], rsdata[t][1], &fflags);
|
||||
break;
|
||||
}
|
||||
trace->fpu.type = FpuType::FNCP;
|
||||
trace->used_fregs.set(rsrc0);
|
||||
trace->used_fregs.set(rsrc1);
|
||||
break;
|
||||
case 0x68:
|
||||
if (rsrc1) {
|
||||
// FCVT.S.WU:
|
||||
rddata[t] = rv_utof(rsdata[t][0], frm, &fflags);
|
||||
} else {
|
||||
// FCVT.S.W:
|
||||
rddata[t] = rv_itof(rsdata[t][0], frm, &fflags);
|
||||
switch(rsrc1) {
|
||||
case 0:
|
||||
// RV32F: FCVT.S.W
|
||||
rddata[t] = rv_itof(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 1:
|
||||
// RV32F: FCVT.S.WU
|
||||
rddata[t] = rv_utof(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 2:
|
||||
// RV64F: FCVT.S.L
|
||||
rddata[t] = rv_ltof(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 3:
|
||||
// RV64F: FCVT.S.LU
|
||||
rddata[t] = rv_lutof(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
}
|
||||
trace->fpu.type = FpuType::FCVT;
|
||||
trace->used_iregs.set(rsrc0);
|
||||
break;
|
||||
case 0x78:
|
||||
// FMV.W.X
|
||||
case 0x69:
|
||||
switch(rsrc1) {
|
||||
case 0:
|
||||
// RV32D: FCVT.D.W
|
||||
rddata[t] = rv_itof_d(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 1:
|
||||
// RV32F: FCVT.D.WU
|
||||
rddata[t] = rv_utof_d(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 2:
|
||||
// RV64D: FCVT.D.L
|
||||
rddata[t] = rv_ltof_d(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
case 3:
|
||||
// RV64D: FCVT.D.LU
|
||||
rddata[t] = rv_lutof_d(rsdata[t][0], frm, &fflags);
|
||||
break;
|
||||
}
|
||||
trace->fpu.type = FpuType::FCVT;
|
||||
trace->used_iregs.set(rsrc0);
|
||||
break;
|
||||
case 0x78: // FMV.W.X
|
||||
case 0x79: // FMV.D.X
|
||||
rddata[t] = rsdata[t][0];
|
||||
trace->fpu.type = FpuType::FNCP;
|
||||
trace->used_iregs.set(rsrc0);
|
||||
|
|
@ -747,16 +1018,36 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
Word fflags = 0;
|
||||
switch (opcode) {
|
||||
case FMADD:
|
||||
rddata[t] = rv_fmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
if (func2)
|
||||
// RV32D: FMADD.D
|
||||
rddata[t] = rv_fmadd_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
else
|
||||
// RV32F: FMADD.S
|
||||
rddata[t] = rv_fmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
case FMSUB:
|
||||
rddata[t] = rv_fmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
if (func2)
|
||||
// RV32D: FMSUB.D
|
||||
rddata[t] = rv_fmsub_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
else
|
||||
// RV32F: FMSUB.S
|
||||
rddata[t] = rv_fmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
case FMNMADD:
|
||||
rddata[t] = rv_fnmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
if (func2)
|
||||
// RV32D: FNMADD.D
|
||||
rddata[t] = rv_fnmadd_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
else
|
||||
// RV32F: FNMADD.S
|
||||
rddata[t] = rv_fnmadd(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
case FMNMSUB:
|
||||
rddata[t] = rv_fnmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
if (func2)
|
||||
// RV32D: FNMSUB.D
|
||||
rddata[t] = rv_fnmsub_d(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
else
|
||||
// RV32F: FNMSUB.S
|
||||
rddata[t] = rv_fnmsub(rsdata[t][0], rsdata[t][1], rsdata[t][2], frm, &fflags);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
@ -1832,7 +2123,7 @@ void Warp::execute(const Instr &instr, pipeline_trace_t *trace) {
|
|||
}
|
||||
}
|
||||
|
||||
PC_ += core_->arch().wsize();
|
||||
PC_ += 4;
|
||||
if (PC_ != nextPC) {
|
||||
DP(3, "*** Next PC: " << std::hex << nextPC << std::dec);
|
||||
PC_ = nextPC;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue