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bram block optimization

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This commit is contained in:
Blaise Tine 2021-08-13 19:31:55 -07:00
parent 4336dcb2a8
commit 646371f9e9
9 changed files with 56 additions and 110 deletions
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6
hw/rtl/VX_icache_stage.v
View file

@ -41,10 +41,8 @@ module VX_icache_stage #(
.waddr(req_tag),
.raddr(rsp_tag),
.wren(icache_req_fire),
.byteen(1'b1),
.rden(ifetch_rsp_if.valid),
.din({ifetch_req_if.PC, ifetch_req_if.tmask}),
.dout({rsp_PC, rsp_tmask})
.din({ifetch_req_if.PC, ifetch_req_if.tmask}),
.dout({rsp_PC, rsp_tmask})
);
`RUNTIME_ASSERT((!ifetch_req_if.valid || ifetch_req_if.PC >= `STARTUP_ADDR), ("invalid PC=%0h", ifetch_req_if.PC))

2
hw/rtl/VX_ipdom_stack.v
View file

@ -47,8 +47,6 @@ module VX_ipdom_stack #(
.waddr(wr_ptr),
.raddr(rd_ptr),
.wren(push),
.byteen(1'b1),
.rden(pop),
.din({q2, q1}),
.dout({d2, d1})
);

4
hw/rtl/cache/VX_data_access.v vendored
View file

@ -70,9 +70,7 @@ module VX_data_access #(
) data_store (
.clk(clk),
.addr(line_addr),
.wren(writeen),
.byteen(byte_enable),
.rden(1'b1),
.wren({BYTEENW{writeen}} & byte_enable),
.din(wdata),
.dout(rdata)
);

2
hw/rtl/cache/VX_miss_resrv.v vendored
View file

@ -180,8 +180,6 @@ module VX_miss_resrv #(
.waddr (allocate_id_r),
.raddr (dequeue_id_r),
.wren (allocate_valid),
.byteen (1'b1),
.rden (1'b1),
.din (allocate_data),
.dout (dequeue_data)
);

6
hw/rtl/cache/VX_tag_access.v vendored
View file

@ -53,16 +53,14 @@ module VX_tag_access #(
) tag_store (
.clk(clk),
.addr(line_addr),
.wren(fill && ~stall),
.byteen(1'b1),
.rden(1'b1),
.wren(fill),
.din({!is_flush, line_tag}),
.dout({read_valid, read_tag})
);
assign tag_match = read_valid && (line_tag == read_tag);
`RUNTIME_ASSERT((~(fill && ~stall && ~is_flush) || ~tag_match), ("%t: redundant fill - addr=%0h, tag_id=%0h", $time, `LINE_TO_BYTE_ADDR(addr, BANK_ID), read_tag))
`UNUSED_VAR (stall)
`ifdef DBG_PRINT_CACHE_TAG
always @(posedge clk) begin

70
hw/rtl/libs/VX_dp_ram.v
View file

@ -14,9 +14,7 @@ module VX_dp_ram #(
input wire clk,
input wire [ADDRW-1:0] waddr,
input wire [ADDRW-1:0] raddr,
input wire wren,
input wire [BYTEENW-1:0] byteen,
input wire rden,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
);
@ -35,14 +33,11 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
if (rden)
dout_r <= mem[raddr];
dout_r <= mem[raddr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
@ -52,16 +47,13 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
if (rden)
dout_r <= mem[raddr];
dout_r <= mem[raddr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
@ -70,11 +62,9 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[raddr];
@ -86,7 +76,7 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
end
assign dout = mem[raddr];
@ -104,14 +94,11 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
if (rden)
dout_r <= mem[raddr];
dout_r <= mem[raddr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
@ -121,16 +108,13 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
if (rden)
dout_r <= mem[raddr];
dout_r <= mem[raddr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
@ -140,11 +124,9 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[raddr];
@ -156,7 +138,7 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
end
assign dout = mem[raddr];
@ -170,11 +152,9 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[waddr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[raddr];
@ -186,7 +166,7 @@ module VX_dp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[waddr] <= din;
end
assign dout = mem[raddr];

4
hw/rtl/libs/VX_fifo_queue.v
View file

@ -164,8 +164,6 @@ module VX_fifo_queue #(
.waddr(wr_ptr_r),
.raddr(rd_ptr_r),
.wren(push),
.byteen(1'b1),
.rden(1'b1),
.din(data_in),
.dout(data_out)
);
@ -209,8 +207,6 @@ module VX_fifo_queue #(
.waddr(wr_ptr_r),
.raddr(rd_ptr_n_r),
.wren(push),
.byteen(1'b1),
.rden(1'b1),
.din(data_in),
.dout(dout)
);

2
hw/rtl/libs/VX_index_buffer.v
View file

@ -78,8 +78,6 @@ module VX_index_buffer #(
.waddr(write_addr),
.raddr(read_addr),
.wren(acquire_slot),
.byteen(1'b1),
.rden(1'b1),
.din(write_data),
.dout(read_data)
);

70
hw/rtl/libs/VX_sp_ram.v
View file

@ -13,9 +13,7 @@ module VX_sp_ram #(
) (
input wire clk,
input wire [ADDRW-1:0] addr,
input wire wren,
input wire [BYTEENW-1:0] byteen,
input wire rden,
input wire [BYTEENW-1:0] wren,
input wire [DATAW-1:0] din,
output wire [DATAW-1:0] dout
);
@ -34,14 +32,11 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
if (rden)
dout_r <= mem[addr];
dout_r <= mem[addr];
end
end else begin
`USE_FAST_BRAM reg [DATAW-1:0] mem [SIZE-1:0];
@ -51,15 +46,13 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
if (rden)
dout_r <= mem[addr];
dout_r <= mem[addr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (BYTEENW > 1) begin
`USE_FAST_BRAM reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
@ -68,11 +61,9 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[addr];
@ -84,7 +75,7 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
end
assign dout = mem[addr];
@ -102,14 +93,11 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
if (rden)
dout_r <= mem[addr];
dout_r <= mem[addr];
end
end else begin
reg [DATAW-1:0] mem [SIZE-1:0];
@ -119,15 +107,13 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
if (rden)
dout_r <= mem[addr];
dout_r <= mem[addr];
end
end
assign dout = dout_r;
end else begin
`UNUSED_VAR (rden)
if (RWCHECK) begin
if (BYTEENW > 1) begin
reg [BYTEENW-1:0][7:0] mem [SIZE-1:0];
@ -137,11 +123,9 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[addr];
@ -153,7 +137,7 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
end
assign dout = mem[addr];
@ -166,12 +150,10 @@ module VX_sp_ram #(
initial mem = '{default: 0};
end
always @(posedge clk) begin
if (wren) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (byteen[i])
mem[addr][i] <= din[i * 8 +: 8];
end
always @(posedge clk) begin
for (integer i = 0; i < BYTEENW; i++) begin
if (wren[i])
mem[addr][i] <= din[i * 8 +: 8];
end
end
assign dout = mem[addr];
@ -183,7 +165,7 @@ module VX_sp_ram #(
end
always @(posedge clk) begin
if (wren && byteen)
if (wren)
mem[addr] <= din;
end
assign dout = mem[addr];