mirror of
https://github.com/vortexgpgpu/vortex.git
synced 2025-04-23 21:39:10 -04:00
Added support for RV64I instructions
This commit is contained in:
Santosh Raghav Srivatsan
parent
d1892bd6ec
commit
64d47f3637
9 changed files with 125 additions and 79 deletions
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@ -1,6 +1,6 @@
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RISCV_TOOLCHAIN_PATH ?= /opt/riscv-gnu-toolchain
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# simx64
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RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv64-unknown-elf-toolchain
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RISCV64_TOOLCHAIN_PATH ?= /nethome/ssrivatsan8/riscv
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CC = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc
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@ -8,7 +8,7 @@ AR = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-gcc-ar
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DP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objdump
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CP = $(RISCV64_TOOLCHAIN_PATH)/bin/riscv64-unknown-elf-objcopy
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CFLAGS += -O3 -march=rv64imfd -mabi=lp64d -Wstack-usage=1024 -fno-exceptions -fdata-sections -ffunction-sections
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CFLAGS += -O3 -march=rv64i -mabi=lp64 -Wstack-usage=1024 -fno-exceptions -fdata-sections -ffunction-sections
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CFLAGS += -I./include -I../hw
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PROJECT = libvortexrt
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@ -22,7 +22,14 @@ inline uint64_t align_size(uint64_t size, uint64_t alignment) {
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}
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// Apply integer sign extension
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inline uint32_t signExt(uint32_t w, uint32_t bit, uint32_t mask) {
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inline uint64_t signExt(uint64_t w, uint64_t bit, uint64_t mask) {
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if (w >> (bit - 1))
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w |= ~mask;
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return w;
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}
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// Apply integer sign extension
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inline uint32_t signExt32(uint32_t w, uint32_t bit, uint32_t mask) {
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if (w >> (bit - 1))
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w |= ~mask;
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return w;
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@ -14,8 +14,9 @@ public:
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ArchDef(const std::string &/*arch*/,
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int num_cores,
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int num_warps,
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int num_threads) {
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wsize_ = 4;
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int num_threads) {
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// simx64
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wsize_ = 8;
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vsize_ = 16;
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num_regs_ = 32;
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num_csrs_ = 4096;
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@ -107,8 +107,12 @@ static const char* op_string(const Instr &instr) {
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case 0: return "LBI";
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case 1: return "LHI";
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case 2: return "LW";
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// simx64
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case 3: return "LD";
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case 4: return "LBU";
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case 5: return "LHU";
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// simx64
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case 6: return "LWU";
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default:
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std::abort();
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}
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@ -117,6 +121,8 @@ static const char* op_string(const Instr &instr) {
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case 0: return "SB";
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case 1: return "SH";
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case 2: return "SW";
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// simx64
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case 3: return "SD";
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default:
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std::abort();
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}
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@ -301,7 +307,7 @@ Decoder::Decoder(const ArchDef &arch) {
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v_imm_mask_ = 0x7ff;
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}
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std::shared_ptr<Instr> Decoder::decode(Word code, Word PC) {
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std::shared_ptr<Instr> Decoder::decode(uint32_t code, uint32_t PC) {
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auto instr = std::make_shared<Instr>();
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Opcode op = (Opcode)((code >> shift_opcode_) & opcode_mask_);
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instr->setOpcode(op);
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@ -310,10 +316,11 @@ std::shared_ptr<Instr> Decoder::decode(Word code, Word PC) {
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Word func6 = (code >> shift_func6_) & func6_mask_;
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Word func7 = (code >> shift_func7_) & func7_mask_;
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int rd = (code >> shift_rd_) & reg_mask_;
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int rs1 = (code >> shift_rs1_) & reg_mask_;
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int rs2 = (code >> shift_rs2_) & reg_mask_;
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int rs3 = (code >> shift_rs3_) & reg_mask_;
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// simx64
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long rd = (code >> shift_rd_) & reg_mask_;
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long rs1 = (code >> shift_rs1_) & reg_mask_;
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long rs2 = (code >> shift_rs2_) & reg_mask_;
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long rs3 = (code >> shift_rs3_) & reg_mask_;
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auto op_it = sc_instTable.find(op);
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if (op_it == sc_instTable.end()) {
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@ -371,7 +378,7 @@ std::shared_ptr<Instr> Decoder::decode(Word code, Word PC) {
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instr->setFunc3(func3);
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instr->setFunc7(func7);
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if ((func3 == 5) && (op != L_INST) && (op != Opcode::FL)) {
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instr->setImm(signExt(rs2, 5, reg_mask_));
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instr->setImm(signExt(rs2, 6, 0x3F));
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} else {
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instr->setImm(signExt(code >> shift_rs2_, 12, i_imm_mask_));
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}
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@ -13,7 +13,7 @@ class Decoder {
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public:
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Decoder(const ArchDef &);
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std::shared_ptr<Instr> decode(Word code, Word PC);
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std::shared_ptr<Instr> decode(uint32_t code, uint32_t PC);
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private:
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@ -16,7 +16,7 @@
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using namespace vortex;
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static bool HasDivergentThreads(const ThreadMask &thread_mask,
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const std::vector<std::vector<DoubleWord>> ®_file,
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const std::vector<std::vector<Word>> ®_file,
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unsigned reg) {
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bool cond;
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size_t thread_idx = 0;
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@ -109,7 +109,8 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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rd_write = true;
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break;
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case AUIPC_INST:
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rddata = ((immsrc << 12) & 0xfffff000) + PC_;
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// simx64
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rddata = signExt(((immsrc << 12) & 0xfffff000), 32, 0xFFFFFFFF) + PC_;
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rd_write = true;
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break;
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case R_INST: {
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@ -199,8 +200,10 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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switch (func3) {
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case 0:
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if (func7) {
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// RV32I: SUB
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rddata = rsdata[0] - rsdata[1];
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} else {
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// RV32I: ADD
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rddata = rsdata[0] + rsdata[1];
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}
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break;
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@ -211,25 +214,32 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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rddata = rsdata[0] << rsdata[1];
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break;
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case 2:
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// RV32I: SLT (signed)
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rddata = (WordI(rsdata[0]) < WordI(rsdata[1]));
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break;
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case 3:
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// RV32I: SLTU (unsigned)
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rddata = (Word(rsdata[0]) < Word(rsdata[1]));
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break;
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case 4:
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// RV32I: XOR
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rddata = rsdata[0] ^ rsdata[1];
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break;
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case 5:
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if (func7) {
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// RV32I: SRA
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rddata = WordI(rsdata[0]) >> WordI(rsdata[1]);
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} else {
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// RV32I: SRL
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rddata = Word(rsdata[0]) >> Word(rsdata[1]);
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}
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break;
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case 6:
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// RV32I: OR
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rddata = rsdata[0] | rsdata[1];
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break;
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case 7:
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// RV32I: AND
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rddata = rsdata[0] & rsdata[1];
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break;
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default:
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@ -241,42 +251,42 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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case I_INST:
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switch (func3) {
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case 0:
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// ADDI
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// RV32I: ADDI
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rddata = rsdata[0] + immsrc;
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break;
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case 1:
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// SLLI
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// RV64I: SLLI
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rddata = rsdata[0] << immsrc;
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break;
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case 2:
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// SLTI
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// RV32I: SLTI
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rddata = (WordI(rsdata[0]) < WordI(immsrc));
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break;
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case 3: {
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// SLTIU
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// RV32I: SLTIU
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rddata = (Word(rsdata[0]) < Word(immsrc));
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} break;
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case 4:
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// XORI
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// RV32I: XORI
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rddata = rsdata[0] ^ immsrc;
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break;
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case 5:
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if (func7) {
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// SRAI
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// RV64I: SRAI
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Word result = WordI(rsdata[0]) >> immsrc;
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rddata = result;
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} else {
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// SRLI
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// RV64I: SRLI
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Word result = Word(rsdata[0]) >> immsrc;
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rddata = result;
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}
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break;
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case 6:
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// ORI
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// RV32I: ORI
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rddata = rsdata[0] | immsrc;
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break;
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case 7:
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// ANDI
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// RV32I: ANDI
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rddata = rsdata[0] & immsrc;
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break;
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default:
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@ -287,37 +297,37 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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case B_INST:
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switch (func3) {
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case 0:
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// BEQ
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// RV32I: BEQ
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if (rsdata[0] == rsdata[1]) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 1:
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// BNE
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// RV32I: BNE
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if (rsdata[0] != rsdata[1]) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 4:
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// BLT
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// RV32I: BLT
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if (WordI(rsdata[0]) < WordI(rsdata[1])) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 5:
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// BGE
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// RV32I: BGE
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if (WordI(rsdata[0]) >= WordI(rsdata[1])) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 6:
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// BLTU
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// RV32I: BLTU
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if (Word(rsdata[0]) < Word(rsdata[1])) {
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nextPC = PC_ + immsrc;
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}
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break;
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case 7:
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// BGEU
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// RV32I: BGEU
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if (Word(rsdata[0]) >= Word(rsdata[1])) {
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nextPC = PC_ + immsrc;
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}
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@ -326,6 +336,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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pipeline->stall_warp = true;
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runOnce = true;
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break;
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// RV32I: JAL
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case JAL_INST:
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rddata = nextPC;
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nextPC = PC_ + immsrc;
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@ -333,9 +344,10 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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runOnce = true;
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rd_write = true;
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break;
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// RV32I: JALR
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case JALR_INST:
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rddata = nextPC;
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nextPC = rsdata[0] + immsrc;
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nextPC = HalfWord(rsdata[0]) + HalfWord(immsrc);
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pipeline->stall_warp = true;
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runOnce = true;
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rd_write = true;
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@ -343,29 +355,37 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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case L_INST: {
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Word memAddr = ((rsdata[0] + immsrc) & 0xFFFFFFFC); // word aligned
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Word shift_by = ((rsdata[0] + immsrc) & 0x00000003) * 8;
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Word data_read = core_->dcache_read(memAddr, 4);
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Word data_read = core_->dcache_read(memAddr, 8);
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D(3, "LOAD MEM: ADDRESS=0x" << std::hex << memAddr << ", DATA=0x" << data_read);
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switch (func3) {
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case 0:
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// LBI
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// RV32I: LBI
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rddata = signExt((data_read >> shift_by) & 0xFF, 8, 0xFF);
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break;
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case 1:
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// LHI
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// RV32I: LHI
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rddata = signExt((data_read >> shift_by) & 0xFFFF, 16, 0xFFFF);
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break;
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case 2:
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// LW
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// RV32I: LW
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rddata = signExt((data_read >> shift_by) & 0xFFFFFFFF, 32, 0xFFFFFFFF);
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break;
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case 3:
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// RV64I: LD
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rddata = data_read;
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break;
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case 4:
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// LBU
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// RV32I: LBU
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rddata = Word((data_read >> shift_by) & 0xFF);
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break;
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case 5:
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// LHU
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// RV32I: LHU
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rddata = Word((data_read >> shift_by) & 0xFFFF);
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break;
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case 6:
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// RV64I: LWU
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rddata = Word((data_read >> shift_by) & 0xFFFFFFFF);
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break;
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default:
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std::abort();
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}
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@ -376,16 +396,20 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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D(3, "STORE MEM: ADDRESS=0x" << std::hex << memAddr);
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switch (func3) {
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case 0:
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// SB
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// RV32I: SB
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core_->dcache_write(memAddr, rsdata[1] & 0x000000FF, 1);
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break;
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case 1:
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// SH
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core_->dcache_write(memAddr, rsdata[1], 2);
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// RV32I: SH
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core_->dcache_write(memAddr, rsdata[1] & 0x0000FFFF, 2);
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break;
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case 2:
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// SW
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core_->dcache_write(memAddr, rsdata[1], 4);
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// RV32I: SW
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core_->dcache_write(memAddr, rsdata[1] & 0xFFFFFFFF, 4);
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break;
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case 3:
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// RV64I: SD
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core_ ->dcache_write(memAddr, rsdata[1], 8);
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break;
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default:
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std::abort();
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@ -396,65 +420,68 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
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switch (func3) {
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case 0:
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if (func7){
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// SUBW
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rddata = DoubleWord(rsdata[0] - rsdata[1]);
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// RV64I: SUBW
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rddata = signExt((HalfWord)rsdata[0] - (HalfWord)rsdata[1], 32, 0xFFFFFFFF);
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}
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else{
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// ADDW
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rddata = DoubleWord(rsdata[0] + rsdata[1]);
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// RV64I: ADDW
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rddata = signExt((HalfWord)rsdata[0] + (HalfWord)rsdata[1], 32, 0xFFFFFFFF);
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}
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break;
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case 1:
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// SLLW
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// RV64I: SLLW
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// shift amount given by rs2[4:0]
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rddata = DoubleWord(rsdata[0] << rsdata[1]);
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rddata = signExt((HalfWord)rsdata[0] << (HalfWord)rsdata[1], 32, 0xFFFFFFFF);
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break;
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case 5:
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if (func7) {
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// SRAW
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// RV64I: SRAW
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// shift amount given by rs2[4:0]
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rddata = DoubleWord(WordI(rsdata[0]) >> WordI(rsdata[1]));
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rddata = signExt((HalfWordI)rsdata[0] >> (HalfWordI)rsdata[1], 32, 0xFFFFFFFF);
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} else {
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// SRLW
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// RV64I: SRLW
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// shift amount given by rs2[4:0]
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rddata = DoubleWord(Word(rsdata[0]) >> Word(rsdata[1]));
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rddata = signExt((HalfWord)rsdata[0] >> (HalfWord)rsdata[1], 32, 0xFFFFFFFF);
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}
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break;
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default:
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std::abort();
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}
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rd_write = true;
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} break;
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// simx64
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case I_INST_64: {
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switch (func3) {
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case 0:
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// ADDIW
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rddata = DoubleWord(rsdata[0] + immsrc);
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// RV64I: ADDIW
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rddata = signExt((HalfWord)rsdata[0] + (HalfWord)immsrc, 32, 0xFFFFFFFF);
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printf("rddata\n");
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break;
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case 1:
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// SLLIW
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// RV64I: SLLIW
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// rs1 shifted by lower 5 bits of imm
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// Illegal exception if imm[5] != 0
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rddata = DoubleWord(rsdata[0] << immsrc);
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rddata = signExt((HalfWord)rsdata[0] << (HalfWord)immsrc, 32, 0xFFFFFFFF);
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break;
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case 5:
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if (func7) {
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// SRAI
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// RV64I: SRAI
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// rs1 shifted by lower 5 bits of imm
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// Illegal exception if imm[5] != 0
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Word result = DoubleWord(WordI(rsdata[0]) >> immsrc);
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Word result = signExt((HalfWordI)rsdata[0] >> (HalfWordI)immsrc, 32, 0xFFFFFFFF);
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rddata = result;
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} else {
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// SRLI
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// RV64I: SRLI
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// rs1 shifted by lower 5 bits of imm
|
||||
// Illegal exception if imm[5] != 0
|
||||
Word result = DoubleWord(Word(rsdata[0]) >> immsrc);
|
||||
Word result = signExt((HalfWord)rsdata[0] >> (HalfWord)immsrc, 32, 0xFFFFFFFF);
|
||||
rddata = result;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
std::abort();
|
||||
}
|
||||
rd_write = true;
|
||||
} break;
|
||||
case SYS_INST: {
|
||||
Word csr_addr = immsrc & 0x00000FFF;
|
||||
|
|
@ -467,37 +494,37 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
|
|||
}
|
||||
break;
|
||||
case 1:
|
||||
// CSRRW
|
||||
// RV32I: CSRRW
|
||||
rddata = csr_value;
|
||||
core_->set_csr(csr_addr, rsdata[0], t, id_);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 2:
|
||||
// CSRRS
|
||||
// RV32I: CSRRS
|
||||
rddata = csr_value;
|
||||
core_->set_csr(csr_addr, csr_value | rsdata[0], t, id_);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 3:
|
||||
// CSRRC
|
||||
// RV32I: CSRRC
|
||||
rddata = csr_value;
|
||||
core_->set_csr(csr_addr, csr_value & ~rsdata[0], t, id_);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 5:
|
||||
// CSRRWI
|
||||
// RV32I: CSRRWI
|
||||
rddata = csr_value;
|
||||
core_->set_csr(csr_addr, rsrc0, t, id_);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 6:
|
||||
// CSRRSI
|
||||
// RV32I: CSRRSI
|
||||
rddata = csr_value;
|
||||
core_->set_csr(csr_addr, csr_value | rsrc0, t, id_);
|
||||
rd_write = true;
|
||||
break;
|
||||
case 7:
|
||||
// CSRRCI
|
||||
// RV32I: CSRRCI
|
||||
rddata = csr_value;
|
||||
core_->set_csr(csr_addr, csr_value & ~rsrc0, t, id_);
|
||||
rd_write = true;
|
||||
|
|
@ -506,6 +533,7 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
|
|||
break;
|
||||
}
|
||||
} break;
|
||||
// RV32I: FENCE
|
||||
case FENCE:
|
||||
pipeline->stall_warp = true;
|
||||
runOnce = true;
|
||||
|
|
@ -661,20 +689,21 @@ void Warp::execute(const Instr &instr, Pipeline *pipeline) {
|
|||
case FMSUB:
|
||||
case FMNMADD:
|
||||
case FMNMSUB: {
|
||||
int frm = get_fpu_rm(func3, core_, t, id_);
|
||||
// int frm = get_fpu_rm(func3, core_, t, id_);
|
||||
// simx64
|
||||
Word fflags = 0;
|
||||
switch (opcode) {
|
||||
case FMADD:
|
||||
rddata = rv_fmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
||||
// rddata = rv_fmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
||||
break;
|
||||
case FMSUB:
|
||||
rddata = rv_fmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
||||
// rddata = rv_fmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
||||
break;
|
||||
case FMNMADD:
|
||||
rddata = rv_fnmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
||||
// rddata = rv_fnmadd(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
||||
break;
|
||||
case FMNMSUB:
|
||||
rddata = rv_fnmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
||||
// rddata = rv_fnmsub(rsdata[0], rsdata[1], rsdata[2], frm, &fflags);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -7,13 +7,15 @@
|
|||
namespace vortex {
|
||||
|
||||
typedef uint8_t Byte;
|
||||
typedef uint32_t Word;
|
||||
typedef int32_t WordI;
|
||||
// simx64
|
||||
typedef uint64_t DoubleWord;
|
||||
typedef uint64_t Word;
|
||||
typedef int64_t WordI;
|
||||
|
||||
// simx64
|
||||
typedef uint64_t Addr;
|
||||
typedef uint32_t HalfWord;
|
||||
typedef int32_t HalfWordI;
|
||||
|
||||
// simx64
|
||||
typedef uint32_t Addr;
|
||||
typedef uint32_t Size;
|
||||
|
||||
typedef std::bitset<32> RegMask;
|
||||
|
|
|
|||
|
|
@ -14,8 +14,8 @@ Warp::Warp(Core *core, Word id)
|
|||
: id_(id)
|
||||
, core_(core) {
|
||||
// simx64
|
||||
iRegFile_.resize(core_->arch().num_threads(), std::vector<DoubleWord>(core_->arch().num_regs(), 0));
|
||||
fRegFile_.resize(core_->arch().num_threads(), std::vector<DoubleWord>(core_->arch().num_regs(), 0));
|
||||
iRegFile_.resize(core_->arch().num_threads(), std::vector<Word>(core_->arch().num_regs(), 0));
|
||||
fRegFile_.resize(core_->arch().num_threads(), std::vector<Word>(core_->arch().num_regs(), 0));
|
||||
vRegFile_.resize(core_->arch().num_regs(), std::vector<Byte>(core_->arch().vsize(), 0));
|
||||
this->clear();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -99,8 +99,8 @@ private:
|
|||
ThreadMask tmask_;
|
||||
|
||||
// simx64
|
||||
std::vector<std::vector<DoubleWord>> iRegFile_;
|
||||
std::vector<std::vector<DoubleWord>> fRegFile_;
|
||||
std::vector<std::vector<Word>> iRegFile_;
|
||||
std::vector<std::vector<Word>> fRegFile_;
|
||||
std::vector<std::vector<Byte>> vRegFile_;
|
||||
std::stack<DomStackEntry> domStack_;
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue