github-mirrors/vortex
1
0
Fork 0
mirror of https://github.com/vortexgpgpu/vortex.git synced 2025-04-23 21:39:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

minor update

Browse source
This commit is contained in:
Blaise Tine 2023-06-26 17:34:10 -04:00
parent 74737b1fd3
commit 64e4481d82
5 changed files with 55 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

24
hw/rtl/cache/VX_cache_bank.sv vendored
View file

@ -406,6 +406,18 @@ module VX_cache_bank #(
.lkp_req_uuid (req_uuid_st0),
.rel_req_uuid (req_uuid_st1),
// fill
.fill_valid (mem_rsp_fire),
.fill_id (mem_rsp_id),
.fill_addr (mem_rsp_addr),
// dequeue
.dequeue_valid (mshr_deq_valid),
.dequeue_id (mshr_deq_id),
.dequeue_addr (mshr_deq_addr),
.dequeue_data ({mshr_wsel, mshr_tag, mshr_idx, mshr_pmask}),
.dequeue_ready (mshr_deq_ready),
// allocate
.allocate_valid (mshr_allocate_st0),
.allocate_addr (addr_st0),
@ -419,18 +431,6 @@ module VX_cache_bank #(
.lookup_addr (addr_st0),
.lookup_matches (mshr_matches_st0),
// fill
.fill_valid (mem_rsp_fire),
.fill_id (mem_rsp_id),
.fill_addr (mem_rsp_addr),
// dequeue
.dequeue_valid (mshr_deq_valid),
.dequeue_id (mshr_deq_id),
.dequeue_addr (mshr_deq_addr),
.dequeue_data ({mshr_wsel, mshr_tag, mshr_idx, mshr_pmask}),
.dequeue_ready (mshr_deq_ready),
// release
.release_valid (mshr_release_st1),
.release_id (mshr_id_st1)

10
hw/rtl/cache/VX_cache_mshr.sv vendored
View file

@ -41,16 +41,16 @@ module VX_cache_mshr #(
output wire [MSHR_ADDR_WIDTH-1:0] allocate_id,
output wire allocate_ready,
// fill
input wire fill_valid,
input wire [MSHR_ADDR_WIDTH-1:0] fill_id,
output wire [`CS_LINE_ADDR_WIDTH-1:0] fill_addr,
// lookup
input wire lookup_find,
input wire lookup_replay,
input wire [`CS_LINE_ADDR_WIDTH-1:0] lookup_addr,
output wire [MSHR_SIZE-1:0] lookup_matches,
// fill
input wire fill_valid,
input wire [MSHR_ADDR_WIDTH-1:0] fill_id,
output wire [`CS_LINE_ADDR_WIDTH-1:0] fill_addr,
// dequeue
output wire dequeue_valid,

23
hw/rtl/libs/VX_elastic_buffer.sv
View file

@ -29,6 +29,29 @@ module VX_elastic_buffer #(
assign data_out = data_in;
assign ready_in = ready_out;
end else if (SIZE == 1) begin
reg [DATAW-1:0] data_out_r;
reg valid_out_r;
wire push = valid_in && ready_in;
wire stall_out = valid_out_r && ~ready_out;
always @(posedge clk) begin
if (reset) begin
valid_out_r <= 0;
end else begin
valid_out_r <= valid_in || stall_out;
end
if (push) begin
data_out_r <= data_in;
end
end
assign ready_in = ~valid_out_r || ready_out;
assign valid_out = valid_out_r;
assign data_out = data_out_r;
end else if (SIZE == 2) begin
VX_skid_buffer #(

5
hw/rtl/tex/VX_tex_lerp.sv
View file

@ -1,7 +1,9 @@
`include "VX_platform.vh"
`TRACING_OFF
module VX_tex_lerp (
module VX_tex_lerp #(
parameter LATENCY = 3
) (
input wire clk,
input wire reset,
input wire enable,
@ -11,6 +13,7 @@ module VX_tex_lerp (
output wire [7:0] out
);
`UNUSED_VAR (reset)
`STATIC_ASSERT(LATENCY == 3, ("invalid value"));
reg [15:0] p1, p2;
reg [15:0] sum;

17
hw/rtl/tex/VX_tex_sampler.sv
View file

@ -45,7 +45,6 @@ module VX_tex_sampler #(
VX_pipe_register #(
.DATAW (1 + REQ_INFOW + (NUM_LANES * 2 * `TEX_BLEND_FRAC) + (NUM_LANES * 4 * 32)),
.DEPTH (2),
.RESETW (1)
) pipe_reg0 (
.clk (clk),
@ -57,7 +56,9 @@ module VX_tex_sampler #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar j = 0; j < 4; ++j) begin
VX_tex_lerp tex_lerp_ul (
VX_tex_lerp #(
.LATENCY (3)
) tex_lerp_ul (
.clk (clk),
.reset(reset),
.enable(~stall_out),
@ -66,7 +67,9 @@ module VX_tex_sampler #(
.frac (req_blends_s0[i][0]),
.out (texel_ul[i][j*8 +: 8])
);
VX_tex_lerp tex_lerp_uh (
VX_tex_lerp #(
.LATENCY (3)
) tex_lerp_uh (
.clk (clk),
.reset(reset),
.enable(~stall_out),
@ -84,7 +87,7 @@ module VX_tex_sampler #(
VX_shift_register #(
.DATAW (1 + REQ_INFOW + (NUM_LANES * `TEX_BLEND_FRAC)),
.DEPTH (2),
.DEPTH (3),
.RESETW (1)
) shift_reg1 (
.clk (clk),
@ -96,7 +99,9 @@ module VX_tex_sampler #(
for (genvar i = 0; i < NUM_LANES; ++i) begin
for (genvar j = 0; j < 4; ++j) begin
VX_tex_lerp tex_lerp_v (
VX_tex_lerp #(
.LATENCY (3)
) tex_lerp_v (
.clk (clk),
.reset(reset),
.enable(~stall_out),
@ -112,7 +117,7 @@ module VX_tex_sampler #(
VX_shift_register #(
.DATAW (1 + REQ_INFOW),
.DEPTH (1),
.DEPTH (3),
.RESETW (1)
) shift_reg2 (
.clk (clk),