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minor updates

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This commit is contained in:
Blaise Tine 2021-03-28 04:00:20 -04:00
parent 0b2f2a27ac
commit 6514a3b782
3 changed files with 31 additions and 24 deletions
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2
hw/rtl/VX_gpu_unit.v
View file

@ -121,7 +121,7 @@ module VX_gpu_unit #(
VX_tex_unit #(
.CORE_ID(CORE_ID)
) texture_unit (
) tex_unit (
.clk (clk),
.reset (reset),
.tex_req_if (tex_req_if),

8
hw/rtl/tex_unit/VX_tex_addr.v
View file

@ -41,10 +41,10 @@ module VX_tex_addr #(
output wire [31:0] mem_req_PC,
output wire [`TEX_FILTER_BITS-1:0] mem_req_filter,
output wire [`TEX_STRIDE_BITS-1:0] mem_req_stride,
output wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr,
output wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_u,
output wire [`NUM_THREADS-1:0][`FIXED_FRAC-1:0] mem_req_v,
output wire [REQ_INFO_WIDTH-1:0] mem_req_info,
output wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr,
input wire mem_req_ready
);
@ -131,14 +131,14 @@ module VX_tex_addr #(
wire stall_out = mem_req_valid && ~mem_req_ready;
VX_pipe_register #(
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + REQ_INFO_WIDTH + (`NUM_THREADS * 4 * 32) + (2*`NUM_THREADS * `FIXED_FRAC)),
.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `TEX_FILTER_BITS + `TEX_STRIDE_BITS + (`NUM_THREADS * 4 * 32) + (2*`NUM_THREADS * `FIXED_FRAC) + REQ_INFO_WIDTH),
.RESETW (1)
) pipe_reg (
.clk (clk),
.reset (reset),
.enable (~stall_out),
.data_in ({valid_in, req_wid, req_tmask, req_PC, filter, log_stride, req_info, addr, u[0], v[0]}),
.data_out ({mem_req_valid, mem_req_wid, mem_req_tmask, mem_req_PC, mem_req_filter, mem_req_stride, mem_req_info, mem_req_addr, mem_req_u, mem_req_v})
.data_in ({valid_in, req_wid, req_tmask, req_PC, filter, log_stride, addr, u[0], v[0], req_info}),
.data_out ({mem_req_valid, mem_req_wid, mem_req_tmask, mem_req_PC, mem_req_filter, mem_req_stride, mem_req_addr, mem_req_u, mem_req_v, mem_req_info})
);
assign ready_in = ~stall_out;

45
hw/rtl/tex_unit/VX_tex_unit.v
View file

@ -28,7 +28,7 @@ module VX_tex_unit #(
reg [`TEX_WIDTH_BITS-1:0] tex_width [(1 << `TEX_MIP_BITS)-1:0];
reg [`TEX_HEIGHT_BITS-1:0] tex_height [(1 << `TEX_MIP_BITS)-1:0];
reg [`TEX_ADDR_BITS-1:0] tex_addr [`NUM_TEX_UNITS-1:0];
reg [`TEX_ADDR_BITS-1:0] tex_baddr [`NUM_TEX_UNITS-1:0];
reg [`TEX_FORMAT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1:0];
reg [`TEX_WRAP_BITS-1:0] tex_wrap_u [`NUM_TEX_UNITS-1:0];
reg [`TEX_WRAP_BITS-1:0] tex_wrap_v [`NUM_TEX_UNITS-1:0];
@ -36,11 +36,10 @@ module VX_tex_unit #(
// CSRs programming
for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
wire [`TEX_MIP_BITS-1:0] mip_waddr = tex_csr_if.write_data[24 +: `TEX_MIP_BITS];
always @(posedge clk ) begin
for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
always @(posedge clk) begin
if (reset) begin
tex_addr[i] <= 0;
tex_baddr[i] <= 0;
tex_format[i] <= 0;
tex_wrap_u[i] <= 0;
tex_wrap_v[i] <= 0;
@ -48,22 +47,16 @@ module VX_tex_unit #(
end begin
if (tex_csr_if.write_enable) begin
case (tex_csr_if.write_addr)
`CSR_TEX_ADDR(i) : tex_addr[i] <= tex_csr_if.write_data[`TEX_ADDR_BITS-1:0];
`CSR_TEX_ADDR(i) : tex_baddr[i] <= tex_csr_if.write_data[`TEX_ADDR_BITS-1:0];
`CSR_TEX_FORMAT(i) : tex_format[i] <= tex_csr_if.write_data[`TEX_FORMAT_BITS-1:0];
`CSR_TEX_WRAP(i) : begin
tex_wrap_u[i] <= tex_csr_if.write_data[0 +: `TEX_WRAP_BITS];
tex_wrap_v[i] <= tex_csr_if.write_data[`TEX_WRAP_BITS +: `TEX_WRAP_BITS];
end
`CSR_TEX_FILTER(i) : tex_filter[i] <= tex_csr_if.write_data[`TEX_FILTER_BITS-1:0];
`CSR_TEX_MIPOFF(i) : begin
tex_mipoff[mip_waddr] <= tex_csr_if.write_data[`TEX_MIPOFF_BITS-1:0];
end
`CSR_TEX_WIDTH(i) : begin
tex_width[mip_waddr] <= tex_csr_if.write_data[`TEX_WIDTH_BITS-1:0];
end
`CSR_TEX_HEIGHT(i) : begin
tex_height[mip_waddr] <= tex_csr_if.write_data[`TEX_HEIGHT_BITS-1:0];
end
`CSR_TEX_MIPOFF(i),
`CSR_TEX_WIDTH(i),
`CSR_TEX_HEIGHT(i):;
default:
assert(tex_csr_if.write_addr >= `CSR_TEX_BEGIN(0)
&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES));
@ -73,6 +66,20 @@ module VX_tex_unit #(
end
end
for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
wire [`TEX_MIP_BITS-1:0] mip_waddr = tex_csr_if.write_data[24 +: `TEX_MIP_BITS];
always @(posedge clk) begin
if (tex_csr_if.write_enable && tex_csr_if.write_addr == `CSR_TEX_MIPOFF(i))
tex_mipoff[mip_waddr] <= tex_csr_if.write_data[`TEX_MIPOFF_BITS-1:0];
if (tex_csr_if.write_enable && tex_csr_if.write_addr == `CSR_TEX_WIDTH(i))
tex_width[mip_waddr] <= tex_csr_if.write_data[`TEX_WIDTH_BITS-1:0];
if (tex_csr_if.write_enable && tex_csr_if.write_addr == `CSR_TEX_HEIGHT(i))
tex_height[mip_waddr] <= tex_csr_if.write_data[`TEX_HEIGHT_BITS-1:0];
end
end
// mipmap attributes
wire [`NUM_THREADS-1:0][`TEX_MIPOFF_BITS-1:0] tex_mipoffs;
@ -111,7 +118,7 @@ module VX_tex_unit #(
VX_tex_addr #(
.REQ_INFO_WIDTH (REQ_INFO_WIDTH_A)
) _tex_addr (
) tex_addr (
.clk (clk),
.reset (reset),
@ -128,7 +135,7 @@ module VX_tex_unit #(
.wrap_u (tex_wrap_u[tex_req_if.unit]),
.wrap_v (tex_wrap_v[tex_req_if.unit]),
.base_addr (tex_addr[tex_req_if.unit]),
.base_addr (tex_baddr[tex_req_if.unit]),
.mip_offsets (tex_mipoffs),
.log_widths (tex_widths),
.log_heights (tex_heights),
@ -142,10 +149,10 @@ module VX_tex_unit #(
.mem_req_PC (mem_req_PC),
.mem_req_filter (mem_req_filter),
.mem_req_stride (mem_req_stride),
.mem_req_addr (mem_req_addr),
.mem_req_u (mem_req_u),
.mem_req_v (mem_req_v),
.mem_req_info (mem_req_info),
.mem_req_addr (mem_req_addr),
.mem_req_ready (mem_req_ready)
);
@ -230,7 +237,7 @@ module VX_tex_unit #(
if (tex_csr_if.write_enable
&& (tex_csr_if.write_addr >= `CSR_TEX_BEGIN(i)
&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(i+1))) begin
$display("%t: core%0d-tex_csr: csr_tex%d_addr, csr_data=%0h", $time, CORE_ID, i, tex_addr[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_addr, csr_data=%0h", $time, CORE_ID, i, tex_baddr[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_width, csr_data=%0h", $time, CORE_ID, i, tex_width[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_height, csr_data=%0h", $time, CORE_ID, i, tex_height[i]);
$display("%t: core%0d-tex_csr: csr_tex%d_format, csr_data=%0h", $time, CORE_ID, i, tex_format[i]);